Новини світу мікро- та наноелектроніки

Microchip’s MD-990-0011-B M.2 plug-in timing module delivers precise synchronization for data center servers and 5G vRAN. Developed with Intel, it is compatible with Xeon 6 SoC–based server platforms. It leverages Intel’s vRAN architecture for low-latency time synchronization in distributed AI workloads and real-time applications.

Customized for Intel-based reference designs, the device supports automatic source selection and locking across GNSS, Synchronous Ethernet (SyncE), and PTP networks. Its integrated SyncE synthesizer includes two independent digital PLL channels: one for time and one for frequency. Additional components include an OCXO supporting 4 or 8 hours of 1.5-µs holdover, along with a temperature sensor, EEPROM, and a crystal oscillator to help maintain low jitter.

By integrating these components into a single plug-in module, the MD-990-0011-B simplifies server design and reduces complexity. Its modular approach also speeds installation and maintenance, helping minimize downtime.

The MD-990-0011-B is available in production quantities from Microchip and authorized distributors.

MD-990-0011-B product page 

Microchip Technology 

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The GD32F5HC series of 32-bit general-purpose MCUs from GigaDevice features a 200-MHz Arm Cortex-M33 core with DSP and FPU capabilities. Hardware-based security, ample on-chip memory, and integrated peripherals target both consumer and industrial designs.

On-chip memory includes 2 MB of flash, 320 KB of SRAM, and 32 KB of instruction cache. Multichannel DMA controllers handle complex algorithms, graphics frameworks, and high-speed data flows. QSPI and SPI interfaces enable external PSRAM and flash expansion at up to 45 MHz.

Peripherals include a 12-bit ADC with an integrated temperature sensor and an infrared interface for analog signal processing. Multiple 16-bit and 32-bit timers, along with a real-time clock, enable waveform generation, motor control, and synchronized multi-axis operation.

Security features combine Arm TrustZone with a 2-kbit eFuse for key storage and hardware cryptographic accelerators. Secure boot, storage, debugging, and firmware updates help maintain system integrity across the device lifecycle.

The MCUs operate from a 3.3-V supply and offer four power-saving modes: sleep, deep sleep, standby, and SRAM sleep. Devices are available in BGA64 and QFN56 packages with up to 54 GPIOs.

GD32F5HC product page

GigaDevice

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Combining an accurate temperature sensor with a standard digital multimeter can make an inexpensive, accurate, and useful thermometer.

A recent Design Idea, BJT is accurate sensor for absolute temperature in Kelvin and Rankine, was based on a 1991 application note (PDF) by a legendary guru, the forever remembered Jim Williams. In his article, Williams demonstrated that, when used as ΔVbe sensors, ordinary unselected transistors give temperature readings accurate to a fraction of a degree without calibration:

“…randomly selected 2N3904s and 2N2222s … showed less than 0.4°C spread over 25 devices from various manufacturers.”

Wow the engineering world with your unique design: Design Ideas Submission Guide

As shown in BJT is accurate…, the basic math of ΔVbe can be cooked down to a simple and easy to remember (hah!) linear-in-absolute-temperature relationship: ΔVbe/°C = Log10(Current-ratio)/5050.  Therefore, if we want any given ΔVbe/°C, the required is just Current-ratio = 10^(5050 ΔVbe/°C). 

For example, for ΔVbe/°C = 100uV, Current-ratio = 10^(5050 * 100uV) = 10^(0.5050) = 3.20.  This ratio is implemented in Figure 1’s simple circuit for a 100uV per Kelvin output.

Figure 1 An ordinary BJT Q1 makes an accurate 100uV per unit Kelvin absolute temperature sensor.

Okay. So. What’s it good for? One plausible application is, as frequent contributor Nick Cornford has shown in several ingenious designs:

• Newer, shinier DMM RTDs—part 1 and part 2
• Dropping a PRTD into a thermistor slot—impossible?
• DIY RTD for a DMM

that the combination of an accurate temperature sensor with a standard digital multimeter can make an inexpensive, accurate, and useful thermometer.

Nick’s favorite sensor is the super-versatile platinum RTD, but as Williams showed, a humble (and super cheap) 2N3904 (or similar) BJT might also fill the bill. That’s assuming that its package-limited −55 to +150°C temperature range is adequate. And that’s also assuming that it gets a little help from its friends, such as Figure 2’s zero-drift op amp that boosts the output span to a DMM-friendly 1mV per unit Celsius, Kelvin, Fahrenheit, and Rankine.

Figure 2 A zero drift, 5uV max offset A1 rescales 100uV/°K by 10x to 1mV/°C and by 18x to 1mV/°F.

Of course, Kelvin and Rankine absolute temperature measurements are absolutely less frequently useful than the common Celsius and Fahrenheit scales…which is where Figure 3 comes in:

Figure 3 Connect the DMM’s plus lead to the appropriate figure 2 output, and the minus lead to the correct precision 0° offset terminal, to re-zero 273K to 0°C and 460R to °0F.

V+ can be anywhere from 3 to 6 volts.  Current consumption at 3v is barely more than 1mA, dominated by the Z1 shunt reference, so two AAs will support 2000 hours (nearly three months) of continuous operation.  A single CR2032 lithium coin will hold up for 10 non-stop days.

Thanks, Nick and Jim!

Stephen Woodward‘s relationship with EDN’s DI column goes back quite a long way. Over 200 submissions have been accepted since his first contribution back in 1974.  They have included best Design Idea of the year in 1974 and 2001.

Related Content 

• BJT is accurate sensor for absolute temperature in Kelvin and Rankine
• Newer, shinier DMM RTDs—part 1
• Newer, shinier DMM RTDs—part 2
• Dropping a PRTD into a thermistor slot—impossible?
• DIY RTD for a DMM

 

The post ΔVbe + DMM = Celsius, Kelvin, Fahrenheit, and Rankine thermometer appeared first on EDN.

Photonic application-specific integrated circuit (PASIC) chip designer and manufacturer OpenLight of Goleta, Santa Barbara, CA, USA (which launched as an independent company in 2022, introducing the first open silicon photonics platform with heterogeneously integrated III-V lasers, modulators, amplifiers and detectors) has raised an additional $50m in a Series A-1 round. Including the $34m Series A funding secured in August 2025, total funding is now $84m...

Adding more compute is no longer enough to maximize AI training and inference performance in today’s AI factories. The real challenge is how efficiently data flows through AI systems, not raw processing power.

Training remains the foundation of AI development, and maximizing throughput across large clusters is critical as models internalize structure, learn statistical relationships, and establish a baseline for downstream workloads. Inference shifts the focus, demanding ultra-low latency and high-reliability token generation. Both of these phases are characterized by exponential scale.

Training trillion-parameter models and performing inference that requires enormous amounts of contextual information places significant pressure on the “plumbing” of modern computing platforms. In this environment, the efficiency, predictability, and speed of data movement across the CPUs, accelerators, memory, and I/Os that compose these AI systems have become the true bottleneck.

Eliminating data bottlenecks is now dependent on optimizing interconnect bandwidth. The interconnects themselves are crucial to system success, with PCI Express (PCIe), specifically PCIe 7.0, being a prime example.

PCIe’s role in multi-GPU scale-up systems

For more than a decade, PCIe has been the backbone of multi-GPU server systems due to its universal and extensible interconnect that ties all compute and I/O devices together inside a node, such as GPU-to-DPU/NIC, or GPU-to-switch. Even as newer, high-bandwidth GPU-to-GPU fabrics and proprietary accelerator meshes have emerged, systems continue to rely on PCIe for baseline connectivity, system bring-up, and data movement across system components.

Announced in June 2025, PCIe 7.0 doubles link bandwidth to 128 GT/s, delivering up to 512 GB/s of bi-directional throughput per x16 connection. While this increased bandwidth helps alleviate I/O bottlenecks for AI computing, fully utilizing PCIe 7.0 for inference workloads also requires minimizing latency across the fabric.

Multiple inference streams sharing the same PCIe path may cause head-of-the-line blocking due to unnecessary serialization. This results in delays in unrelated traffic, which impacts overall system efficiency.

To maintain low latency and fully utilize PCIe 7.0 bandwidth under parallel workloads, a more flexible ordering model is required.

Baseline PCIe ordering rules: Why serialization exists

First, it’s helpful to understand PCIe’s baseline ordering rules. Most systems using early PCIe generations—from 2.5 GT/s in PCIe 1.0 to 8 GT/s in PCIe 3.0—relied on simple point‑to‑point connections supporting a single application or device context. As a result, the PCIe protocol strictly enforced baseline ordering rules to ensure that the results of memory operations are presented in an order that matches software expectations.

Within a single traffic class, PCIe groups transaction-layer packets (TLPs) into posted, non-posted, and completion categories, each governed by defined ordering constraints. Posted requests are memory writes (MWR) and messages (MSG) that operate without needing a completion, while non‑posted requests include memory reads (MRD) and configuration transactions that must receive a completion. To simplify the discussion, the focus is on the main traffic. Only MRD requests, MWR requests, and read completions (CPL) are described in the ordering rules.

Table 1 Baseline ordering rules highlight the relationship between the current and previous requests. Source: Cadence Design Systems

Table 1 shows the relationship between the current requests in rows A, B, and C and the previous requests in columns 2, 3, and 4. The “Y/N” in the table is the abbreviation of “Yes/No” that implies the row’s request/completion “may pass” the column’s request/completion type.

To understand the A3 deadlock scenario detailed in Figure 1, assume the root complex (RC) issues an MRD request (1) followed by an MWR request (2) toward the endpoint (EP) device. A deadlock can occur when the RC exhausts the completion credits, and its completion buffer becomes full (3). The RC is unable to accept new completions (4) associated with the outstanding non-posted MRD (1).

Figure 1 In A3 deadlock, the RC completion queue (CQ) is full, preventing it from returning completion to release the MRD from blocking the MWR request. Cadence Design Systems

Because strict ordering prevents the newer MWR (2) from bypassing the unresolved MRD (1) until its completion (4) is received, the RC’s transmit request path is also blocked. This prevents the issuance of MWR (2) from propagating to the EP link (5). This head-of-the-line blocking creates circular dependency, which stalls internal request queue draining and completion acceptance. Unless the MWR is allowed to bypass the MRD, a deadlock results.

For the C3 deadlock scenario illustrated in Figure 2, assume both the RC and EP issue many non-posted read requests (1), which aggressively fill both the RX and TX request queues (RQ) (2) and prevent them from accepting any new MRD requests (3). Meanwhile, the completions (4) are returned for pending MRD requests (1) in the opposite direction, but they can’t be forwarded to fulfill the previous pending MRD request (1). This is because they arrived behind the new MRD request (3). If the completion is not allowed to bypass the previous MRD requests in the same direction, it will result in a deadlock.

Figure 2 A C3 deadlock occurs if both the RX and TX request queues are full, and the completion is not allowed to pass the previous MRD request. Source: Cadence Design Systems

For A2 (Row A, column 2), B2, and C2, MWR, MRD, and CPL requests cannot pass MWR requests to maintain correctness. These three scenarios are illustrated in Figure 3, Figure 4, and Figure 5, respectively.

Figure 3 In A2, current MWR requests cannot pass previous MWR requests. Source: Cadence Design Systems

Figure 4 In B2, current MRD requests cannot pass previous MWR requests. Source: Cadence Design Systems

Figure 5 In C2, current completion requests cannot pass previous MWR requests. Source: Cadence Design Systems

However, A3 and C3 illustrate that both MWR requests and completions can pass an earlier MRD request to avoid a deadlock. This is shown in Figure 6 and Figure 7.

Figure 6 In A3, MWR requests are allowed to bypass previous MRD requests to avoid a deadlock. Source: Cadence Design Systems

Figure 7 In C3, completions are allowed to bypass previous MRD requests to avoid a deadlock. Source: Cadence Design Systems

For B3, the current MRD request might be bypassed or blocked by the previous MRD request. For A4 and B4, the current MWR or MRD request is permitted to pass the previous completion or be blocked by the completion.

Figure 8 describes both the C4a and C4b scenarios. The yellow and green completions belong to the pending yellow (RD1) and green (RD0) MRD requests, respectively. If current completions belong to different MRD requests, they can pass each other as CPL10 passes CPL01 (C4a scenario). However, if they belong to the same MRD request as in the C4b scenario, they must follow the order and cannot pass previous completions (CPL00 followed by CPL01, and CPL10 followed by CPL11).

Figure 8 In C4, completions of the same MRD request can pass completions of the previous MRD, and completions of the same MRD request must follow in order. Source: Cadence Design Systems

Strict ordering: A safe but conservative baseline

PCIe’s default strict ordering rules ensure safe producer-consumer software behavior. Under strict ordering, the system observes transactions issued by a requester in program order. Posted writes must be completed before subsequent read completions of subsequent pending MRD requests.

However, this global ordering discipline is conservative. It causes unrelated transactions to wait for one another, even when there is no true data dependency. For instance, this can occur when different functions access data from different memory segments in the host or local memory. As PCIe link speeds increase, this approach becomes a scalability bottleneck because it causes head-of-the-line blocking of unrelated serialized traffic and underutilizes the available bandwidth.

Why relaxed ordering is needed

Relaxed ordering loosens these global constraints. When a transaction is marked as relaxed, it tells the PCIe fabric that this MRD or MWR request does not need to participate in the default system‑wide ordering guarantees. Relaxed ordering improves throughput and reduces latency by enabling certain transactions to be reordered. The key point is that relaxed ordering removes unnecessary ordering barriers between independent operations.

However, it still preserves most of the transactional correctness, such as ensuring the completion order of the same MRD requests. This is especially valuable for workloads such as prefetching, polling reads, or accelerator traffic, where software already explicitly manages synchronization. Relaxed ordering addresses the performance loss caused by overly strict global rules. However, it treats ordering as a binary choice, either fully ordered or globally relaxed.

Why ID‑based ordering is also necessary

Relaxed ordering alone is too coarse‑grained for modern devices. High‑performance endpoints, such as GPUs, NICs, and NVMe controllers, generate traffic from many independent sources, including queues, processes, virtual machines, or process address space IDs (PASIDs).

These sources often require ordering within themselves, but not between each other. With ID‑based ordering, PCIe maintains ordering among transactions that share the same requester ID or PASID, while permitting reordering across different IDs. In effect, it scopes ordering guarantees to a logical context rather than imposing them system‑wide.

This allows transactions of the same function or context to maintain the correct program semantics, while the fabric freely parallelizes traffic across independent functions or contexts. Without ID-based ordering, systems would be forced to choose between full serialization for safety or full relaxation with no per‑context guarantees.

Attribute-based ordering: Relaxed and ID-based ordering

Because the PCIe fabric already enforces ordering semantics for both relaxed ordering and ID‑based ordering, system software and device logic influence these behaviors by setting attributes in the TLP headers rather than redefining the rules themselves. Relaxed ordering and ID‑based ordering address different dimensions of the same problem, which is why both are required to meaningfully relax PCIe’s strict ordering rules.

Relaxed ordering removes unnecessary global ordering constraints between different classes of traffic, enabling better scheduling and reducing head-of-the-line blocking. In contrast, ID‑based ordering refines ordering to the level of a requester or context, preserving correctness where the associated software expects it while eliminating artificial dependencies elsewhere.

Together, they allow PCIe to scale with modern parallel workloads. While strict ordering provides a safe default, relaxed ordering removes global bottlenecks, and ID‑based ordering preserves local semantics without sacrificing concurrency. This combination allows PCIe to support today’s accelerators, virtualized I/Os, and high‑throughput devices without breaking the programming models that software relies on.

Table 2 Here is a highlight of the ordering rules for relaxed ordering and ID-based ordering. Source: Cadence Design Systems

Table 2 specifies the ordering rules for relaxed ordering and ID-based ordering. The “Y/N” in the table is the abbreviation for “yes/no”, indicating whether the row’s request/completion “may pass” the column’s request/completion type.

The key differences between the relaxed ordering and ID-based ordering rules detailed in Table 2 and the baseline rules shown earlier in Table 1 are A2, B2, and C2 vs. D2, E2, and F2, respectively. For baseline rules, current MWR, MRD, or completions are not allowed to pass previous MWR requests. However, relaxed ordering and ID-based ordering allow them to pass previous MWR requests if their request IDs—bus, device, function, and PASID—are different.

Vanessa Do is a senior product marketing manager for PCIe IP at Cadence with over 20 years of experience in PCIe design, system validation, and customer engagement. Her background spans PCIe protocol development, FPGA-based customer support, and leading cross‑functional teams to debug complex PCIe issues at the system level.

Editor’s Note

This is Part 1 of the article series about PCIe 7.0 fundamentals. Part 2 will explain why PCIe 7.0 bandwidth alone isn’t enough while highlighting the importance of addressing legacy ordering limitations with UIO.

The post PCIe 7.0 fundamentals: Baseline ordering rules appeared first on EDN.

These are a couple of auxiliary sensor enclosures I made for my Farmbot. The first box is power distribution and housing for i/o of the RS485 7 in 1 soil sensor and an array of moisture sensors. All through USBC ports and RJ45. 24v for the 7 in 1, 5v for the extra USB power ports and the Max485. Not pictured is the max485 circuit and the associated wiring. Box two is a relay enclosure to control 120v pumps and lights. All with custom faceplates to identify the ports so nobody mistakes the RS485 port for a standard USBC. Pretty simple stuff but it's still fun. submitted by /u/BeatAdditional6914 [link] [comments]

Deepak Shankar, founder of Mirabilis Design and developer of VisualSim Architect platform for chip and system designs, has created this cartoon for electronics design engineers.

The post The system architect’s sketchbook: The tree knows appeared first on EDN.

The drive toward greater accuracy, efficiency, and automation in manufacturing environments and smart factories is accelerating at an unprecedented pace. This includes the deployment of advanced robotic systems, including autonomous mobile robots (AMRs) and collaborative robots working alongside humans, known as cobots.

The future of manufacturing depends on safe and seamless human-robot collaboration, requiring robots to dynamically adapt to the presence and movements of human workers. Maximizing the potential of these collaborative environments demands a critical capability: fast, accurate, and reliable 3D spatial sensing.

Traditional sensing methods often fall short in dynamic industrial settings that require reliable performance and high resolution. So, precision laser technologies, particularly time-of-flight (ToF) and frequency modulated continuous wave (FMCW) lidar, are emerging as key technologies, providing the detailed environmental sensing technology necessary for robots to navigate safely around personnel and to optimize workflows without compromising human safety.

Advanced lidar systems enable highly precise obstacle detection, distance measurement and real-time mapping, facilitating safer interaction between humans and robots. Design engineers are integrating the technology into automated factory systems to address the challenges of modern manufacturing while boosting accuracy, operational safety, and overall production efficiency.

How ToF lidar uses light to measure distance in smart factories

ToF lidar delivers highly accurate distance measurements by timing the round-trip travel of laser pulses, creating precise 3D point clouds of all objects in the surrounding environment—giving AMRs and cobots a detailed, real-time picture of their workspace. A ToF lidar system emits a pulse of invisible laser light onto an object and receives the reflected pulse back.

The system then calculates the distance between the transmitter/receiver and the object based on how long that round trip takes. Figure 1 shows a high-level diagram of a single-point optical ToF lidar system.

Figure 1 Distance measurement is shown between the object and the ToF lidar. Source: Texas Instruments

Cameras and ultrasonic sensors fall short in dynamic applications

Camera-based systems and ultrasonic sensing cannot match the speed and precision that ToF lidar delivers for distance measurement. While cameras excel at extracting texture and color information from their environment, they struggle with depth perception, especially in challenging lighting conditions.

Cameras often require illumination of the entire area of interest to function accurately, while ToF lidar systems, such as the module on top of the robot in Figure 2, supply their own illumination in the form of laser pulses. Most ToF lidar systems use laser light with a 905-nm wavelength invisible to humans and can sense objects over 100 m away while remaining eye-safe. Some scanning ToF lidar systems can provide 360-degree distance measurements, making them particularly useful in AMR applications where spatial awareness in all directions matters.

Figure 2 AMR is equipped with a ToF lidar module on top to supply illumination in the form of laser pulses. Source: Texas Instruments

Obtaining accurate 3D distance information from cameras requires complex and computationally expensive image processing algorithms that can introduce latency and potential inaccuracies. Camera-based systems also require good lighting conditions to operate properly.

Due to light dispersion, most camera-based systems deliver accurate distance measurements only for objects a few meters away and lose accuracy at greater distances unless design engineers use large, costly lenses.

Ultrasonic sensors offer a low-cost solution for proximity detection, but suffer from limited range, poor accuracy, and susceptibility to interference from noise and surface characteristics. Accuracy for distance measurement typically falls within a range of several centimeters, and environmental factors such as temperature, humidity, and the object surface texture heavily influence results. Additionally, a wide field of view makes it difficult to pinpoint the exact location of an obstacle, increasing the risk of false positives.

FMCW lidar adds velocity measurement for safer human-robot collaboration

FMCW lidar is quickly emerging as a superior sensing solution for smart factories, particularly in collaborative robotic applications.

Unlike ToF, which measures distance based on the time it takes a laser pulse to return, FMCW lidar transmits a continuous wave laser that varies in frequency. By analyzing the frequency difference between the transmitted and received signals, the system applies the Doppler principle to directly measure both distance and velocity with extremely high precision.

This velocity measurement provides critical advantage in environments where robots work alongside humans and other robots, enabling a proactive response to movement and significantly reducing collision and injury risks. FMCW lidar also achieves longer distance measurement range at the same laser power as ToF-based systems. Figure 3 shows a high-level diagram of an FMCW lidar system.

Figure 3 The high-level diagram shows how an FMCW lidar system works. Source: Texas Instruments

In high-throughput manufacturing environments utilizing conveyor belts, FMCW lidar offers significant advantages over traditional camera-based vision systems for object detection and tracking.

Camera-based systems rely on image processing and pattern recognition, which can be computationally intensive and sensitive to object orientation. Conversely, FMCW lidar directly measures distance and velocity regardless of these factors, enabling quicker and more reliable detection even with fast-moving objects.

FMCW lidar’s ability to create a dense 3D point cloud allows engineers to determine accurate size and shape without complex image analysis, significantly increasing overall manufacturing line throughput and system accuracy.

Driving what’s next in smart factory automation

The increasing demand for automation, efficiency, and safety in modern manufacturing is driving the rapid adoption of advanced sensing technologies such as ToF and FMCW lidar. Both technologies offer substantial advantages over camera-based vision systems and ultrasonic sensors in dynamic environments where human-robot collaboration takes priority.

ToF lidar provides accurate 3D spatial data for reliable obstacle detection and precise distance measurements. FMCW lidar further elevates performance through the direct measurement of both distance and velocity, crucial for proactive collision avoidance and enhanced safety.

Companies such as Texas Instruments provide essential semiconductor building blocks such as transimpedance amplifiers, laser drivers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and a comprehensive range of power products that are vital for designing and building high-performance ToF and FMCW lidar systems.

Ongoing innovation in laser technology and signal processing promises continued advancements in lidar capabilities, positioning it as a cornerstone technology in the evolution of smart factories and industrial automation.

Anthony Vaughan is marketing manager for high-speed amplifiers at Texas Instruments.

 

 

Special Section: Smart Factory

• Rethinking machine vision in industrial automation
• Smart factory: The rise of PoE in industrial environments

The post Precision lasers boost safety and efficiency in smart factories appeared first on EDN.

Leveraging a prior fixture design with different lab equipment once again enables highly reliable results.

High resolution bench digital multimeters (DMMs) are commonplace now in most work labs, even trickling down to home labs and one-person shops! These DMMs are great for all sorts of measurements, including those of low Z components when utilizing the popular 4-wire Kelvin-type probes and clips.

Wow the engineering world with your unique design: Design Ideas Submission Guide

However, attempting to measure low Z SMD components can be challenging even with the best probes and clips, thereby explaining why I developed a specialized custom fixture for bench-type LCR meters. This fixture has subsequently proven quite valuable when measuring various SMD inductors, capacitors and resistors. The thought of using a similar concept for high-resolution DMMs with four banana type inputs therefore naturally occurred to me. Specifically, since I’d already created custom PCBs with lever arm-toggling capabilities for holding SMDs in place, why not utilize the same PCB and lever arm concepts for DMM use?

DMMs require banana plugs as inputs; high-resolution DMM models have four total. As with the custom LCR meter fixture, my not wanting to have any potentially tangling cables would instead require a somewhat direct four-wire connection to the DMM utilizing banana plugs. Various bare banana plug options are available, such as the ones used in the Tektronix 577 adapter, along with commonplace ones found in audio applications. Since the audio types were handy, they’re what I used.

Mechanical support for the four banana plugs and the custom PCB was provided by a custom developed 3D-printed enclosure (Figures 1-3). The connections between the PCB and banana plugs were originally made by spade lugs (shown), but this approach proved difficult when tightening down the banana plugs. Instead, I later utilized direct-soldered wire connections.

Figure 1 Adapting a tried-and-true PCB design to a different kind of test and measurement equipment proved straightforward.

Figure 2 The design approach leverages commonplace audio banana plug.

Figure 3 The resultant fixture is compact and rugged.

Operation with low Z SMD components such as 2512 precision metal film resistors is possible with very good repeatability and stability, even on older DMMs such as the HP/AG34401A (Figures 4-6)!

Figure 4 The fixture delivers highly accurate, stable and repeatable measurement results.

Figure 5 This time, the fixture is being used in a full enclosed fashion.

Figure 6 The fixture works well even with legacy DMMs.

This custom fixture has been quite useful in my small home office/lab and didn’t cost me a week’s salary….actually, my week’s salary now won’t even buy me a coffee, since I’m now semi-retired, but you get the point! Hopefully, others will also find this fixture useful with their high-resolution bench DMMs.

Michael A Wyatt is a life member with the IEEE and has continued to enjoy electronics ever since his childhood. Mike has a long career spanning Honeywell, Northrop Grumman, Insyte/ITT/Ex-elis/Harris, ViaSat and retiring (semi) with Wyatt Labs. During his career he accumulated 32 US Patents and in the past published a few EDN articles including Best Idea of the Year in 1989.

Related Content

• Custom DIY LCR SMD fixture for low-Z components
• DIY custom Tektronix 576 & 577 curve tracer adapters
• DMM Plug-In Test Resistor with temperature sensing

 

The post Custom DIY DMM SMD fixture for low Z measurements appeared first on EDN.

Intelligent power and sensing technology firm onsemi of Scottsdale, AZ, USA and China-based Geely Auto Group Co Ltd have expanded their global strategic collaboration aimed at accelerating the development of next-generation electric and hybrid vehicles. The partnership deepens system-level integration of onsemi’s EliteSiC silicon carbide technologies across Geely’s vehicle platforms to drive faster, more efficient EV development...

Built this last year based on Ben Eater’s 8-bit computer design using 74LS series ICs on breadboards. Implemented core modules including registers, ALU, program counter, memory address register, and control logic. The LEDs are used to visualize bus states and output during execution. Biggest challenges were signal stability and debugging wiring issues across multiple modules. Getting consistent clock behavior also took some iteration. Overall, it was a great hands-on way to understand how a simple CPU operates at the hardware level. submitted by /u/mapfolds [link] [comments]

Opto-semiconductor device maker Seoul Viosys Co Ltd (SVC, a subsidiary of South Korean LED maker Seoul Semiconductor Co Ltd) is accelerating its entry into the next-generation photonics market supported by its proprietary ‘No-wire’ and ‘No-package’ fundamental patents — essential technologies for micron (μm)-scale miniaturization of opto-semiconductors — as well as its vertical-cavity surface-emitting laser (VCSEL) technology...

China-based Innoscience (Suzhou) Technology Holding Co Ltd, which manufactures GaN-on-silicon power chips on 8” silicon wafers says that it has received two favorable judgments from the Beijing Intellectual Property Court in patent administrative litigation cases. The court fully upheld the validity of Innoscience’s two core invention patents related to gallium nitride (GaN) technology and rejected the invalidation requests of Infineon Technologies AG of Munich, Germany...

Aeluma Inc of Goleta, CA, USA has appointed Willy Rachmady Ph.D. as its VP of strategic partnerships and ecosystem, reporting directly to president & CEO Jonathan Klamkin Ph.D. He will lead foundry and ecosystem partnerships, customer engineering, and the firm’s technology commercialization strategy spanning silicon photonics and compound semiconductor platforms...

Indium Corp of Clinton, NY, USA (a supplier of refined gallium, germanium, indium and other specialty technology metals) has been awarded a $3.2m grant by the U.S. Department of Energy’s (DOE) Office of Critical Minerals and Energy Innovation (CMEI) to develop a domestic process for recovering high-purity gallium from manufacturing by-products — a critical step toward establishing a secure, domestic supply chain for a material essential to modern defense systems, semiconductors, and advanced electronics...

Intelligent power and sensing technology firm onsemi of Scottsdale, AZ, USA has announced an expanded strategic collaboration with China-based car maker NIO Inc to advance next-generation electric vehicle (EV) platforms. Building on a multi-year partnership, the firms are more closely engaging to accelerate NIO’s transition from 400V to 900V architectures, enabled by onsemi’s latest EliteSiC enhanced M3e technology...

Mineral exploration company Volta Metals Ltd of Toronto, Canada (which owns, has optioned and is currently exploring a critical minerals portfolio of rare-earths, gallium, lithium, cesium and tantalum projects in Ontario) has received approval for funding of up to $215,000 under the Ontario Junior Exploration Program (OJEP). The funding will support eligible exploration expenditures incurred in 2025 and the first two months of 2026 at its 4750-hectare Springer Rare Earth Element (REE) and Gallium Project, located about 70km east of Sudbury, Ontario, with direct access via the Trans-Canada Highway and Highway 64...

I found a piece of a laptop with a fingerprint scanner from 2007 in a junk bin. Surprisingly, it works perfectly with Windows 11 and reads my fingerprint without any problems. It requires a 3.3-volt voltage regulator to power it. I 3D-printed the enclosure and came up with a pretty good device. submitted by /u/SpaceRuthie [link] [comments]

Increasing power demands in data centers demand high-efficiency, high-density power-conversion solutions.

Figure 1 shows a block diagram of power distribution inside an IT tray. A 48V bus bar goes down the back of the rack to distribute power to the IT trays. Inside each tray is hot-swap or e-fuse circuitry to limit inrush current during tray plug-in and to protect the upstream rack during tray failures. Intermediate bus converters (IBCs) convert 48V to the second-stage voltage, usually 12V or 6V. Final-stage multiphase buck voltage regulators complete power delivery by converting the second-stage voltage to the loads, with the majority of power going to sub-1V, high-current processors. In this edition of Power Tips, I will focus on the 48V IBC, covering design considerations, comparing topologies, and discussing system trade-offs of various approaches.

Figure 1 48V IT tray power distribution. Source: Texas Instruments

The IBC power distribution network offers a wide range of power-conversion approaches inside an IT tray (Reference 1). As the system architect, you have three main design choices:

• A modular or discrete solution (also known as chip-down design).
• Regulated, unregulated (also known as fixed ratio) or semiregulated IBC operation.
• The second-stage bus voltage to maximize system performance.

When selecting a modular or chip-down design power converter, your main trade-off will be power density vs. board design flexibility. Power modules, as shown in Figure 2a, are highly optimized solutions built on high-layer-count printed circuit boards (PCBs) (usually more than 16), offering prequalification and the highest power density. The drawbacks of power modules are a lack of flexibility, with fixed footprints and set features, as well as a higher cost per watt.

Chip-down designs, as shown in Figure 2b, are highly flexible solutions that offer footprint and feature freedom, with a lower cost per watt in high-volume production. Their drawbacks include longer upfront time and greater cost investments to qualify the design.

(a) (b)

Figure 2 48V IBC design examples of modular (a) and chip-down design (b) approaches. Source: Texas Instruments

When considering the output regulation of the IBC, your choice depends on two main factors: the load being powered and the operating range of the IBC’s input bus voltage. When the IBC directly drives 12V loads such as cooling fans, hard drives and Peripheral Component Interconnect Express cards, only a fully regulated output voltage (Reference 1) will ensure component safety. In modern data centers, the tray voltage has a more stable, narrow range, typically 40V to 60V. This narrow input range gives you the option to use higher-efficiency and higher-power-density fixed-ratio or semiregulated IBCs. The regulated second-stage voltage regulators following the IBC stage can absorb fixed-ratio IBC output voltage fluctuations.

Your third design choice is the second-stage voltage delivered by the IBC. Equation 1 determines system efficiency (ηsystem):

ηsystem = ηIBC x ηPDN x ηVR

For a given power load, decreasing the second-stage bus voltage will lower the IBC efficiency (ηIBC), because it must deliver more current at a lower voltage to provide the same output power. Similarly, for the motherboard power distribution network (PDN), which distributes current from the first-stage IBC to the second-stage voltage regulator, the PDN efficiency (ηPDN) will also decrease because of increased I2 x R ohmic losses. The benefit of a lower second-stage bus voltage is apparent when using final-stage, high-frequency, high-current voltage regulators with significantly reduced voltage-related switching losses. This results in higher second-stage efficiency (ηVR) and a potentially smaller size of the second stage.

Unlike a buck converter-dominated second-stage voltage regulator, a first-stage IBC has a wide range of power delivery approaches and thus a wider variety of power-conversion topologies available. In most modern IT applications, isolation for safety purposes is not required, so your power topology options increase further when you can consider transformerless options. Figure 3 shows four popular options for IBC module and chip-down designs.

The full-bridge converter shown in Figure 3a is a simple buck converter-derived transformer-isolated topology. The full-bridge converter’s strengths are ease of regulation and the ability to easily scale the intended output voltage by adjusting the transformer turns ratio for your chosen second-stage bus voltage. One drawback of the full-bridge converter is that transformer design is key to its performance, requiring a high-layer-count PCB that limits the topology to module-based designs. Another drawback of the full-bridge converter is that the primary devices are hard-switched, limiting power density and efficiency.

The transformer-isolated inductor-inductor-capacitor (LLC) converter shown in Figure 3b looks very similar to the full-bridge converter but uses an additional capacitor and two inductors to eliminate switching-related losses in the primary devices, enabling high efficiency and high power density (Reference 2). The LLC converter has the same transformer-related strength (an easily scalable output voltage) and weakness (it’s limited to module-based designs) as the full-bridge converter. The LLC converter operates with the highest efficiency at the resonant frequency set by the additional passive components (CR and LR), with efficiency decreasing as you move away from the resonant frequency to regulate the output voltage. For this reason, the LLC converter’s most common application in IBCs is fixed-ratio designs, always operating at the resonant frequency, ensuring the highest efficiency.

Two other popular topologies, the hybrid switched-capacitor (HSC) converter (Reference 3) shown in Figure 3c and the basic buck converter shown in Figure 3d, both offer benefits for chip-down designs because of their lack of AC-dependent power transformers. The HSC converter has a natural step-down ratio of 4-to-1, making it a strong candidate for high-efficiency 48V to 12V IBCs. The addition of flying capacitors limits the power density and hinders this converter’s operation in boost mode, making it a good fit for semiregulation, as regulating only occurs in step-down buck converter mode.

Because the HSC converter has a natural step-down ratio of 4-to-1, scaling the output voltage down further to an 8-to-1 6VOUT design (for example) is more challenging than it would be for the full-bridge and LLC converter options because the HSC converter must rely instead on a longer freewheeling period, requiring a larger output filter inductor, decreasing power density and efficiency.

The buck converter is the most common topology in power electronics, used exclusively in the second-stage voltage regulator, so it is natural to want to apply this simple and well-known approach to the IBC stage as well. The challenge with using a buck converter in the higher-voltage IBC application is that the power devices experience the highest voltage and current stresses when compared to the other topologies, limiting efficiency and power density.

(a) (b) (c) (d)

Figure 3 Popular IBC topologies: full-bridge converter (a); LLC converter (b); HSC converter (c); and buck converter (d). Source: Texas Instruments

Table 1 compares the different topologies and trade-offs.

  Full-bridge converter LLC converter HSC converter Buck converter

Module or chip-down design	Module	Module	Both	Both
Regulation type	Regulated	Fixed ratio	Semiregulated	Regulated
Efficiency	Medium	High	High	Low
Power density	Medium	High	Medium	Low
Output-voltage scalability	High	High	Medium	Medium
Complexity	Medium	High	High	Low

Table 1 Comparing IBC topology characteristics.

 With the maturation of gallium nitride (GaN) power devices (Reference 4), which have much lower switching-related charges compared to traditional silicon metal-oxide semiconductor field-effect transistors (MOSFETs), simpler topologies like the buck converter topology become more attractive and viable options for higher-voltage applications like IBCs. See Table 2.

  100V Texas Instruments GaN semiconductor 100V silicon MOSFET Difference

VDS (V)	100	100
RDS(on) (mΩ)	1.1	1.7	35% lower
QG (nC)	27	106	75% lower
QOSS (nC)	98	205	52% lower
QGD (nC)	2.5	26	90% lower
FOM1 = QG x RDS(on)	29.7	180.2	83% lower
FOM2 = QOSS x RDS(on)	107.8	348.5	69% lower
FOM3 = QGD x RDS(on)	2.75	44.2	93% lower
Package (mm x mm = mm2)	4 x 6.5 = 26 FET with gate driver	5 x 6 = 30 Discrete FET	13% smaller

Table 2 Comparison of 100V GaN and silicon-based IBC semiconductor options.

The IBC power distribution network offers the widest range of power-conversion approaches of the systems inside an IT tray for good reason. As power requirements and architectures rapidly evolve, the best way to optimize performance for 48V IBCs changes. And as additional variables such as highly improved GaN semiconductors get thrown into the equation, it becomes even more important to understand design considerations, topology comparisons and trade-offs.

References

1. Hsu, C., L. Olariu, S. Zou, et al. “48V Onboard Power Solution Requirements.” Open Compute Project, Version 1.0.0, Nov. 15, 2024.
2. McDonald, Brent. “Overview of a planar transformer used in a 1kW high-density LLC power module.” Texas Instruments technical article, 2025.
3. Li, C., and J.A. Cobos. “A Switched Capacitor and Autotransformer Hybrid Converter With DC Current in the Windings,” in IEEE Transactions on Power Electronics 37 (2), February 2022, pp. 1870-1884.
4. Gallium nitride (GaN) power stages, Texas Instruments.

David Reusch is a systems engineer on the data center team at Texas Instruments, specializing in power electronics. David has more than 20 years of experience in power electronics, ranging from cutting-edge gallium nitride (GaN) technology to high-reliability space-grade DC-DC converters. He received his B.S., M.S. and Ph.D. in electrical engineering from Virginia Tech.

 

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