Новини світу мікро- та наноелектроніки

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This is one real-life quest: How do we increase the output voltage of a step-up converter? If you have unlimited access to the right ICs, you are one lucky dog, but what if you don’t? Or maybe you are limited to a specific chip due to particular requirements, for instance, it is stable under some environmental conditions or, it has some specific features/interfaces or maybe, it’s easily accessible or cheap. Here, the ADP1611 step-up converter, is taken as an example. An application circuit can be seen in Figure 1.

Figure 1: An application circuit for the 5 to 15 V ADP1611 step-up regulator.

Wow the engineering world with your unique design: Design Ideas Submission Guide

It has a 20-V limit on its output voltage; this limit is mainly due to the output switch of the ADP1611. Adding a tiny GaN FET such as the EPC2051 to the ADP1611 can increase this limit to above 100 V (Figure 2).

Figure 2: A 5 V to 40 V step-up regulator with the addition of the GaN FET.

The cascode, shown in Figure 2 consists of an internal switch transistor and the newcomer FET; to have better frequency characteristics than the internal switch alone. So, if the newly added GaN FET also has much lower on-resistance (Rds(on)), then the internal switch, it will not reduce the efficiency.

To make the trick possible, the step-up converter should have an open drain (or open collector) output. Also, the connection of the inductor, diode, and the output of the chip must be reconfigured as shown in Figure 2. Diode D2 protects the internal switch from over-voltage.

Don’t forget to use this new value of the output voltage in your calculations. The output diode, capacitor, and inductor should also be rated to the new voltage. For the output diode, I used the HER107.

The addition of this GaN FET adds only 15 mΩ to the switch resistance of ADP1611 (0.23 Ω)—an increase of less than 10%. Please note, the gate-source voltage (VGS) of EPC2051 cannot exceed +6V, so be careful.

—Peter Demchenko studied math at the University of Vilnius and has worked in software development.

 Related Content

• GaN vs SiC: A look at two popular WBG semiconductors in power
• High-performance GaN-based 48-V to 1-V conversion for PoL applications
• GaN transistors for efficient power conversion: buck converters
• How to get 500W in an eighth-brick converter with GaN, part 1
• Thermal design for a high density GaN-based power stage

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The US Department of Commerce has signed a non-binding preliminary memorandum of terms (PMT) to provide up to $225m in proposed direct funding under the CHIPS and Science Act to tier-1 automotive supplier Bosch. The investment would support Bosch’s planned investment of $1.9bn to transform its manufacturing facility in Roseville, California, for production of silicon carbide (SiC) power semiconductors. This direct funding would support the expansion of Bosch’s largest SiC device factory globally, which would significantly increase the firm’s production capacity and create up to 1000 construction jobs and up to 700 manufacturing, engineering and R&D jobs in California...

After beginning construction in November 2023, the new €100m Innovation Center of deposition equipment maker Aixtron SE in Herzogenrath, near Aachen, Germany has been opened by Mona Neubaur, Minister for Economic Affairs, Industry, Climate Protection and Energy & Deputy Prime Minister of the State of North Rhine-Westphalia...

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With its new R&S NRPxE RF power sensors, Rohde & Schwarz sets a new standard for accurate and reliable power measurements in frequency ranges up to 18 GHz, while offering an unprecedented level of affordability. These innovative sensors offer a perfect blend of precision, durability, and value, making them an ideal solution for a wide range of applications, from R&D and production to education and field service

The new R&S NRPxE power sensors from Rohde & Schwarz offer unmatched performance and versatility. They feature an impressive dynamic range of 80 dB, a video bandwidth of 100 kHz, and the ability to perform up to 1,000 measurements per second. With frequency ranges from 10 MHz to 8 or 18 GHz, the power sensors cater to various measurement needs. Their compact design and ruggedized housing ensure easy handling and reliable operation in demanding environments.

Simplified Operation

The R&S NRPxE sensors feature a user-friendly design with IEEE-compliant label and connector color coding, ensuring safe and secure operation. The built-in trigger capability and RGB status LED provide additional convenience, allowing users to monitor sensor status and trigger measurements with ease.

Seamless Integration and Remote Control

Equipped with a USBTMC interface, the R&S NRPxE sensors can be easily integrated into test systems and controlled remotely via PC or mobile device. The free PowerViewer mobile app enables on-the-go measurements using an Android smartphone, making it perfect for field service and maintenance applications.

The new R&S NRPxE RF power sensors replace the established NRP-Z2x1 RF power sensors, offering up-to-date power measurements on modulated and unmodulated signals. They are now available from Rohde & Schwarz and selected distribution partners. For further information visit: https://www.rohde-schwarz.com/product/nrpxe

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Lumentum Holdings Inc of San Jose, CA, USA (which designs and makes optical and photonic products for cloud, optical networking and industrial and consumer laser applications) has appointed Paul Lundstrom to its board of directors, expanding the membership to nine members (eight of whom are independent)...

As we look ahead to 2025, one thing is clear: the digital landscape is evolving quickly, and it’s creating new cybersecurity challenges for businesses globally. From the growing speed, scale and sophistication of cyberattacks to the changing nature of how we work and connect, the future of network security depends on a holistic approach that integrates advanced AI technologies and seamless user experience.

In fact, Palo Alto Networks 2025 Cybersecurity and AI Predictions showcase how we’re at a pivotal moment in the evolution of enterprise security practices. One of the standout predictions we made was that 2025 will be the year enterprises will widely adopt a secure browser. This trend is not only an inevitability, it’s a necessity. ​​While secure browsers will see a huge increase in adoption in the year ahead, they represent only one piece of the puzzle.

Eight Network Security Trends We Think Will Redefine Organizations’ Approach to Cybersecurity in 2025:

1. The Rise of the Secure Browser

As more work is done through the browser and data breaches increasingly originate from browser vulnerabilities, securing this gateway to the digital world is now non-negotiable. We’re no longer living in an era where employees access business applications solely through desktops located primarily in an office. With the proliferation of remote work, BYOD (bring your own device) and the ever-growing reliance on cloud services, it’s more critical than ever that organizations provide workers with secure access to the digital tools needed to get their work done, regardless of location, device or application. Secure browsers not only safeguard against attacks but also prevent accidental and intentional leakage of sensitive data, yet can be as easy to use as consumer browsers. As this technology becomes widely adopted, it will fundamentally reshape how organizations approach browser security, marking the start of a new era in secure digital transformation.

2. As Nation-States Increase Attacks on Infrastructure, Governments Will Invest in Smart and Secure Infrastructure Technology

We expect ​​governments will invest in modernized and secure systems, especially as nation-state attacks on critical infrastructure increase. This effort goes beyond replacing outdated technology and focuses on deploying smart technologies while securing both legacy and new infrastructure to meet the needs of a digitally connected world.

Governments are also prioritizing investments in 5G technology to enable smart cities. These advancements will drive innovation in transportation, energy and public services, supporting the transition to smarter infrastructure. However, the challenges are significant. For instance, 66% of transportation organizations have been affected by ransomware attacks, and 77% of the government and other public sector organizations lack complete visibility over all their IoT devices. These gaps expose critical systems to risks, such as physical damage, data theft and service interruptions. This highlights the urgent need for comprehensive security measures.

Many critical environments, including industrial sites and remote facilities, face unique challenges in securing infrastructure. Ruggedized NGFWs are an essential solution for these settings, providing reliable security in places where traditional equipment may fail. With increasing threats and the complexity of securing IoT and OT devices, a robust approach to visibility and protection is essential.

We believe governments will focus on building integrated security solutions that protect both legacy systems and new technologies. By leveraging AI-driven tools for real-time discovery, monitoring and protection of IoT and OT devices, these investments will ensure critical systems remain secure while supporting the digital transformation of public infrastructure. These efforts will help keep essential services running while offering citizens the safety and confidence they expect.

3. Attackers Will Leverage Post-Quantum Cryptography (PQCs) to Evade Security Defenses

The security controls that are intended to protect against future quantum attacks (PQCs) have created an opportunity for attackers to take advantage of security solutions that don’t support or haven’t been upgraded to identify and block traffic encrypted with PQCs. For example, the Google Chrome browser now supports PQCs by default. The unintended consequence of this is that we’ll see an increase in PQC attacks, embedded in the web traffic that is encrypted now by default. This will affect cybersecurity because many network security products are unable to inspect PQC traffic, and attackers will take advantage of this to hide attacks inside of post-quantum encryption.

To combat this, enterprises will need visibility into where these algorithms are being used and ensure they are able to decrypt and inspect all data flowing through their enterprise networks. The good news is that the technology exists, like the Strata Network Security Platform, to identify, block and decrypt PQCs.

4. Attacks Will Increasingly use Multiple Techniques for a Successful Breach, Requiring Security Services to Work Together as Part of a Platform

Gone are the days of attacks hitting a single product or vulnerability. In 2025, one of the most alarming trends in cybersecurity will be the increasing use of multivector attacks and multistage approaches. How does it work? Cybercriminals leverage a combination of tactics, techniques and procedures (TTPs), hitting across multiple areas at once to breach defenses. We’ll see an increase in sophistication and evasion from web-based attacks, file-based attacks, DNS-based attacks and ransomware attacks, which will make it more difficult for traditional, siloed security tools to effectively defend against modern threats.

Preventing these attacks will require multiple security services to work together as part of an integrated platform to stop every attack along the cyber kill chain. For example, our Cloud-Delivered Security Services (CDSS) powered by Precision AI can prevent the latest and most advanced threats in real-time, with protections built into our Network Security Platform and delivered automatically. By protecting at multiple points in the cyber kill chain, companies can thwart the attack, providing defense-in-depth to address the full spectrum of threat vectors. In 2025 and beyond, only security solutions with global visibility into the attack patterns across network, cloud and endpoints will offer the most effective protection.

5. AI in Security Will Allow Organizations to Chip Away at the Cybersecurity Skills Gap

As cyberthreats become more sophisticated and widespread, the demand for skilled cybersecurity professionals continues to outpace the supply. But, there are bright skies ahead as AI-powered copilots fill in the gaps as intelligent assistants designed to support cybersecurity professionals in their daily tasks. If 2024 was the year when every security vendor introduced a copilot, 2025 will be the year of widespread adoption as customers understand the full extent of their power. Using our copilots, cybersecurity experts can harness knowledge at their fingertips, gain instant access to insights and benefit from guided automation. In the future, the life of the cybersecurity professional will get even easier, thanks to copilots’ ability to automate repetitive tasks, sift through huge amounts of data, and give more insightful answers and analysis.

This is a huge deal as the cybersecurity skills gap has long been a challenge to enterprises globally. When every cybersecurity professional is armed with a highly capable, AI-powered assistant (like our free Strata Copilot), cybersecurity professionals will be empowered to work smarter, not harder.

6. 2025 will be an Inflection Point Year, as Companies Will Double Their Interest and Deployment of Single Vendor Secure Access Service Edge (SASE)

No longer confined to the office, workers need secure, high-performance access to critical business technologies. From the home office, to the local coffee shop, to the beach, ​​they need to get their work done no matter where they are, and no matter what device they use. To adapt to the next frontier of work, companies will need to do more to protect sensitive workloads and data, while ensuring worker productivity. This is why in 2025, we’ll see the widespread adoption of single-vendor SASE solutions.

Because workers will demand the same experience they get from consumer applications, the security solution of choice will need to help, not hinder, productivity. This includes ensuring that users experience minimal latency and downtime, even when accessing cloud-based applications from remote locations. With a cybersecurity vendor like Palo Alto Networks, your workforce can access SaaS apps up to 5x faster than they would directly over the internet, so you don’t have to make a choice between security and performance. The future of work demands flexibility, and single-vendor SASE solutions are poised to provide the agility and security that enterprises need to thrive in an increasingly distributed workforce. And a comprehensive SASE solution should include a secure browser natively!

7. AI Will be Infused in Every Major Business Application, Leading to a Rise in AI-Specific Attacks

We anticipate the number of AI Apps will increase by 3-5x in the next 12-24 months. As companies eagerly bring these technologies onboard, they may overlook key issues in data collection methods, governance and AI-specific security needs. Anticipating weaknesses, attackers will step up their attacks against new components, such as LLMs, and training and inferencing data. This has the potential to create security incidents, compliance and legal issues in the coming year.

At the end of the day, it’s about protecting your sensitive data. But the question is how? The only way to protect against all these AI-specific threats is through comprehensive, AI-powered solutions. You can enable AI with AI, by using AI Access Security, which ensures that employees can securely access GenAI applications. AI Security Posture Management (SPM) identifies risks in your AI supply chain, including configuration issues and ways you might be exposing your sensitive data. AI Runtime Security ensures your applications, data and models are protected from AI-specific threats. In 2025, the companies that are securely adopting AI will separate themselves from the pack.

8. AI Will Make Phishing Emails Indistinguishable from Legitimate Ones

In 2025, user-targeted techniques, like phishing emails, will become more successful, thanks to bad actors’ adoption of generative AI (GenAI) to craft better and more convincing attacks. We’re already seeing a 30% increase in successful phishing attempts when emails are written or rewritten by GenAI. Mere humans, like ourselves, will become even less reliable as a last line of defense and enterprises will rely on advanced, AI-powered security protections to defend against these sophisticated attacks.

While companies today rely on antiphishing technologies, such as URL filtering (AURL) at the network level, more companies will enhance their protection with secure browsers as a first line of defense against these attacks. Pair this with an AI-powered single vendor SASE solution that offers advanced, cloud-delivered security services and your company will be ready to prevent the latest and most advanced threats in real-time. The best part? With Palo Alto Networks, these protections are built into our SASE solution and delivered automatically. And with us, you don’t need to cobble together point products. All these innovations are natively integrated into one comprehensive SASE solution, across every user, device and app.

Preparing for the Future of Network Security

The future of network security is an exciting one, but it also comes with its challenges. As 2025 approaches, it’s critical for organizations to stay ahead of these emerging trends by building agile security strategies that are adaptable to the rapidly changing threat landscape.

For businesses looking to future-proof their network security, the key is investing in a holistic platform approach that incorporates new technologies like secure browsers, single-vendor SASE, AI Copilots and AI-driven threat detection and response. By doing so, they will not only defend against today’s threats but also be ready for the cyber risks of tomorrow.

In 2025, network security will be more dynamic, innovative and proactive than ever before —transforming the way organizations defend their most valuable assets and ensuring a secure, resilient future in the face of an ever-evolving digital world.

The post 8 Trends Reshaping Network Security in 2025 appeared first on ELE Times.

Anritsu Corporation introduces an option that evaluates the RF transmit and receive characteristics of 2×2 MIMO as defined in IEEE 802.11be (Wi-Fi 7) for its Wireless Connectivity Test Set MT8862A (WLAN Tester). With this new expanded capability, the MT8862A supports to measure the receive sensitivity and transmit power of devices supporting Wi-Fi 7 2×2 MIMO, using the Network Mode [*], which allows devices to be evaluated under real-world operating conditions, thus helping to improve the communication quality of WLAN-equipped devices.

Development Background

Although the official release of the Wi-Fi 7 standard is scheduled for 2024, product development based on the draft standard is underway, with leading companies already beginning to bring their products to market. Especially, in devices for applications such as ultra-high-definition video streaming and AR/VR, large amounts of high-speed data is being handled. Multiple-Input Multiple-Output (MIMO) technology is used to increase transmission speed and the amount of traffic, but the complexity of the evaluation is a challenge. Anritsu has therefore enhanced the functionality of the MT8862A, which can easily measure WLAN-equipped devices under real-world operating conditions, to enable the evaluation of devices supporting Wi-Fi 7 2×2 MIMO, which requires two antennas for each of the transmitter and receiver.

Anritsu will contribute to improving the performance of ALMA, the unravelling of the universe, and the development of science.

Product Overview

• Evaluating RF TRX characterization of Wi-Fi 7 in Network Mod

The MT8862A supports three frequency bands (2.4 GHz/5 GHz/6 GHz), a 320 MHz channel bandwidth, and 4096 QAM modulation, and the new option allows it to evaluate the RF TRX characteristics of devices supporting Wi-Fi 7 2×2 MIMO in Network Mode.

• Easy to use and measure

The MT8862A can perform the necessary measurements by simply connecting to the WLAN-equipped device under test. No target control settings are required, and measurements can be taken even by personnel unfamiliar with how to configure the measurement system.

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To all the fellow software engineers - I see your off-by-one error, and raise to off-by-two! Can you spot a problem faster than me? https://imgur.com/a/aRg5k7a This chip failed to flash, but was erratically responding to some commands, took me hours to find the issue. submitted by /u/maxwell_aws [link] [comments]

Adaptive SoCs in AMD’s Versal RF series integrate direct RF sampling data converters, dedicated DSP hard IP, and AI engines in a single chip. The devices offer wideband-spectrum observability and up to 80 TOPS of digital signal processing performance in a SWaP-optimized design for radar, spectral analysis, and test and measurement applications. They also provide programmable logic and ample memory to create powerful accelerators.

Versal RF SoCs enable wideband spectrum capture and analysis with 14-bit multichannel RF ADCs and RF DACs. These converters support input/output frequencies up to 18 GHz and sampling rates up to 32 Gsamples/s. Select DSP functions, like 4-Gsample/s FFT/iFFT, channelizer, polyphase resampler, and LDPC decoder, run on dedicated hard IP blocks, cutting dynamic power by up to 80% compared to AMD soft logic.

Versal RF silicon samples and evaluation kits are expected in Q4 2025, with production shipments beginning in the first half of 2027.

Versal RF product page 

AMD

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post SoCs offer RF sampling and DSP muscle appeared first on EDN.

Nexus 2 is Lattice Semiconductor’s next-generation small FPGA platform, featuring improved power efficiency, edge connectivity, and security. Built on a 16-nm FinFET TSMC process, Nexus 2 FPGAs offer 65k to 220k system logic cells in a form factor that is up to 5 times smaller than similar class devices.

According to Lattice, Nexus 2 FPGAs deliver up to 3 times lower power consumption and up to 10 times greater energy efficiency for edge sensor monitoring compared to competing devices in the same class. Fast connectivity is enabled by a multiprotocol 16-Gbps SERDES, PCIe Gen 4 controller, and MIPI D-PHY/C-PHY interfaces operating at speeds up to 7.98 Gbps.

Nexus 2 FPGAs support a broad range of security functions, including 256-bit AES-GCM encryption and SHA3-512 hashing, compliant with FIPS 140-3 Level 2 standards. The devices also feature crypto agility, anti-tamper protection, and post-quantum readiness.

The Nexus 2 platform is designed to allow rapid development of new device families based on a single platform. The first of these, the Certus-N2 family of general-purpose small FPGAs, is now available for sampling.

Nexus 2 product page  

Certus-N2 product page 

Lattice Semiconductor 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Joining Synaptics’ Veros IoT connectivity family is the SYN20708, a dual-core SoC that supports Bluetooth 5.4 and IEEE 802.15.4. The Matter-compliant chip enables Bluetooth Classic, Bluetooth Low Energy (BLE), Zigbee, and Thread protocols to operate concurrently on both cores, allowing simultaneous connections to multiple endpoints in heterogeneous network environments.

The SYN20708 employs a modular software architecture that simplifies development for systems requiring low latency, extended range, low power, and interoperability. It can be used in a range of consumer, automotive, healthcare, and industrial applications, including dedicated home hubs and automotive infotainment systems.

The SoC features dual-antenna maximum ratio combining (MRC) and transmit beamforming (TxBF) to enhance signal quality and double communication range. It is Bluetooth 5.4 certified and Bluetooth 6.0 compliant, enabling channel sounding, Bluetooth Classic Audio, and LE Audio. The SoC supports IEEE 802.15.4 (OpenThread and ZBOSS) up to Version 2, along with BLE Long Range, angle of departure (AoD), and angle of arrival (AoA) capabilities. Synaptics’ proprietary CoEX technology improves coexistence in the 2.4-GHz band.

The SYN20708 wireless SoC is available now.

SYN20708 product page

Synaptics

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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A 4-phase PWM controller from AOS, paired with industry-standard DrMOS power stages, boosts system efficiency for NVIDIA Blackwell GPU platforms. The AOZ73004CQI, which powers AI servers and graphics cards based on the Blackwell architecture, is fully compliant with the Open Voltage Regulator (OpenVReg) OVR4-22 standard.

The AOZ73004CQI’s cycle-by-cycle current limit aligns with the GPU’s overcurrent protection requirements, enabling safe power throttling to maximize performance. It features an external reference input and PWMVID interface for dynamic output voltage control. By reducing ripple effects, the controller achieves PWMVID slew rates of up to 30 mV/µs—a threefold increase over typical rates. Additionally, deep-off and shallow-off power states minimize power consumption.

The AOZ73004CQI with 4-phase PWM is not limited to using four DrMOS power stages as standard. AOS’s proprietary DrMOS design allows precise turn-on timing, enabling one PWM to drive two or three DrMOS devices. By doubling or tripling DrMOS, designers can create a high-power, multiphase system with up to 12 power stages.

Prices for the AOZ73004CQI buck controller start at $1.20 each in lots of 1000 units.

AOZ73004CQI product page 

Alpha & Omega Semiconductor 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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With 36 programmable LED current channels, the AL5887Q from Diodes drives up to 12 RGB configurations or 36 individual LEDs. The automotive-compliant linear driver provides a hardware-selectable I2C or SPI digital interface, along with an internal 12-bit PWM for precise color and brightness control. Designers can create dynamic lighting patterns and rich color depths for both interior and exterior lamps.

An external resistor sets the output current for all 36 channels, with each channel’s current digitally configurable up to 70 mA without the need for paralleling. An automatic power-saving mode reduces current to 15 µA, and a quiescent shutdown mode cuts it to 1 µA when all LEDs are off for more than 30 ms, minimizing energy draw from the car’s battery.

The AL5887Q includes multiple protection features, such as an open-drain fault pin with diagnostic fault registers and individual fault mask registers. It also provides overtemperature protection with a pre-OTP warning.

The AEC-Q100 qualified AL5887Q driver costs $1.13 each in lots of 1000 units.

AL5887Q product page

Diodes

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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The ubiquitous variable resistance circuit network shown in Figure 1…

Figure 1 Classic adjustable resistance; Rmax = Rs + Rr; Rmin = Rs.

…can be accurately synthesized in solid state circuitry built around a digital potentiometer (Dpot) as discussed in “Synthesize precision Dpot resistances that aren’t in the catalog.” Its accuracy holds up despite pot resistance element tolerance and is independent of wiper resistance. See Figure 2 for the circuit.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 2 Synthetic Dpot evades problems by using FET shunt, precision fixed resistors, and op-amp; Rab > Rmax; Rp = (Rmax-1 – Rab-1)-1; Rs = (Rmin-1 – Rab-1 – Rp-1)-1.

But a sticky question remains: What if the polarity of the Va – Vb differential is subject to reversal? Figure 1 can of course accommodate this without a second thought, but it’s a killer for Figure 2.

A simple—but unfortunately unworkable—solution is shown in Figure 3.

Figure 3 Simply paralleling complementary N and P channel MOSFETs might look good but won’t work beyond a few hundred mV of |Va – Vb|.

The problem arises of course from the parasitic body diodes common to MOSFETs, which conduct and bypass the transistor if the reverse polarity source-drain differential is ever more than a few tenths of a volt.

Figure 4 shows the simplest (not very simple) solution I’ve been able to come up with.

Figure 4 Two complementary anti-series FET pairs connected in parallel allow bipolar operation.

Inspection of Figure 4 shows a couple extra FETs have been added in anti-series with the paralleled complementary transistors of Figure 3, together with polarity comparator amplifier A2. A2 enables the Q1/Q2 pair for (Va – Vb) > 0, Q3/Q4 for (Va – Vb) < 0. 

The TLV9152 with its 4.5-MHz gain-bandwidth, 400-ns overload recovery, and 21-V/µs slew rate is a fairly good choice for this application. Nevertheless, significant crossover distortion can be expected to creep in for low signal amplitudes and frequencies above 10 kHz or so.

Design equations are unchanged from Figure 2.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Synthesize precision Dpot resistances that aren’t in the catalog
• Keep Dpot pseudologarithmic gain control on a leash
• Dpot pseudolog + log lookup table = actual logarithmic gain
• Digital potentiometer simulates log taper to accurately set gain
• Op-amp wipes out DPOT wiper resistance
• Adjust op-amp gain from -30 dB to +60 dB with one linear pot

The post Synthesize precision bipolar Dpot rheostats appeared first on EDN.

All buck converters need capacitors on the input. Actually, in a perfect world, if the supply had zero output impedance and infinite current capacity and the tracks had zero resistance or inductance, you wouldn’t need input capacitors. But since this is infinitesimally unlikely, it’s best to assume that your buck converter will need input capacitors.

Input capacitors store the charge that supplies the current pulse when the high-side switch turns on; they are recharged by the input supply when the high-side switch is off (Figure 1).

Figure 1 The above diagram shows simplified current waveform in the input capacitor current during the buck DC/DC switching cycle, assuming infinite output inductance. Source: Texas Instruments

The switching action of the buck converter charges and discharges the input capacitor, causing the voltage across it to rise and fall. This voltage change represents the input voltage ripple of the converter at the switching frequency. The input capacitor filters the input current pulses to minimize the ripple on the input supply voltage.

The amount of capacitance governs the voltage ripple, so the capacitor must be rated to withstand the root-mean-square (RMS) current ripple. The RMS current calculation assumes the presence of only one input capacitor, with no equivalent series resistance (ESR) or equivalent series inductance (ESL). The finite output inductance accounts for the current ripple on the input side, as shown in Figure 2.

Figure 2 Input capacitor ripple current and calculated RMS current are displayed by TI’s Power Stage Designer software. Source: Texas Instruments

Current sharing between parallel input capacitors

Most practical implementations use multiple input capacitors in parallel to provide the required capacitance. These capacitors often include a small-value, high-frequency multilayer ceramic capacitor (MLCC), for example, 100 nF. One or more larger MLCCs (10 µF or 22 µF) are used, and sometimes accompany a polarized large-value bulk capacitor (100 µF).

Each capacitor is performing similar yet different functions; the high-frequency MLCC decouples fast transient currents caused by the MOSFET switching process in DC/DC converter. The larger MLCCs source the current pulses to the converter at the switching frequency and its harmonics. The bulk capacitor supplies the current required to respond to output load transients when the impedance of the input source means that it cannot respond as quickly.

Where used, a large bulk capacitor has a significant ESR, which provides some damping of the input filter’s Q factor. Depending on its equivalent impedance at the switching frequency relative to the ceramic capacitors, the capacitor may also have significant RMS current at the switching frequency.

The datasheet of a bulk capacitor specifies a maximum RMS current rating to prevent self-heating and ensure that its lifetime is not degraded. The MLCCs have a much smaller ESR and correspondingly much less self-heating because of the RMS current. Even so, circuit designers sometimes overlook the maximum RMS current specified in ceramic capacitor datasheets. Therefore, it is important to understand the RMS currents in each of the individual input capacitors.

If you are using multiple larger MLCCs, you can combine them and enter the equivalent capacitance into the current-sharing calculator for calculating RMS currents in parallel input capacitors. The calculation of RMS current considers the fundamental frequency only. Nonetheless, this calculation tool is a useful refinement of the single input capacitor RMS current calculation.

Consider an application where VIN = 9 V, VOUT = 3 V, IOUT = 12.4 A, fSW = 440 kHz and L = 1 µH. The three parallel input capacitors could then be 100 nF (MLCC), ESR = 30 mΩ, ESL = 0.5 nH; 10 µF (MLCC), ESR = 2 mΩ, ESL = 2 nH; and 100 µF (bulk), ESR = 25 mΩ, ESL = 5 nH. The ESL here includes the PCB track inductance.

Figure 3 shows the capacitor current-sharing calculator results for this example. The 100-nF capacitor draws a low RMS current of 40 mA as expected. The larger MLCC and bulk capacitors divide their RMS currents more evenly at 4.77 A and 5.42 A, respectively.

Figure 3 Output is shown from TI’s Power Stage Designer capacitor current-sharing calculator. Source: Texas Instruments

In reality, the actual capacitance of the 10-µF MLCC is somewhat lower because of the voltage applied. For example, a 10-µF, 25-V X7R MLCC in an 0805 package might only provide 30% of its rated capacitance when biased at 12 V, in which case the large bulk capacitor’s current is 6.38 A, which may exceed its RMS rating.

The solution is to use a larger capacitor package size and parallel multiple capacitors. For example, a 10-µF, 25-V X7R MLCC in a 1210 package retains 80% of its rated capacitance when biased at 12 V. Three of these capacitors have a total effective value of 24 µF when used for C2 in the capacitor current-sharing calculator.

Using these capacitors in parallel reduces the RMS current in the large bulk capacitor to 3.07 A, which is more manageable. Placing the three 10-µF MLCCs in parallel also reduces the overall ESR and ESL of the C2 branch by a factor of three.

The low capacitance of the 100-nF MLCC and its relatively high ESR mean that this capacitor plays little part in sourcing the current at the switching frequency and its lower-order harmonics. The function of this capacitor is to decouple nanosecond current transients seen at the switching instants of the DC/DC converter’s MOSFETs. Designers often refer to it as the high-frequency capacitor.

In order to be effective, it’s essential to place the high-frequency capacitor as close as possible to the input voltage and ground terminals of the regulator using the shortest (lowest inductance) PCB routing possible. Otherwise, the parasitic inductance of the tracks will prevent this high-frequency capacitor from decoupling the high-frequency harmonics of the switching frequency.

It’s also important to use as small a package as possible to minimize the ESL of the capacitor. A high-frequency capacitor with a value of <100 nF can be beneficial for decoupling at a specific frequency when compared to its ESR and impedance curve. A smaller capacitor will have a higher self-resonance frequency.

Similarly, always place the larger MLCCs as close as possible to the converter to minimize their parasitic track inductance and maximize their effectiveness at the switching frequency and its harmonics.

Figure 3 also shows that, although the overall RMS current in the overall input capacitor (were it a single equivalent capacitor) is 6 A, the sum of RMS currents in the C1, C2 and C3 branches is >6 A and does not follow Kirchhoff’s current law. The law only applies to the instantaneous values, or to the complex addition of the time-varying and phase-shifted currents.

Using PSpice for TI or TINA-TI software

Designers who need more than three input capacitor branches for their applications can use PSpice for TI simulation software or TINA-TI software. These tools enable more complex RMS current calculations, including harmonics alongside the fundamental switching frequency and the use of a more sophisticated model for the capacitor, which captures the frequency-dependent nature of the ESR.

TINA-TI software can compute the RMS current in each capacitor branch in the following way: run the simulation, click the desired current waveform to select it, and from the Process menu option in the waveform window, select Averages. TINA-TI software uses a numerical integration over the start and end display times of the simulation to calculate the RMS current.

Figure 4 shows the simulation view. For clarity in this example, we omitted the 100-nF capacitor because its current is very low and contributes to ringing at the switching edges. The Power Stage Designer software analysis of the total input capacitor current waveform for the converter calculates the input current (IIN), which is 6 ARMS, the same value as for Figure 2.

Figure 4 Output from TINA-TI software shows the capacitor branch current waveforms and calculated RMS current in C2. Source: Texas Instruments

The capacitor current waveforms in each branch are quite different compared to the idealized trapezoidal waveform that ignores their ESR and ESL. This difference has implications for DC/DC converters such as the TI LM60440, which has two parallel voltage input (VIN) and ground (GND) pins.

The mirror-image pin configuration enables designers to connect two identical parallel input loops, meaning that they can place double input capacitance (both high frequency and bulk) in parallel close to the two pairs of power input (PVIN) and power ground (PGND) pins. The two parallel current loops also halve the effective parasitic inductance.

In addition, the two mirrored-input current loops have equal and opposite magnetic fields, allowing some H-field cancellation that further reduces the parasitic inductance (Figure 5). Figure 4 suggests that if you don’t carefully match the parallel loops in capacitor values, ESR, ESL and layout for equal parasitic impedances, then the current in the parallel capacitor paths can differ significantly.

Figure 5 Parallel input and output loops are shown in a symmetrical “butterfly” layout. Source: Texas Instruments

Software tool use considerations

To correctly specify input capacitors for buck DC/DC converters, you must know the RMS currents in the capacitors. You can estimate the currents from equations, or more simply by using software tools like TI’s Power Stage Designer. You can also use this tool to estimate the currents in up to three parallel input capacitor branches, as commonly used in practical converter designs.

More complex simulation packages such as TINA-TI software or PSpice for TI can compute the currents, including harmonics and fundamental frequencies. These tools can also model frequency-dependent parasitic impedance and many more parallel branches, illustrating the importance of matching the input capacitor combinations in mirrored input butterfly layouts.

Dr. Dan Tooth is Member of Group Technical Staff at Texas Instruments. He joined TI in 2007 and has been a field application engineer for over 17 years. He is responsible for supporting TI’s analog and power product portfolio in ADAS, EV and diverse industrial applications.

Dr. Jim Perkins Senior Member of Technical Staff at Texas Instruments. He joined TI in 2011 as part of the acquisition of National Semiconductor and has been a field application engineer for over 25 years. He is now mainly responsible for supporting TI’s analog and power product portfolio in grid infrastructure applications such as EV charging and smart metering.

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