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Gallium nitride (GaN) power IC and silicon carbide (SiC) technology firm Navitas Semiconductor Corp of Torrance, CA, USA says that Samsung has expanded adoption of its GaNFast ICs from the original flagship Galaxy S22, S23 and S24 to the mainstream Galaxy A, and Galaxy Z Fold6 and Galaxy Z Flip6 smartphones with enhanced Galaxy AI features...

ams OSRAM GmbH of Premstätten, Austria and Munich, Germany says that, this fall, it will launch the SPL S8L91A_3 A01, a high-performance 915nm infrared SMT pulsed laser with a monolithically integrated 8-channel design in a QFN (quad flat no leads) package. By simplifying the system design and boosting the performance, the laser is said to increase the effectiveness and reliability of long-range, high-resolution LiDAR systems...

Oscilloscope measurement parameters provide accurate measurements of acquired waveforms. Most digital oscilloscopes offer around twenty-five standard parameters like frequency, peak-to-peak amplitude, and RMS amplitude. What if you need a measurement parameter that is not in the standard measurement package? Most oscilloscope manufacturers keep alert for these opportunities and offer specialized software analysis packages with optional application-specific parameters. Optional software for power, jitter, serial data, and many more applications, each with specialized measurement parameters, are offered. Another solution is to allow users to create custom measurements using both waveform and parameter math.

Waveform math combines whole waveforms using mathematical functions. Parameter math allows oscilloscope users to create custom measurement parameters based on simple arithmetic relationships between standard measurement parameters. These features allow users to extend the original complement of measurement parameters and to create new parameters based on their measurement needs. This feature can extend the number of available measurements beyond the basic measurement parameters available in the oscilloscope.

This article will examine some commonly used measurements and show how waveform and parameter math can be used to calculate them based on standard measurements.

Setting up a custom measurement using parameter math

Parameter math is controlled in the measurement parameter setup of this oscilloscope and offers eight arithmetic operations to apply to one or more defined measurement parameters (Figure 1).

Figure 1 A typical measurement parameter math setup takes the ratio of parameter P3 to parameter P4. Source: Arthur Pini

The available arithmetic operations are sum, difference, product, ratio, reciprocal (invert), identity, rescale, and constant. These operations, supplemented by the use of waveform math operations can yield many custom parameters. Parameter math also includes the ability to do these calculations using visual basic scripts. Visual basic scripting is used to internally program the scope and automate selected scope operations.

Measurements based on parameter math share all the characteristics of standard measurement parameters. They can be displayed singly or statistically adding mean, minimum, maximum, and standard deviation values. They can be used as inputs to waveform math functions including histograms, trends, and tracks.

Examples of custom measurement parameters. Range finder

Measuring distance using ultrasonic signals involves taking a difference between two parameters along with rescaling that measurement from time delay to distance. Figure 2 shows a range measurement using an ultrasonic signal.

Figure 2 Using parameter math to take the time difference between a transmitted and reflected ultrasonic pulse. Source: Arthur Pini

The ultrasonic range finder emits a series of 40 kHz pulses and then detects the time to receive a reflection for each transmitted pulse. The oscilloscope measurement determines the maximum amplitude of the transmitted (parameter P1) and reflected pulses (parameter P3) using gated measurements. It then measures the time at which each maximum occurs using the X@max parameter (parameters P2 and P4). The time difference between these parameters (P5) is the delay between the pulses. This time represents double the distance between the range finder and the target. The final step is to use the parameter math rescale function to multiply the time by one-half of the pulse velocity. The parameter P6 multiplies the time difference by the velocity of the pulse in air divided by two [171.5 meters per second (m/s)]. The rescale function also features the ability to modify the units so that the readout is in units of meters. The resultant distance of 548 millimeters.

Frequency to wavelength

All digital oscilloscopes can read the frequency of a periodic signal. What if you needed to measure the signal’s wavelength? Wavelength is the velocity of the signal divided by its frequency. For a 2.249 GHz sinewave in air, the velocity is 300,000,000 m/s and the wavelength is 0.133 meters (133 mm). The calculation is easy enough to do with a calculator but suppose you wanted to document the measurement and have it available on the oscilloscope screen along with all your other measurements. Using a combination of the constant and ratio arithmetic operations and the measured frequency, the wavelength can be added to the screen as shown in Figure 3.

Figure 3 The constant setup for computing wavelength from frequency using parameter math. The constant is divided by the measured frequency to obtain the signal’s wavelength. Source: Arthur Pini

The calculation of wavelength from frequency starts with entering the velocity of the signal in air at 300M m/s into parameter P2. The setup of the constant includes the ability to enter the physical units of the constant, m/s in this case. The ratio of signal velocity to frequency is accomplished by using the ratio function in parameter P2 to the frequency in P1 as shown in P3. The wavelength of the 2.249 GHz sinewave is 133 mm.

Crest factor

The crest factor is the ratio of the peak amplitude of an RF signal to its RMS value. The oscilloscope measures the peak-to-peak value of a waveform but getting the peak value takes a little math. Figure 4 shows the process using a 40 gigabaud 8PSK signal on a 1-GHz carrier. Determining the peak value of a complex signal is complex. Peaks can be positive or negative in polarity. The peak value is extracted by using the absolute value waveform math function to create a peak detector, converting the acquired bipolar RF signal into a unipolar signal, and then using the maximum measurement parameter to find the greatest peak.

Figure 4 Using the absolute value math function and the maximum measurement parameter to measure the peak value of a modulated RF carrier. Source: Arthur Pini

The math trace F1 performs the computation of the absolute value of the modulated RF carrier in trace M1. Measuring the peak value is done using the maximum value measurement parameter as parameter P1. This process produces a custom measurement of the amplitude using a math function and can be done in any oscilloscope offering the absolute math functions and a maximum or peak measurement, it does not require the use of measurement parameter math. The second half of the crest factor calculation does use parameter math. Continuing with the maximum parameter P1 with the peak value of the RF carrier. The measurement P2 is the RMS value of the RF waveform, a standard measurement. Parameter math is used to complete the calculation of the crest factor by taking the ratio of P1 to P2 and displaying it as parameter P3.

Apparent power and power factor

Although measurements of switched-mode power supplies are generally supported by an application-specific software option in this oscilloscope it is possible to make the same measurements using a combination of waveform and parameter math. Figure 5 provides an example of computing apparent power, real power, and power factor based on the acquired primary voltage and current of a switched-mode power supply.

Figure 5 Using parameter math to calculate apparent power, real power, and power factor based on the input line voltage and line current of a power supply. Source: Arthur Pini

The apparent power P3 is the product of the RMS values of the line voltage P1 and line current P2. The parameter math rescale function P4 is used to convert the reading of apparent power to the correct units of volt-amperes (VA).

To calculate the real power the waveform math product function multiplies the voltage and current waveforms. This is the instantaneous power shown in math trace F1. The parameter P5 measures the mean of the instantaneous power resulting in the real power reading. The ratio of the real to the apparent power is the power factor shown as P6 which used the ratio parameter math function.

FM modulation index

Frequency modulation (FM) is commonly used for applications like frequency shift keying and spread spectrum clocking. One of the key measurements made on an FM signal is its modulation index. The modulation index is the ratio of the FM signal’s frequency deviation from the carrier to its modulation frequency. Neither of these measurements can be made directly from the modulated carrier. The signal has to be demodulated to determine the FM deviation and modulation frequency.

Demodulation is easy to accomplish by using the waveform math track function of the frequency measurement parameter. The track is a time-synchronous plot of the signal’s instantaneous frequency. Figure 6 shows the key measurements made in computing the FM modulation index of an FM signal with a 90-MHz carrier.

Figure 6 Using measurements of the track function of frequency demodulate the 90-MHz FM signal to compute the frequency deviation and modulation frequency needed to calculate the modulation index. Source: Arthur Pini

The FM carrier is shown in the upper left grid. The fast Fourier transform (FFT) of the modulated carrier, in the right-hand grid, shows the dynamics of the variation of the signal frequency about the 90-MHz carrier. The horizontal scale factor of the FFT is 500 kHz per division, frequency deviation can be read approximately from the FFT as ± 250 kHz.   

A more accurate determination of the frequency deviation can be obtained by plotting the track of the signal frequency. This is shown in the lower left-hand grid. The track function plots the instantaneous frequency measured on a cycle-by-cycle basis versus time, synchronous to the source waveform. The vertical axis of the track function is in units of frequency. A parameter measurement of the track’s peak-to-peak amplitude P2 is double the frequency deviation. The parameter math rescale function is used to divide the track by a factor of two with the frequency deviation result in P3 as 251.67 kHz. The frequency of the track P4 is the modulation frequency, 10 kHz in this example. P5 uses the parameter math ratio function to compute the modulation index by dividing the frequency deviation by the modulation frequency. The modulation index is 25.2.

The oscilloscope used for these examples is a Teledyne LeCroy WaveMaster 8Zi-A which, like other Teledyne LeCroy Windows-based oscilloscopes, includes parameter math. Oscilloscopes that do not include parameter math may be able to use scripting or similar programming capabilities to perform these calculations.

Waveform and parameter math

Using a combination of waveform and parameter math allows oscilloscope users to create custom measurements. These measurements are displayed on-screen just like the standard measurement parameters and can be used as the basis of ongoing analysis including measurement statistics and histograms, trends, and track waveform math functions.

Arthur Pini is a technical support specialist and electrical engineer with over 50 years of experience in electronics test and measurement.

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LED product and lighting maker Lumileds LLC of San Jose, CA, USA says that in July it completed the sale of its Lamps and Accessories business to First Brands Group LLC (a global automotive parts maker that serves the worldwide automotive aftermarket)...

AAEON’s SRG-IMX8PL and PICO-IMX8PL enhance its growing RISC computing line.

Industry leader AAEON has expanded its RISC computing product portfolio with the release of the SRG-IMX8PL and PICO-IMX8PL, a Mini PC and 2.5” PICO-ITX board, respectively. Both products are powered by the NXP i.MX 8M Plus platform, featuring a quad-core Arm Cortex-A53 processor with a Neural Processing Unit (NPU) operating at up to 2.3 TOPS.

Built to provide cost-efficient IoT Gateway solutions in rugged environments, the SRG-IMX8PL and PICO-IMX8PL both offer wide temperature ranges of -40°C to 80°C with the use of a fanless heatsink, a 9V to 36V power input range. The SRG-IMX8PL Mini PC also features enhanced shock, drop, and vibration resistance.

Dual LAN ports with IEEE 1588 and TSN capabilities, alongside Wi-Fi and 4G module support via M.2 2230 E-Key and full-size mini card, provide each device with broad connectivity options for industrial IoT use. Additionally, both the PICO-IMX8PL and SRG-IMX8PL support a wide range of operating systems, including Debian 11, Android 13, Windows 10 IoT, and Yocto, as well as data communication protocols such as Modbus, MQTT, and OPC Unified Architecture (OPC UA).

Other key interfaces that make the two products well-suited for low-power, efficient IoT applications are the variety of industrial communication protocols they offer. Both platforms provide dual CAN-FD, dual COM for RS-232/422/485, and a range of other options such as GPIO, SPI, I2C, and UART. These interfaces offer scalability, long-distance communication, and wide compatibility for legacy systems.

It should also be noted that the SRG-IMX8PL is available with both wall-mount and DIN rail mounting options, making the compact system suitable for a variety of settings.

Pricing and ordering information are now available via AAEON’s online contact form, with the products also available via the AAEON eShop.

For detailed specifications, please visit the IoT Gateway & Protocol Expansion section of the AAEON website.

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Worldwide silicon wafer shipments increased 7.1% quarter-over-quarter to 3,035 million square inches (MSI) in the second quarter of 2024 but saw an 8.9% decline from the 3,331 million square inches recorded during the same quarter last year, the SEMI Silicon Manufacturers Group (SMG) reported in its quarterly analysis of the silicon wafer industry.

“The silicon wafer market is recovering driven by strong demand related to products for data centers and generative AI,” said Lee Chungwei (李崇偉), Chairman of SEMI SMG and Vice President and Chief Auditor at GlobalWafers. “While the recovery is uneven across different applications, 300mm wafer Q2 shipments indicated 8% quarter-over-quarter growth for the best performance among all wafer sizes. There are a growing number of new semiconductor fabs under construction or ramping production volume. This expansion, along with the longer-term trend toward a $1 trillion semiconductor market, will inevitably require more silicon wafers.”

Data cited in this release include polished silicon wafers, including those used as virgin test wafers, as well as epitaxial silicon wafers, and non-polished silicon wafers shipped by the wafer manufacturers to end users.

Silicon wafers are the fundamental building material for the majority of semiconductors, which are vital components of all electronic devices. The highly engineered thin disks are produced in diameters of up to 12 inches and serve as the substrate material on which most semiconductors are fabricated.

The SMG is a sub-committee of the SEMI Electronic Materials Group (EMG) and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi). The SMG facilitates collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.

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The advancement of three-dimensional integrated circuits (3DICs) offers substantial performance enhancements by consolidating more functionality into compact designs. However, this innovation also brings significant challenges, particularly in managing the increased heat dissipation.

The Benefits and Obstacles of 3DICs

3DIC technology entails layering several silicon wafers or dies and linking them through vertical interconnects. This stacking provides several advantages:

1. Enhanced Performance: Reducing the distance between components minimizes signal delays, accelerating processing speeds.
2. Increased Functionality: Multiple functionalities can be integrated into a single compact package, leading to more versatile devices.
3. Lower Power Consumption: Shorter interconnects can result in reduced power consumption compared to traditional 2D ICs.

Despite these benefits, 3DICs face challenges, with thermal management being a primary concern. The increased component density can result in elevated temperatures, which may affect the performance and reliability of the device.

Why Effective Thermal Management Matters

Thermal management in 3DICs is complex due to factors such as:

1. High Power Density: The close arrangement of components generates significant heat.
2. Thermal Gradients: Uneven power distribution can create varying temperatures across the chip.
3. Thermal Resistance: Stacked, thinned dies increase resistance to heat dissipation.

Inadequate thermal management can lead to performance degradation, reduced reliability, and shorter device lifespans. Therefore, thorough thermal analysis is critical throughout the design process.

The Importance of Early-Stage Thermal Analysis

Historically, thermal analysis was conducted at the package and system levels, separate from IC design. However, with the advent of 3DICs, early-stage thermal analysis at the die level is crucial. This approach helps:

1. Identify Hotspots: Early detection of high thermal activity areas enables design adjustments to improve heat distribution.
2. Optimize Design: Iterative analysis during die and package design enhances thermal performance.
3. Improve Reliability: Addressing thermal issues early boosts overall product reliability and reduces failure risks.

Advancements in Die-Level Thermal Analysis

Emerging integrated chip-package thermal co-design tools are vital for addressing 3DIC thermal challenges. These tools offer:

1. IC Design Integration: Integration with existing IC design tools ensures thermal analysis is part of the design process.
2. Precision and Detail: Sophisticated solvers deliver comprehensive thermal analysis for the 3DIC assembly.
3. Automated Simulation: Automation makes thermal analysis accessible to designers without specialized expertise.
4. Iterative Analysis: Continuous refinement based on thermal feedback is facilitated.

Integrated Thermal Analysis Solutions

An example of an effective thermal analysis tool is one that includes a custom 3D solver within a well-established IC design platform. This tool supports various 3D integration technologies and allows for comprehensive thermal assessment from initial design to final approval. It is integrated with other design tools across IC, package, and system levels.

Utilizing Thermal Analysis Throughout the Design Process

An effective thermal analysis tool should be capable of supporting multiple phases of the design process:

1. Early Design Planning: High-level power estimates guide thermal impact exploration, including 3D partitioning and package selection.
2. Detailed Design: Thermal analysis verifies that designs remain within thermal limits, focusing on power maps and hotspot effects.
3. Design Signoff: Comprehensive verification ensures the design meets thermal and reliability requirements.
4. Package-System Integration: IC-level thermal models aid in package and system thermal analysis, streamlining the development process.

Practical Integration and Usability

Effective thermal analysis tools should be user-friendly, incorporating automation features such as:

1. Optimized Gridding: Finer grids in critical areas for accuracy and coarser grids elsewhere for efficiency.
2. Time Step Automation: Automatic generation of smaller time steps during power transitions.
3. Equivalent Thermal Properties: Simplifying models while maintaining accuracy.
4. Power Map Compression: Adaptive bin sizes to capture non-uniform power distribution.
5. Automated Reporting: Summary reports that highlight key results for decision-making.

Visualization and Debugging

Advanced visualization tools are crucial for interpreting results and debugging. Features may include:

1. Overlaying Thermal Maps: Visualizing power distribution and thermal behaviour in the context of the layout.
2. Multiple Colormap Displays: Viewing thermal distributions across 3D components with animation capabilities.
3. Waveform Viewing: Integrating temperature and power waveforms with measured results for calibration.

Real-World Applications and Case Studies

The benefits of integrated thermal analysis solutions are demonstrated in real-world scenarios. For instance, CEA utilized an advanced tool from Siemens EDA to study their 3DNoC demonstrator, achieving high accuracy with minimal differences between simulated and measured data. Additionally, thermal-aware partitioning and optimization in complex designs involving multiple chiplets demonstrated significant improvements in thermal management.

Conclusion

The shift to 3DICs represents a major advancement in semiconductor design, offering enhanced performance and functionality. Addressing the associated thermal challenges requires robust thermal analysis tools. By incorporating early-stage thermal analysis, designers can ensure their 3DICs meet performance and reliability standards, paving the way for the next generation of high-performance electronic devices.

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Physicists from the Cavendish Laboratory have discovered groundbreaking methods to enhance the performance of organic semiconductors. By innovating ways to remove more electrons from these materials than previously possible and leveraging unique properties within a non-equilibrium state, they have achieved significant improvements for electronic devices.

Enhanced Electron Removal and Non-Equilibrium States

“Our goal was to understand the impacts of heavy doping in polymer semiconductors,” stated Dr. Dionisius Tjhe, a Postdoctoral Research Associate at the Cavendish Laboratory. Doping, the process of adding or removing electrons in a semiconductor, enhances its ability to conduct electrical current. In a recent Nature Materials paper, Tjhe and his colleagues explained how these novel insights could significantly enhance the performance of doped semiconductors.

Energy Bands and Advanced Doping Levels

Electrons in solids are organized into energy bands, with the valence band playing a crucial role in properties like electrical conductivity and chemical bonding. Typically, doping in organic semiconductors involves removing a small fraction of electrons from the valence band, creating holes that conduct electricity.

“Typically, only 10 to 20 percent of electrons are removed from the valence band of an organic semiconductor,” Tjhe explained. “However, in our study, we succeeded in completely emptying the valence band in two polymers. Even more remarkably, in one of these materials, we were able to extract electrons from the band beneath the valence band, which may be an unprecedented achievement in the field.”

Higher Conductivity in Deeper Energy Levels

Interestingly, the conductivity is significantly higher in the deeper valence band compared to the top one. Dr. Xinglong Ren, a co-first author of the study, noted, “Higher conductivity in deep energy levels could lead to more powerful thermoelectric devices, which convert heat into electricity. By finding materials with higher power output, we can make waste heat conversion into electricity more viable.”

Polymer Benefits and Broader Implications

While researchers believe the valence band emptying effect could be replicated in other materials, it is most easily observed in polymers. “The polymer’s energy band arrangement and disordered chains facilitate this effect,” Tjhe pointed out. “Achieving this in other semiconductors like silicon is more challenging. Understanding how to replicate this in other materials is our next crucial step.”

Innovative Methods to Enhance Thermoelectric Performance

Doping increases hole numbers but also raises ion counts, potentially limiting power. However, using a field-effect gate electrode allows researchers to control hole density without affecting ion numbers.

“By utilizing the field-effect gate, we discovered that modifying the hole density produced unusual results,” according to Dr. Ian Jacobs, a Royal Society University Research Fellow at the Cavendish Laboratory. “Surprisingly, adjusting the hole density with the field-effect gate, whether by adding or removing holes, always resulted in increased conductivity.”

Exploiting Non-Equilibrium State Properties

The researchers linked these surprising effects to a ‘Coulomb gap,’ a seldom-seen characteristic in disordered semiconductors. This phenomenon vanishes at room temperature but was observable at -30°C.

“Coulomb gaps are difficult to detect as they only manifest when the material cannot achieve its most stable state,” Jacobs explained. “In our material, ions become frozen at relatively high temperatures.” When electrons are added or removed in this frozen state, the material enters a non-equilibrium state, revealing the Coulomb gap.”

This non-equilibrium state allows both thermoelectric power output and conductivity to increase together, a significant improvement. The current limitation is that the field-effect gate only affects the material’s surface. Affecting the bulk could enhance power and conductivity even further.

Future Prospects

Despite remaining challenges, the researchers have outlined a clear path to improving organic semiconductor performance. Their work opens doors for further investigation, particularly in energy applications. “Tapping into transport within these non-equilibrium states continues to offer a promising approach for improving organic thermoelectric devices,” said Tjhe.

With these advancements, the potential for organic semiconductors in electronic devices and energy applications looks more promising than ever.

 

Source: University of Cambridge

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Open-source projects allow anyone to examine, modify or improve the respective code, offering significantly more flexibility than proprietary software. They are also gaining momentum by creating opportunities to enhance the future of electric vehicle (EV) charging. What are examples of the possibilities, and how could this progress affect electronics design engineers?

Start with determining the best EV charging locations. Many EV advocates assert that charging locations must be viable for professionals who spend long hours on the road in heavy-duty trucks. Although some managers have transitioned their fleets to electric vehicles, those switches can only exist as long-term, reliable options with the necessary infrastructure.

Take Amazon, for instance, which brought an open-source tool called Charging Location for Electric Trucks (CHALET) to Europe. People associated with the e-commerce company hope it will contribute to the region’s decarbonization strategies by supporting involved parties in deciding where to build future stations.

This data-driven tool allows users to enter specifics such as transit times, vehicle ranges, and battery statistics to generate ranked lists of the best places to put EV chargers. This innovation is part of a goal to invest more than €1 billion in five years to electrify and eliminate carbon emissions from Amazon’s European transportation network. In 2022, it began using fully electric 40-ton trucks in the European and U.K. markets. Thanks to CHALET, more businesses are expected to follow suit.

Figure 1 CHALET aims to help determine appropriate locations for charging stations. Source: Amazon

Once that happens, electronics design engineers should stay abreast of how to offer charging products that provide the reliability and fast speeds demanded by industry representatives. Those leaders will be much more likely to begin using EVs or expand their current usage if the foundational technologies can meet their stringent requirements.

Offering better EV charging visibility

Some consumers are warming up to owning electric vehicles, but they want assurances that the experience will be maximally convenient. Statistics indicate EVs comprised a 7.6% share of the U.S. market in 2023. However, some people interested in buying them worry about potential difficulties in finding charging points. Such challenges could become especially bothersome during road trips through unfamiliar areas.

So, a U.K. network operator has taken an open-source approach that other regions may adopt if it proves successful. The system uses an API that shows whether an area’s chargers are working or potentially dysfunctional due to power outages. Such information could help people plan their trips and avoid wasted time and disappointment caused by inoperable charging stations. Reduced frustration should make EV ownership more pleasant, encouraging people to make permanent changes.

One power supplier tested this open-source solution with EV users, and 94% of participants wanted to keep receiving the outage information once the trial concluded. That feedback resulted in the network operator creating an app with push notifications informing customers of planned or unplanned infrastructure disruptions and estimating restoration times.

This example shows why electronics design engineers should prioritize visibility and user-friendliness in their decisions. Most people appreciate visual features that confirm charging statuses. Still, it’s even better when they link with apps that show people the whole network and all available power points.

More consistency to charging protocols

One of the current challenges with some countries’ EV charging points is a lack of interoperability between the necessary communication protocols. However, representatives from the United States Joint Office of Energy and Transportation and the Linux Foundation believe open-source options could bring positive changes.

Figure 2 Open-source tools could significantly contribute to building a viable charging infrastructure. Source: Joint Office of Energy and Transportation

The entities will collaborate to develop and maintain independent, open-source tools that improve charging-related communications associated with vehicles and other EV industry components. This includes power grids and charging station payment apps. Those involved believe the efforts will improve interoperability and make charging a more reliable activity for EV owners.

This partnership could impact electronics design engineers because participants want to find solutions to facilitate better charging options for consumers and industrial users. They also aim to establish minimum standards that engineers and others can meet to streamline the development of highly effective real-world applications.

Although EVs are becoming more popular, people will be even more open to buying and using them if charging infrastructure is widely available, easy to use, and reliably functional. Here, open-source projects can support those goals and many others.

Ellie Gabel is a freelance writer as well as an associate editor at Revolutionized.

 

 

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STMicroelectronics, a prominent global semiconductor leader, has released its financial results for the second quarter ending June 29, 2024. The company reported net revenues of $3.23 billion, with a gross margin of 40.1%, an operating margin of 11.6%, and a net income of $353 million, translating to $0.38 diluted earnings per share.

Financial Highlights Jean-Marc Chery, President & CEO of STMicroelectronics

The second quarter saw STMicroelectronics (ST) achieving net revenues of $3.23 billion, which was slightly above the midpoint of the company’s business outlook. This performance was primarily driven by higher revenues in the Personal Electronics segment, partially offset by lower-than-expected revenues in the Automotive sector. The company’s gross margin of 40.1% was in line with expectations.

 

 

 

Jean-Marc Chery, President & CEO of STMicroelectronics, stated in the media briefing, “Q2 net revenues were above the midpoint of our business outlook range, driven by higher revenues in Personal Electronics, partially offset by lower-than-expected revenues in Automotive. Gross margin was in line with expectations.”

For the first half of 2024, ST reported net revenues of $6.70 billion, with a gross margin of 40.9%, an operating margin of 13.8%, and a net income of $865 million. However, year-over-year, the first half net revenues decreased by 21.9%, primarily due to declines in the Microcontrollers and Power and Discrete segments.

Segment Performance

The company’s performance varied across different product segments:

• Analog, Power & Discrete, MEMS and Sensors (APMS): This segment saw a year-over-year revenue decrease of 16.2%. Within this segment, Analog products, MEMS and Sensors (AM&S) revenues fell by 10.0%, mainly due to a decline in Imaging. Power and Discrete products (P&D) revenues dropped by 24.4%. The operating profit for AM&S decreased by 44.5% to $144 million, while P&D saw a 57.9% decline in operating profit to $110 million.
• Microcontrollers, Digital ICs and RF products (MDRF): This segment experienced a significant year-over-year revenue decrease of 35.5%. The Microcontrollers (MCU) segment alone saw a 46.0% drop in revenue, mainly due to a decrease in General Purpose MCU. The operating profit for the MCU segment plummeted by 87.1% to $72 million. In contrast, the Digital ICs and RF products (D&RF) segment’s revenue decreased by a modest 7.6%, with a 23.8% drop in operating profit to $150 million.

Strategic Focus Areas

1. Automotive: Despite the decline in demand, ST continues to execute its strategy to support car electrification. The company secured multiple wins in power discrete with both silicon-carbide and IGBT technologies for traction inverters at leading car manufacturers. Additionally, ST has announced a long-term Silicon Carbide supply agreement with Geely Auto for SiC power devices in their battery EVs and established a joint lab to explore innovative solutions for evolving automotive architectures.
2. Industrial: The anticipated stabilization of demand in the Industrial sector did not materialize, with customer orders remaining weak, particularly for general-purpose microcontrollers. Short-cycle businesses such as power tools, residential solar, lighting, and appliances continued to struggle, while longer-cycle businesses like energy storage, grid, EV charging, and process automation showed more resilience. Entering the second half of the year, ST faces a weaker-than-expected backlog.
3. Personal Electronics, Communications Equipment, and Computer Peripherals (CECP): Engaged customer programs in these sectors ran as expected, providing some stability amidst broader market volatility.

Market Challenges and Future Outlook

STMicroelectronics faced several challenges during the second quarter. Contrary to prior expectations, customer orders for Industrial applications did not improve, and demand in the Automotive sector declined. Chery noted, “During the quarter, contrary to our prior expectations, customer orders for Industrial did not improve and Automotive demand declined.”

Looking ahead, STMicroelectronics has set its business outlook for the third quarter of 2024. At the midpoint, the company expects net revenues of $3.25 billion, representing a year-over-year decrease of 26.7% and a sequential increase of 0.6%. The gross margin is anticipated to be around 38%, impacted by approximately 350 basis points of unused capacity charges.

Jean-Marc Chery outlined the company’s plan for the full fiscal year 2024, targeting revenues in the range of $13.2 billion to $13.7 billion, with an expected gross margin of about 40%.

Financial Summary

A detailed comparison of the financial results is as follows:

• Net Revenues: Decreased by 25.3% year-over-year to $3.23 billion in Q2 2024.
• Gross Profit: Decreased by 38.9% year-over-year to $1.30 billion.
• Operating Income: Decreased by 67.3% year-over-year to $375 million.
• Net Income: Decreased by 64.8% year-over-year to $353 million.
• Diluted Earnings Per Share: Decreased by 64.2% year-over-year to $0.38.

Cash Flow and Balance Sheet Highlights

For the second quarter, STMicroelectronics reported net cash from operating activities of $702 million, compared to $1.31 billion in the year-ago quarter. The company’s net capital expenditures (Capex) were $528 million, compared to $1.07 billion in the same period last year. Free cash flow, a non-U.S. GAAP measure, was $159 million, down from $209 million in Q2 2023.

The company’s inventory at the end of the second quarter stood at $2.81 billion, up from $2.69 billion in the previous quarter but down from $3.05 billion in the year-ago quarter. Days sales of inventory increased to 130 days, compared to 122 days in the previous quarter and 126 days in Q2 2023.

STMicroelectronics also highlighted its shareholder return initiatives, including $73 million in cash dividends and an $88 million share buyback, completing its $1,040 million share repurchase program launched in July 2021. In June 2024, the company announced a new share buyback plan comprising two programs totaling up to $1.1 billion to be executed over three years.

As of June 29, 2024, ST’s net financial position, a non-U.S. GAAP measure, was $3.20 billion, up from $3.13 billion as of March 30, 2024. The company’s total liquidity was $6.29 billion, with total financial debt of $3.09 billion. The adjusted net financial position, considering the effect of advances from capital grants, stood at $2.80 billion.

Manufacturing and Expansion

In May, STMicroelectronics announced the construction of a new high-volume 200mm silicon carbide manufacturing facility in Catania, Italy. This facility will produce power devices and modules, including both device manufacturing and testing and packaging. Alongside the SiC substrate manufacturing facility on the same site, these facilities will form ST’s Silicon Carbide Campus. This ambitious project is projected to be a €5 billion multi-year investment, supported by €2 billion from the State of Italy under the EU Chips Act.

During the quarter, ST also expanded its existing multi-year 150mm silicon carbide substrate wafers supply agreement with SiCrystal.

Future Outlook

Looking ahead to Q3 and beyond, STMicroelectronics expects continued challenges due to the current semiconductor cycle’s impact on various end markets, inventory adjustments, and the nonlinear acceleration of structural trends towards sustainability. The company has revised its full-year 2024 revenue projection between $13.2 billion and $13.7 billion, representing a decline of about 22% at the midpoint compared to 2023.

The company continues to invest in R&D and strategic initiatives, such as the ST Edge AI Suite, which simplifies and accelerates edge-AI application development.

The Way Forward

STMicroelectronics is navigating a complex and volatile semiconductor market with a mix of strategic adaptations and long-term investments. The company’s ability to weather the storm will depend on its agility in adjusting to market dynamics and its continued focus on innovation and customer engagement. With a Capital Markets Day scheduled for November 20th in Paris, stakeholders will have an opportunity to gain further insights into ST’s strategic direction and growth ambitions.

The post STMicroelectronics Reports Financial Results for Q2 2024- Navigating with focus on Innovation & Customer engagement appeared first on ELE Times.

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