Новини світу мікро- та наноелектроніки

This is the Microchip MCP41xxx digital potentiometer data sheet that includes (on page 15, their Figure 4-4) an interesting application circuit comprising a Dpot controlled amplifier with pseudologarithmic gain settings. However, as explained in the Microchip text, the gains implemented by this circuit start changing radically as the control setting of the pot approaches 0 or 256. As Microchip puts it: “As the wiper approaches either terminal, the step size in the gain calculation increases dramatically. This circuit is recommended for gains between 0.1 and 10 V/V.”

That’s good advice. Unfortunately, following it would effectively throw away some 48 of the 256 8-bit pot settings, amounting to a loss of nearly 20% of available resolution. The simple modification shown in Figure 1 gets rid of that limitation.

Figure 1 Two fixed resistors are added to bound the gain range to the recommended limits while keeping full 8-bit resolution.

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This results in the gain vs code red curve of Figure 2.

Figure 2 Somewhat improved pseudologarithmic gain curve from the simple modification shown in Figure 1.

However, despite this improvement, the key term remains pseudologarithmic. It still isn’t a real log function and, in fact, isn’t quantitatively even that close, deviating by almost a factor of two in places. Can we do better? Yes!

The simple (software) trick is to prepare a 257-byte logarithmic lookup table that translates the 0.1 to 10.0 gain range settings to the Dpot codes needed to logarithmically generate those gains.

Let’s call the table index variable J. Then for a 257-byte table of (abs) gains G from 0.1 to 10.0 inclusive,

J(G) = (128 LOG10(abs(G)) + 128)
…examples…
J(0.1) = 0,
J(0.5) = 89,
J(1.0) = 128,
J(10.0) = 256,
etc.

Inspection of the gain expression in Figure 1 reveals that the Dpot decimal code N required for (abs) gain G is:

N(G) = (284.4G – 28.4)/(G + 1)
…thus…
N(.1)  = (28.4 – 28.4)/(.1 + 1) = 0/1.1 = 0,
N(.5)  = (142 – 28.4)/(.5 + 1) = 114/1.5 = 76,
N(1.0) = (284.4 – 28.4)/(1 + 1) = (256)/2 = 128,
N(10.0) = (2844 – 28.4)/(10 + 1) = 2816/11 = 256,
etc.

Figure 3 summarizes the resulting relationship between G, J, and N. 

Figure 3 The Dpot settings [N(J)] versus log table indices [J(G)], summarizing the relationship between G, J, and N.

The table of log gains can be found in this excel sheet. The net result, with as good log conformity as 8 bits will allow, is exhibited as Figure 4’s lovely green line.

Figure 4 The absolute gain [Gabs = 10(J/128 -1)] versus decimal code (J).

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• Keep Dpot pseudologarithmic gain control on a leash
• Synthesize precision Dpot resistances that aren’t in the catalog
• Reducing error of digital potentiometers
• Adjust op-amp gain from -30 dB to +60 dB with one linear pot
• Op-amp wipes out DPOT wiper resistance

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Meaning of data transformation

Data transformation is the process of converting data from one format or structure into another format or structure.  For instance, converting a raw dataset into a well arranged, scientifically analysed, vetted, and a user-friendly format.

As the aim of data transformation is to present the data into a very user-friendly format, it invariably involves converting dataset from one format of file into another format. For instance, CSV (comma separated values), excel spreadsheet, XML (extensible markup language), etc.

It involves conversion of both the format and/ or structure of a data set into a format or structure that is congruent to the requirements of the target system.

Aim of data transformation

The aim behind executing any data transformation process is to ensure that the available data is scientifically arranged, well-analysed, vetted from reliable sources and as per the internationally accepted standards, and presented in a user-friendly format.

This ensures that the decision making based on the available data is rational, logical, scientific, and correct to the best of knowledge. Hence, it aids in analyses and developing insights. Besides, further analyses of the data available after executing the process of data transformation brings to fore some of the hitherto unexplored facts or dimensions about any topic.

Data transformation is only change in the format of the data and not the content of the data

An important feature of data transformation is that it only involves conversion of data from one format to another. It does not change anything in the content of the data.

Who are the people involved in the process of data transformation?

Majorly, the data engineers, data analysts, and data scientists collaborate amongst each other to execute the process of data transformation.

Processes involved in data transformation

Data transformation is executed by accomplishing three processes. They are as follows:

First, data integration.

Second, data migration.

Third, warehousing.

Phases of data transformation

Data transformation is accomplished over five phases. They are as follows:

First, data discovery.

Second, data mapping.

Third, code generation.

Fourth, code execution.

Fifth, data review.

Classification of the process of data transformation

The process of data transformation is classified into four types. They are as follows:

First, constructive data transformation. In this type, data is copied, replicated, or added.

Second, destructive data transformation. In this type, data pertaining to fields or records is deleted.

Third, structural data transformation. In this type, columns in data is combined, moved or renamed.

Fourth, aesthetic data transformation. In this type, data pertaining to certain values are standardized.

Significance of data transformation

First, data transformation is a critical stage of both the ETL (Extract, Transform, Load) and ELT (extract, load, transform) processes.

The difference between the ETL approach and the ELT approach is that the ETL approach uses a fixed criteria to sort data from multiple sources before compiling it a central place. On the other hand, the ELT approach aggregates data as it is from the beginning and then transforms it later depending upon the requirements of the case and analytics.

Second, data transformation is an important aspect of big data analytics. Hence, it is of immense importance in today’s age of big data, an age when the data is already huge in volume and is rapidly growing in gargantuan proportions.

Common life examples of data transformation

Data transformation is undertaken in various applications in our life. Few such examples are as follows:

First, converting file from CSV format to XML format.

Second, conversion of speech into text by means of speech conversion software.

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Fraunhofer Institute for Applied Solid State Physics (IAF) of Freiburg, Germany has used metal-organic chemical vapor deposition (MOCVD) to fabricate and characterize aluminum yttrium nitride (AlYN), enabling the development of new, diverse applications...

The companies enable an interoperable coherent optics ecosystem that can help streamline the development of data center interconnect and metro transport systems

The latest data center architectures and increased traffic are driving higher bandwidth requirements between data centers. To address this challenge, system developers must streamline the development of a new generation of 1.2 Tbps (1.2T) transport solutions across a wide range of client configurations. This requires that today’s terabit-scale Ethernet PHY devices and coherent optical modules interoperate with each other in Data Center Interconnect (DCI) and metro transport networks. Microchip Technology today announces that it has worked with Acacia to demonstrate the fourth generation of interoperability between Microchip’s META-DX2 Ethernet PHY family and Acacia’s Coherent Interconnect Module 8 (CIM 8).

The two companies’ interoperable devices enable low-power, bandwidth-optimized, scalable solutions for pluggable optics in DCI and transport networks. They deliver three key benefits as they jointly enable high-capacity, multi-rate muxponders for optical transport platforms:

• Optimized DCI bandwidth: The META-DX2 family, through its META-DX2+ PHY, uses its unique Lambda Splitting feature to split 400 GbE or 800 GbE clients across multiple wavelengths driven by the CIM 8 modules. This maximizes the capacity between data centers in rate configurations such as 3×800 GbE over 2×1.2 Tbps waves or 5×400 GbE over 2×1.0 Tbps waves.
• Reduced design risk: Microchip and Acacia have jointly verified successful SerDes interoperation at up to 112G per lane for Ethernet and OTN clients, which reduces design validation and system qualification requirements.
• Better support for full bandwidth, multi-rate operation: The META-DX2+ crosspoint and gearbox functions enable 100 GbE to 800 GbE client modules to connect with full bandwidth to CIM 8 modules.

“This interoperability extends a long-established partnership with Acacia to help accelerate and optimize the build-out of cloud computing and AI-ready optical networks while reducing development risk for our customers,” said Maher Fahmi, vice president for Microchip’s communications business unit. “Our META-DX2 is the first solution of its kind to integrate 1.6T of encryption, port aggregation and Lambda Splitting into the most compact 112G PAM4 device in the market.”

“With Acacia’s CIM 8 coherent modules verified to interoperate with Microchip’s META-DX2 devices, we see this as a robust solution that reduces system time-to-market,” said Markus Weber, senior director DSP product line management of Acacia. “The compact size and power efficiency of our CIM 8 coherent modules were designed to help network operators deploy and scale capacity of high-bandwidth DWDM connectivity between data centers and throughout transport networks.”

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Welcome to my where’s Waldo themed workbench also it’s Wednesday in New zealand so i’d say this counts. List of stuff to find: • DSSTC H-bridge(50 points) • tesla coil secondary(10 points) • multimeter(1 point because its easy to find) • drill battery(5 points) • Variac(20 points) • shunt resistor (you win instantly and gain the achievement: how tf?) Comment you’re score try and beat my high-score of 0 (I have no idea where anything is anymore lol) submitted by /u/jjiscool_264 [link] [comments]

Infineon Technologies AG has announced the expansion of its Bluetooth portfolio by eight new products in the AIROC CYW20829 Bluetooth Low Energy 5.4 microcontroller (MCU) family, featuring Systems-on-Chip (SoCs) and modules optimized for industrial, consumer, and automotive use cases. The high integration of the CYW20829 product family allows designers to reduce bill-of-material (BOM) cost and device footprint in a wide variety of applications, including PC accessories, low-energy audio, wearables, solar micro inverters, asset trackers, health and lifestyle, home automation and others. Product designers also benefit from Infineon’s rich development infrastructure and commitment to robust security, with support for secure boot and execution environments and cryptography acceleration to safeguard sensitive data.

The latest automotive part in the product family, the AIROC CYW89829 Bluetooth Low-Energy MCU, is ideal for car access and wireless battery management systems (wBMS) applications, due to its robust RF performance, long range and latest Bluetooth 5.4 features including PAwR (Periodic Advertising with Responses). The dual ARM Cortex core design of the chip family features separate application and Bluetooth Low Energy subsystems that deliver full featured support for Bluetooth 5.4, low-power, 10 dBm output power without a PA, integrated flash, CAN FD, crypto accelerators, high security including Root of Trust (RoT), and is PSA level 1 ready.

“Infineon offers one of the industry’s broadest portfolios of IoT solutions. Our Bluetooth solutions offer robust connectivity and the latest features,” said Shantanu Bhalerao, Vice President of the Bluetooth Product Line, Infineon Technologies. “Our automotive AIROC CYW89829 Bluetooth LE MCU, and versatile AIROC Bluetooth CYW20829 LE MCU deliver ultra-low power and a high degree of integration for a better user experience across various applications in automotive, industrial, and consumer markets.”

Infineon has been working with customers to design with current products in the CYW20829 family and has received positive reviews:

“The Infineon CYW20829 is the leading Bluetooth part in the market, which has passed the latest Bluetooth 5.4 certification,” said Kevin Wang, CEO of ITON. “CYW20829 has very good RF performance, supports PAwR and LE Audio. These features bring more possibilities in consumer and industrial markets.”

“CYW20829, with perfect RF performance, flexible API, and good long-range features, provides a good solution for commercial lighting, industrial IoT, and more,” said Cai Yi, CEO of Pairlink.

“Earlier this year, the Bluetooth SIG released version 5.4 of the specification with new features: Periodic Advertising with Responses and Encrypted Advertising Data. These features implemented on Infineon’s CYW20829 chips allow Addverb to develop a secure monitoring and controlling system for a fleet of wireless robots in the industrial warehouse, satisfying safety requirements,” said Tapan Pattnayak, Chief Scientist at Addverb, a global leader in robotics.

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I'm wondering how to reconnect this so maybe I can make a rechargeable mic? submitted by /u/lilyxcatnap [link] [comments]

I hate myself I hate myself I hate myself I hate myself I hate myself I hate myself submitted by /u/BlownUpCapacitor [link] [comments]

Editor’s note: The first part of this two-part design idea (DI) shows how modifications to an oscillator can produce a useful and unusual pulse generator. The second part will extend this to step function generation.

The principle behind testing the impulse response of circuits is simple: hit them with a sharp pulse and see what happens. As usual, Wikipedia has an article detailing the process. This notes that the ideal pulse—a unit impulse, or Dirac delta—is infinitely high and infinitely narrow with an area beneath it of unity, so it’s infinitely tricky to generate, which is just as well, considering the effects one would have on everything from protection diodes to slew rates. Fortunately, it’s just an extreme case of the normal or Gaussian distribution, or bell curve, which is a tad easier to generate or at least emulate and, which this DI shows how to do.

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In the real world, the best testing impulses come from arbitrary waveform generators. An older technique is to filter narrow rectangular pulses, but if you change the pulse width, the filter’s characteristics also need to be varied to maintain the pulse shape. The approach detailed in here avoids that problem by generating raised cosine pulses (not to be confused with raised-cosine filters) which are close enough to the ideal to be interesting. But let’s be honest: simple rectangles, slightly slugged to avoid those slew-rate problems, are normally quite adequate.

Producing our pulses

We make our pulses by taking the core of a squashed-triangle sine-wave oscillator and adding some logic and gating so that when triggered, it produces single cycles which rise from a baseline to their peak and then fall back again, following a cosine curve. The schematic in Figure 1 shows the essentials.

Figure 1 A simple oscillator with some added logic generates single pulses when triggered.

How the oscillator works

The oscillator’s core is almost identical to the original, though it looks different having been redrawn. Its basic form is that of an integrator-with-Schmitt, where C1 is charged up through resistors R2 and R3 until its voltage reaches a positive threshold defined by D3, which flips A1b’s polarity, so that C1 starts to discharge towards D4’s negative threshold. D1/D2 provide bootstrapping to give linear charge/discharge ramps while compensating for variations in D3/D4’s forward voltages with temperature (and supply voltage, though that should not worry us here). The resulting triangle wave on A2’s output is fed through R7 into D5/D6 which squash it into a reasonable (co)sine wave (<0.5% THD). The diode pairs’ forward voltages need to be matched to maintain symmetry and so minimize even-harmonic distortion. A4 amplifies the signal across D5/6 so that the pulse just spans the supply rails, thermistor Th1 giving adequate compensation for temperature changes.

If A2’s output were connected directly to R1’s input, the circuit would oscillate freely—and we’ll allow it to later on—but for now we need it to start at its lowest point, make one full cycle, and then stop.

In the resting condition, U2a is clear and A1b’s output is high, producing a positive reference voltage across D3. (That’s positive with respect to the common, half-supply internal rail.) That voltage is inverted by A2a and applied through U1a to R1, so that there is negative feedback round the circuit, which stabilizes at the negative reference. (Using a ‘4053 for U1 may seem wasteful, but the other sections of it will come in handy in Part 2.)

When U2a’s D input sees a (positive-going) trigger, its outputs change state. This way, U1a connects R1 to A1b’s (still high) output, starting the cycle; the feedback is now positive. After a full cycle, A1b’s output goes high again, triggering U2b and resetting U2a, thus stopping the cycle and restoring the circuit to its resting state. The relevant waveforms are shown in Figure 2.

Figure 2 Some waveforms from the circuit in Figure 1.

Comparing raised cosines with ideal normal-distribution pulses is instructive, and Figure 3 shows both. While most of the curves match reasonably, the bottom third or so is somewhat wanting, though it can be improved on with some extra complexity—but that’s for later.

Figure 3 A comparison between an ideal normal-distribution curve and a raised cosine, including the output from Figure 1.

As previously mentioned, and apparent from the schematic, the circuit works as a simple oscillator if U2a’s operation is disabled by inhibiting its trigger input and jamming its preset input low to force its Q high and Q low. U1a now connects A1b’s output to R1, and the circuit runs freely. Apart from being useful as a feature, this helps us to set it up.

Trimming the oscillator

A few trims, in the oscillator mode, are needed to get the best results.

1. R3 must be set to give equal tri-wave amplitudes at the maximum and minimum settings of R2, or distortion will vary with frequency (or pulse width). Set R2 to max (lowest frequency) and R3 to min (towards the right on the schematic), then measure the amplitude at A1’s output. Now set R2 to min and adjust R3 to give the same amplitude as before. (Thanks to Steve Woodward for the idea behind this.)
2. R7 defines the drive to the squashing diodes D5/6 and thus the distortion. Using a ‘scope’s FFT is preferable: adjust R7 to minimize the third and fifth harmonics. (The seventh remains fairly constant.) Failing that, set R7 so that the voltage across the diodes is precisely 2/3 of the tri-wave’s value. As a last resort, a 30k fixed resistor may be close enough, as it was in my build.
3. Set the output level using R9. The waveform should run from rail to rail, just shaving the tips of the residual pips (which are mainly responsible for those seventh harmonics) from the peaks. Don’t overdo it, or the third and fifth harmonics will start to increase. This depends on using RRO op-amps for at least A1b and A2b and carefully-split rails for symmetry.

Once trimmed as an oscillator, it’s good to go as a pulse generator, which relies on exactly the same settings, so that each pulse will be a single cycle of a cosine wave, offset by half its amplitude.

The schematic in Figure 1 gives the bare bones of the circuit, which will be fleshed out in Part 2. The op-amps used are Microchip MCP6022s, which are dual, 5-V, 10-MHz CMOS RRIO devices with <500 µV input offsets. Power is at 5 V, with the central “common” rail derived from another op-amp used as a rail-splitter: shown in Figure 4 together with a suitable output buffer.

Figure 4 A simple rail-splitter to derive the 2.5-V “common” rail, and an output level control and buffer with both AC- and DC-coupled outputs.

C1 can be switched to give several ranges, allowing use from way over 20 kHz (for 25 µs pulses, measured at half their height) down to as low as you like. R3 then also needs to be switched; see Figure 5 for a three-range version. (The lowest range probably won’t need an HF trim.) While the tri-wave performance is good to around 1 MHz, the squashing diodes’ capacitance starts to introduce waveform distortion well before that, at least for the 1N4148 or the like.

Figure 5 For multi-range use, timing capacitor C1 is switched. To trim the HF response for each range, R3 must also vary.

Improving the pulse shape

Now for that extra complexity to improve the pulse shape. In very crude terms, the top half of the desired pulse looks (co)sinusoidal but the bottom more exponential, and that part must be squashed even further if we want a better fit. We can do that by bridging D6 with a series pair of Schottky diodes, D7 and D8. The waveform’s resulting asymmetry needs offsetting, necessitating a slightly higher gain and different temperature compensation in the buffer stage A2b. These mods are shown in Figure 6.

Figure 6 Bridging D6 with a pair of Schottky diodes gives a better fit to the desired curve, though the gain and offset need adjusting.

In this mode, R16 sets the offset and R9A the gain. The three sections of U3 will:

• Switch Schottkys D7/8 into circuit
• Select the gain- and offset-determining components according to the mode
• Short out R8 to place the thermistor directly across R12 and optimize the temperature compensation of the pulse’s lower half

Figure 7 shows the modified pulse shape. Different diodes or combinations thereof could well improve the fit, but this seems close enough.

Figure 7 The improved pulse shape resulting from Figure 6.

To set this up, adjust R16 and R9A (which interact; sorry about that) so that the bottom of the waveform is at 0 V while the peaks are at a little less than 5 V. Because the top and bottom halves of each pulse rely on different diodes, their tempcos will be slightly different. The 0-V baseline is now stable, but the peak height will increase slightly with temperature.

To be continued…

By now, we’ve probably passed the point at which it’s simpler, cheaper, and more accurate to reach for a microcontroller (Arduino? RPi?) and add a DAC—or just use a PWM output, at these low frequencies—equip it with look-up tables (probably calculated and formatted using Python, rather like the reference curves in these Figures) and then worry about how to get continuous control of the repetition rate and pulse width. Or even just buy a cheap AWG, which is cheating, though practical.

But all that is a different kind of fun, and we have not yet finished with this approach. Part 2 will show how to add more tweaks so that we can also generate well-behaved step-functions.

—Nick Cornford built his first crystal set at 10, and since then has designed professional audio equipment, many datacomm products, and technical security kit. He has at last retired. Mostly. Sort of.

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• Squashed triangles: sines, but with teeth?
• Dual RRIO op amp makes buffered and adjustable triangles and square waves
• Arbitrary waveform generator waveform creation using equations
• 555 triangle generator with adjustable frequency, waveshape, and amplitude; and more!
• Adjustable triangle/sawtooth wave generator using 555 timer
• Voltage-controlled triangle wave generator

The post How to control your impulses—part 1 appeared first on EDN.

While physical layer (PHY) interconnect IP has been making headlines after the emergence of the Universal Chiplet Interconnect Express (UCIe) specification, a Korean design house has announced the availability of controller IP that complies with the UCIe 1.1 standard.

The PHY part in UCIe encompasses link initialization, training, power management states, lane mapping, lane reversal, and scrambling. On the other hand, UCIe’s controller part includes the die-to-die adapter layer and the protocol layer.

Openedges Technology calls it OUC, and it derives its name from the term Openedges UCIe controller. Openedges, a supplier of memory subsystem IP, is based in Seoul, South Korea. Its controller IP extends on-chip AXI interconnections to multi-die connections to deliver multi-die connectivity across diverse applications.

The chiplet controller IP employs flits or flow control units for reliability and latency, thus preventing overflow at the receiver buffer. It also ensures seamless communication by synchronizing AXI parameters with its link partner, accommodating different AXI configurations through padding and cropping as per the default operation rules defined in AXI.

The highly configurable UCIe controller IP facilitates die-to-die interconnect and protocol connections. Source: Openedges Technology

In short, the new controller IP effortlessly integrates with the company’s on-chip interconnect IP. That synergy simplifies multi-chiplet interconnects while facilitating efficient bandwidth transfer capabilities.

Related Content

• TSMC, Arm Show 3DIC Made of Chiplets
• Chiplets Get a Formal Standard with UCIe 1.0
• How the Worlds of Chiplets and Packaging Intertwine
• Cadence and Arm launch ADAS chiplet development platform
• Imec’s Van den hove: Moving to Chiplets to Extend Moore’s Law

The post Chiplets diary: Controller IP complies with UCIe 1.1 standard appeared first on EDN.