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Editor’s note: The first part of this two-part design idea (DI) shows how modifications to an oscillator can produce a useful and unusual pulse generator; this second and final part extends that to step functions.

 In the first part of this DI, we saw how to gate an oscillator to generate well-behaved impulses. Now we find out how to extend that idea to producing well-behaved step functions, or nicely smoothed square waves.

The ideal here is the Heaviside or unit step function, which has values of 0 or 1 with an infinitely sharp transition between them. Just as the Dirac delta impulse which we met in Part 1 is the extreme case of a normal distribution or bell curve, the Heaviside is the limit of the logistic function (which I gather logisticians use about as often as plumbers do bathtub curves).

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Square wave with smooth edges

Anyone working with audio kit will have employed square-wave testing with that infinity tamed by an RC time-constant, which is good enough for everyday use, but another approach is to replace that still-sharp step with a portion of a cosine wave. Taking the circuit from Part 1 and adding some more gating means that instead of generating a full raised-cosine pulse for every trigger input, we get a half cycle at each transition, with alternating polarities. The result: a square wave at half the frequency of the trigger and with smooth edges. The revised circuit is in Figure 1.

Figure 1 Extra logic added to the original circuit now gives half a cosine on each trigger pulse, with alternating polarities, generating a square wave with smoothed edges.

In pulse or oscillator modes, U1b delivers a reset to U2 whenever A1b’s output goes high, which gives a full cycle of the raised cosine. In the square wave mode, U2 is reset whenever A1b changes, irrespective of polarity, at the half-cycle point. U1b and U3b/c act as a gated EXOR with delays through one leg to generate the reset pulse. Some waveforms are shown in Figure 2; compare these with those in Figure 2 of Part 1. As before, A2 is jammed when the oscillator mode is selected, forcing continuous, sine-wave operation.

Figure 2 Some waveforms from the circuit in Figure 1.

A single, positive-going transition is shown in Figure 3, with our target curve for comparison. These are both theoretical plots, but the actual output is very close to the cosine.

Figure 3 The target step-function is a logistic curve; a segment of a cosine is shown for comparison.

In Part 1, we tried to get closer to a normal distribution curve by some extra squashing of our tri-wave. This worked up to a point but was clunkily over-elaborate, partly owing to the waveform’s lack of symmetry. We now have a symmetrical function to aim at, which should be easier to emulate.

Building our target curve

The spare section of mux U1 together with three new resistors offers a neat solution, and the circuit fragment in Figure 4 shows how.

Figure 4 Adding the components in red gives a much better fit to our target curve. The tri-wave amplitude is increased and can now be squashed even more.

Putting 47k (R14) in series with D3/4 increases the trip points’ levels, so that the tri-wave now spans ~4.3 V rather than ~1.1 V. The increased drive to D5/6 through R7 results in the diodes not so much squashing the triangle into a (co)sine as crushing it into something much squarer though with greater amplitude. R24 and R25, connected across D7/8, pot the voltage across the diodes down so that the peaks—which are now gentle curves—are cropped by A2b’s (rail-to-rail) output. (The resistive loading of D7/8 slightly softens their response, which also helps.)

U1c does two jobs. When pulses or a continuous sine wave are to be generated, it shorts out R14 and opens R24, giving our standard operating conditions, but in square-wave mode, R14 is left in circuit while R24 is grounded, as needed for the extra tri-wave amplitude and crushing.

The waveforms now look like Figure 5 (note the change of scale for trace C) while a single, actual edge is shown in Figure 6 with a theoretical, ideal step for comparison—and the match is now very good.

Figure 5 Waveforms after adding the mods shown in Figure 4.

Figure 6 Comparison of the target curve with part of the trace D in Figure 5.

There is some fudging involved here, the two curves in Figure 6 having been adjusted for the same slope at the half-height point. Because R24/R25 reduce the amplitude of the signal across the diodes by nearly 20%, the slope will also be that much shallower than for the cosine version, which is not a practical problem.

The final circuit

To turn all this into a functional piece of kit ready for doing some audio testing, we need to add some extras:

• A rail-splitter to define the central, common rail
• Level-control pot with an output buffer
• Simple oscillator to produce the trigger pulses, with an input so that an external TTL signal can override the internal one
• A switch to select the mode.

Putting all these together, we reach the full and reasonably final circuit of Figure 7. Multiple ranges can easily be accommodated by adding the extras detailed in Part 1, Figure 5. The modified pulse-shaping circuit shown in Part 1, Figure 6 could also be added, but may be more fiddly than it is worth.

Figure 7 The full circuit, which now produces square waves with well-shaped edges as well as pulses and continuous sine waves.

The absence of pin numbers is deliberate, because their inclusion would imply an optimized layout. Be careful to keep the logic signals away from analog ones, especially at and around the earthy end of R24, which can pick up switching spikes when open-circuited. U1’s E-not (pin 6) and VEE (pin 7) must be at 0 V.

While this approach to generating nicely-formed pulses is perhaps more interesting than accurate, it does show that crunching up triangles with diodes is not limited to generating sine(ish) waves, which was the starting-point for this idea. For anything more complex, an AWG is probably a better solution, if less fun.

—Nick Cornford built his first crystal set at 10, and since then has designed professional audio equipment, many datacomm products, and technical security kit. He has at last retired. Mostly. Sort of.

Related Content

• How to control your impulses—part 1
• Squashed triangles: sines, but with teeth?
• Dual RRIO op amp makes buffered and adjustable triangles and square waves
• Arbitrary waveform generator waveform creation using equations
• 555 triangle generator with adjustable frequency, waveshape, and amplitude; and more!
• Adjustable triangle/sawtooth wave generator using 555 timer

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Hybrid bonding—a significant advancement in chip packaging technology—is becoming vital in heterogeneous integration, which enables semiconductor companies to merge multiple chiplets with diverse functions, process nodes, and sizes into a unified package. It vertically links die-to-wafer or wafer-to-wafer via closely spaced copper pads, bonding the dielectric and metal bond pads simultaneously in a single bonding step.

However, the enhanced reliability and mechanical strength of its interconnects compared to traditional bump-based interconnections don’t come without challenges. For instance, to successfully transition to high-volume manufacturing with high yields, it requires advanced metrology tools that can quickly identify defects such as cracks and voids within the bonded layers.

PVA TePla OKOS, a Virginia-based manufacturer of industrial ultrasonic non-destructive (NDT) systems, claims to have a solution based on scanning acoustic microscopy (SAM). A non-invasive and non-destructive ultrasonic testing method, SAM is quickly becoming the preferred technique for testing and failure analysis involving stacked dies or wafers, according to Hari Polu, president of PVA TePla OKOS.

SAM utilizes ultrasound waves to non-destructively examine internal structures, interfaces, and surfaces of opaque substrates. The resulting acoustic signatures can be constructed into 3D images that are analyzed to detect and characterize device flaws such as cracks, delamination, inclusions, and voids in bonding interfaces. The images can also be used to evaluate soldering and other interface connections.

Figure 1 SAM is becoming a preferred technique for testing and failure analysis involving stacked dies or wafers. Source: PVA TePla OKOS

SAM—an industry standard for inspection of semiconductor components to identify defects such as voids, cracks, and delamination—has been adapted to facilitate 100% inspection of hybrid bonded packages, says Polu.

How it works

In hybrid bonding, various steps must be reliably performed to ensure quality. The process starts with manufacturing the wafers or dies in a semiconductor fab before the chips are bonded together. The next key steps include the preparation and creation of the pre-bonding layers, the bonding process itself, the post-bond anneal, and the associated inspection and metrology at each of the step.

However, in conventional SAM techniques, wafers are held horizontally in a chuck and processed in a water medium. That, in turn, could lead to water ingress, which could cause significant issues in the next step of assembly. On the other hand, by re-designing the chuck in a vertical orientation, engineers can use gravity to eliminate any concern over water ingress while also using other water management technologies.

Here, SAM directs focused sound from a transducer at a small point on a target object. The sound hitting the object is either scattered, absorbed, reflected, or transmitted. As a result, the presence of a boundary or object and its distance can be determined by detecting the direction of scattered pulses as well as the time of flight. Next, samples are scanned point by point and line by line to produce an image.

Figure 2 SAM stands ready to deliver 100% non-destructive inspection of vertically stacked and bonded die-to-wafer or wafer-to-wafer packages to help facilitate the adoption of hybrid bonding. Source: PVA TePla OKOS

It’s important to note that scanning modes range from single-layer views to tray scans and cross-sections and that multi-layer scans can include up to 50 independent layers. The process can extract depth-specific information and apply it to create 2D and 3D images. Then, the images are analyzed to detect and characterize flaws like cracks, delamination, and voids.

The AI boost

Polu is confident that advancements in artificial intelligence (AI)-based analysis of the data collected from SAM inspection of wafer-to-wafer hybrid bonding will further automate quality assurance and increase fab production. “Innovations in the design of wafer chucks, array transducers, and AI-based analysis of inspection data are converging to provide a more robust SAM solution for fabs involved in hybrid bonding,” he said.

So, when fabs take advantage of the higher level of failure detection and analysis, the production yield and overall reliability of high-performance chips improve significantly. “Every fab will eventually move toward this level of failure analysis because of the level of detection and precision required for hybrid bonding,” Polo concluded.

Especially when the stakes are higher than ever because one bad wafer, die, or interconnection could cause the entire package to be discarded down the line.

Related Content

• EAG Adds IC Analytical Tools
• The Importance of 3D IC Ecosystem Collaboration
• CEA-Leti Presents TSVs that Promise Smarter Cameras
• Applied Materials, IME Extend Hybrid Bonding Research
• Intel and FMD’s Roadmap for 3D Heterogeneous Integration

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For second-quarter 2024, Guerrilla RF Inc (GRF) of Greensboro, NC, USA has reported revenue of $6.1m, up 61.7% on $3.8m a year ago. The firm develops and manufactures radio-frequency integrated circuits (RFICs) and monolithic microwave integrated circuits (MMICs) for wireless OEMs in markets including network infrastructure for 5G/4G macro and small-cell base stations, SATCOM, cellular repeaters/DAS, automotive telematics, military communications, navigation, and high-fidelity wireless audio...

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In this article, we'll learn the basics of switching-mode RF amplifiers in general and Class D amplifiers in particular.

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Whether in-home or in a dense commercial network, Microchip’s EV charger designs give designers access to new features straight out of the box.

Moog’s Cascade single-board computer supports multiple payloads and spacecraft bus processing needs within a single radiation-hardened unit. Cascade was created through an R&D partnership with Microchip Technology, as part of NASA’s early-engagement ecosystem for its next-gen High-Performance Spaceflight Computing (HPSC) processor.

The SBC is based on Microchip’s PIC64-HPSC, a radiation-hardened microprocessor with 10 64-bit RISC-V cores. In addition to advanced computing power, the processor provides an Ethernet TSN Layer 2 switch for data communications, fault tolerance and correction, secure boot, and multiple levels of encryption.

Available with or without an enclosure, Cascade is an extended 3U SpaceVPX board that conforms to the Space Standards Open Systems Architecture (Space SOSA) standard for maximum interoperability. The rad-hard SBC can withstand a total ionizing dose (TID) of 50 krad without shielding and has a single event latchup (SEL) tolerance of 78 MeV/cm² after bootup.

For more information about the Cascade SBC, click the product page link below.

Cascade product page

Moog

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Percept current sensors from Molex employ a coreless differential Hall-effect design and proprietary packaging to slash both size and weight. The sensor-in-busbar configuration allows for simple plug-and-play installation in automotive and industrial current sensing applications, such as inverters, motor drives and EV chargers.

Percept integrates an Infineon coreless magnetic current sensor in a Molex package to create a component that is 86% lighter and up to half the size of competing current sensors. The design also suppresses stray magnetic fields and reduces sensitivity and offset errors. 

Automotive and industrial-grade Percept sensors are available in current ranges from ±450 A to ±1600 A, with ±2% accuracy over temperature. They offer bidirectional sensing with options for full-differential, semi-differential, and single-ended output modes. AEC-Q100 Grade 1-qualified devices operate across a temperature range of -40°C to +125°C.

Sensors for industrial applications are expected to be available in October 2024, with the automotive product approval process scheduled for the first half of 2025. Limited engineering samples for industrial applications are available now.

Percept product page

Molex

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TDK-Lambda expands its i7A series of non-isolated step-down DC/DC converters with seven 500-W models that provide 20 A of output current. The converters occupy a standard 1/16th brick footprint and use a standardized pin configuration.

With an input voltage range of 28 V to 60 V, the new converters offer a trimmable output of 3.3 V to 32 V and achieve up to 96% efficiency. This high efficiency reduces internal losses and allows operation in ambient temperatures ranging from -40°C to +125°C. Additionally, an adjustable current limit option helps manage stress on the converter and load during overcurrent conditions, enabling precise adjustment based on system needs.

The 20-A i7A models are available in three 34×36.8-mm mechanical configurations: low-profile open frame, integrated baseplate for conduction cooling, and integrated heatsink for convection or forced air cooling.

Samples and price quotes for the i7A series step-down converters can be requested on the product page linked below.

i7A series product page

TDK-Lambda 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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A discrete graphics processing unit (dGPU), the Arc A760A from Intel delivers high-fidelity graphics and AI-driven cockpit capabilities in high-end vehicles. According to Intel, the dGPU supports smooth and immersive AAA gaming and responsive, context-aware AI assistants.

The Arc A760A marks Intel’s entry into automotive discrete GPUs, complementing its existing portfolio of AI-enhanced, software-defined vehicle (SDV) SoCs with integrated GPUs. Together, these devices form an open and flexible platform that scales across vehicle trim levels. Automakers can start with Intel SDV SoCs and later add the dGPU to handle larger compute workloads and expand AI capabilities.

Enhanced personalization is enabled by AI algorithms that learn driver preferences, adapting cockpit settings without the need for voice commands. Automotive OEMs can transform the vehicle into a mobile office and entertainment hub with immersive 4K displays, multiscreen setups, and advanced 3D interfaces.

Intel expects the Arc A760A dGPU to be commercially deployed in vehicles as soon as 2025. Read the fact sheet here.

Intel

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The Raspberry Pi Pico 2 single-board computer is powered by the RP2350 MCU, featuring two Arm cores or optional RISC-V cores. This $5 computer board also boasts higher clock speeds, twice the memory, enhanced security, and upgraded interfacing compared to its predecessor, the Pico 1.

Designed by Raspberry Pi, the RP2350 MCU leverages a dual-core, dual-architecture with a pair of Arm Cortex-M33 cores and a pair of Hazard3 RISC-V cores. Users can select between the cores via software or by programming the on-chip OTP memory. Both the Arm and RISC-V cores run at clock speeds of up to 150 MHz.

Pico 2 offers 520 kbytes of on-chip SRAM and 4 Mbytes of onboard flash. A second-generation programmable I/O (PIO) subsystem provides 12 PIO state machines for flexible, CPU-free interfacing.

The security architecture of the Pico 2 is built around Arm TrustZone for Cortex-M and includes signed boot support, 8 kbytes of on-chip antifuse OTP memory, SHA-256 acceleration, and a true random number generator. Global bus filtering is based on Arm or RISC-V security/privilege levels.

Preorders of the Pico 2 are being accepted now through Raspberry Pi’s approved resellers. Even though Pico 2 does not offer Wi-Fi or Bluetooth connectivity, Raspberry Pi expects to ship a wireless-enabled version before the end of the year.

Pico 2 product page

Raspberry Pi

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Pre-Configured CryptoAuthentication ICs help reduce development time and minimize design costs

Secure key provisioning is vital to protect sensitive keys against third-party tampering and malicious attacks. For securing consumer, industrial, data center and medical applications, secure key storage is essential but the process to develop and document secure key provisioning can be complex and costly. To lower the barrier of entry into secure key provisioning and enable more rapid prototyping, Microchip Technology has added the ECC204, SHA104 and SHA105 CryptoAuthentication ICs to its TrustFLEX portfolio of devices, services and tools.

ECC20x and SHA10x ICs are hardware-based, secure storage devices that are designed to keep secret keys hidden from unauthorized attacks. As part of the TrustFLEX platform, ECC204, SHA104 and SHA105 ICs are preconfigured with defined use cases, customizable cryptographic keys and code examples to streamline the development process.

“Adding the ECC20x and SHA10x pre-configured devices to our TrustFLEX platform will facilitate leveraging Microchip’s secure provisioning services for a broader set of applications,” Nuri Dagdeviren, corporate vice president of Microchip’s secure computing group. “With this platform expansion, Microchip is continuing to strengthen its portfolio, making security authentication ICs more accessible and more specifically optimized for high-volume, cost-sensitive applications.”

ECC20x and SHA10x devices meet Common Criteria Joint Interpretation Library (JIL) High rated secure key storage requirements and have been certified by the NIST Entropy Source Validation (ESV) and Cryptographic Algorithm Validation Program (CAVP) in compliance with the Federal Information Processing Standard (FIPS). The secure IC families are designed to implement trusted authentication to maintain the confidentiality, integrity and authenticity of data and communications in a wide range of systems and applications.

Microchip’s CryptoAuthentication ICs are small, low-power devices that are designed to be compatible with any microprocessors (MPUs) or microcontrollers (MCUs). They provide flexible solutions for securing industrial, medical devices, battery-powered equipment and disposable applications. Additionally, the ECC204 is a Wireless Power Consortium (WPC) approved Qi authentication Secure Storage Subsystem (SSS). Visit the Microchip website to learn more about the  Trust Platform and its portfolio of security solutions.

Development Tools

ECC20x and SHA10x ICs are supported by Microchip’s Trust Platform Design Suite, which provides code examples and learning materials and enables the secure transfer of credentials to more easily leverage Microchip’s secure key provisioning services. The devices are also supported by the MPLAB® X Integrated Development Environment (IDE), product-specific evaluation boards and CryptoAuthLib library support.

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Key Features Include Larger Sensitive Area of 6.0 mm², Increased Reverse Light Current, and Small Form Factor of 4.8 mm by 2.5 mm by 0.5 mm

Vishay Intertechnology, Inc. has released a new silicon PIN photodiode that brings a higher level of sensitivity in the visible / near infrared wavelength to biomedical applications such as heart rate and blood oxygen monitoring. The new VEMD8082 features increased reverse light current, decreased diode capacitance, and faster rise and fall times compared to previous-generation solutions. Additionally, its small form factor of 4.8 mm by 2.5 mm by 0.5 mm makes it suitable for integration into low profile devices such as smart watches.

The high sensitivity provided by the VEMD8082 is particularly important in biomedical applications such as photoplethysmography (PPG), where the photodiode is used to detect changes in blood volume and flow by measuring the amount of light absorbed or reflected by blood vessels. In such applications, precise measurements are crucial for diagnosing and monitoring conditions such as cardiovascular disease.

Specifications for the new device contributing to its high sensitivity compared to previous-generation devices include a radiant sensitive area of 6.0 mm² and an increase in reverse light current of 18 % to 20 %, depending on wavelength. Decreased diode capacitance from 50 pF to 46 pF, as well as faster rise times of 40 ns vs. 110 ns, allow for higher sampling rates.

Samples and production quantities of the VEMD8082 are available now.

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As noted by Kleiner Perkins partner Mamoon Hamid, the migration to RISC-V is in full flight. Kleiner Perkins, along with Fidelity and Mayfield, is a backer of RISC-V upstart Akeana, which has officially launched itself after exiting the stealth mode.

Akeana marked this occasion by unveiling RISC-V IPs for microcontrollers, Android clusters, artificial intelligence (AI) vector cores and subsystems, and compute clusters for networking and data centers. Its 100 Series configurable processors come with 32-bit RISC-V cores and support applications spanning from MCUs to edge gateways.

Akeana’s 1000 Series processor line includes 64-bit RISC-V cores and an MMU to support rich operating systems as well as in-order or out-of-order pipelines, multi-threading, vector extension, hypervisor extension and other extensions that are part of recent and upcoming RISC-V profiles.

Next, its 5000 Series features 64-bit RISC-V cores optimized for demanding applications in data centers and cloud infrastructure. These processors are compatible with the Akeana 1000 Series but offer much higher single-thread performance.

Three RISC-V processors come alongside an SoC IP suite. Source: Akeana

Akeana feels especially confident in data center processors while having acquired the same team that designed Marvell’s ThunderX2 server chips. “Our team has a proven track record of designing world-class server chips, and we are now applying that expertise to the broader semiconductor market as we formally go to market,” said Rabin Sugumar, Akeana CEO.

Besides RISC-V processors, Akeana offers a collection of IP blocks needed to create processor system-on-chips (SoCs). That includes coherent cluster cache, I/O MMU, and interrupt controller IPs. The company also provides scalable mesh and coherence hub IP compatible with AMBA CHI to build large coherent compute subsystems for data centers and other use cases.

Akeana, another RISC-V startup challenging the semiconductor industry status quo, has been officially launched three years after its foundation. And it has raised over $100 million from A-list investors like Kleiner Perkins, Mayfield, and Fidelity.

Related Content

• Navigating the RISC-V Revolution in Europe
• Amidst export restrictions, RISC-V continues to advance
• Accelerating RISC-V development with network-on-chip IP
• RISC-V venture in Germany to accelerate design ecosystem
• RISC-V as you like it: the ‘first’ fully configurable 64-bit processor core

The post RISC-V migration to mainstream one startup at a time appeared first on EDN.

The Topaz FPGA line builds on the company’s Titanium FPGA portfolio with high-performance, cost-effective chips for mainstream applications.