Новини світу мікро- та наноелектроніки

Solutions, a global technology manufacturer of hardware and software. Key drivers of the global investments in AI infrastructure and AI server applications are currently the high demand for highly complex server boards, which is leading to an increased need for SMT solutions for technologically sophisticated manufacturing processes.

New order bookings in the first quarter were more than double last year’s amount. Business in Asia showed particularly strong growth. The company also saw a noticeable increase in demand for SIPLACE placement solutions in the Americas and in Europe. In light of these welcome developments, ASMPT SMT Solutions expects its business to keep growing strongly for the rest of fiscal 2026.

“The dynamic growth surrounding AI server applications has exceeded our already high expectations,” explains Josef Ernst, CEO of ASMPT SMT Solutions.

Especially when it comes to the assembly of highly complex server boards, the demands on precision, process stability, and productivity are rising dramatically. It is precisely in these applications that our solutions are currently demonstrating their strengths worldwide.

AI servers are placing new demands on electronics manufacturing.

Placement solutions for modern AI server boards must be capable of handling both heavy, large-format, high-performance BGAs and thousands of highly miniaturized components from 016008M size with great reliability, precision, and productivity.

The combination of ever-larger printed circuit boards, rising component complexity, and the highest demands on accuracy and process stability presents new challenges for SMT manufacturing. Consequently, there is a need for placement solutions that intelligently combine high speed, maximum precision, and stable processes. In this context, the interplay between integrated hardware and software, as well as global service, is becoming increasingly important.

“Today, our customers no longer evaluate individual machines alone, but rather the performance of complete solution environments,” says Josef Ernst. “Global presence, local support, and the close integration of hardware, software, and service are becoming increasingly important.”

Focus on the supply chain and delivery capability

At the same time, high demand is creating new challenges for global supply chains. Geopolitical uncertainties, rising logistics costs, and the highly dynamic market are increasing pressure on supply chains, manufacturing, and service organizations. ASMPT SMT Solutions is therefore making targeted investments in expanding global delivery and service capacities to reliably support customers worldwide.

“In market phases like these, it quickly becomes clear just how resilient a manufacturer really is,” explains Josef Ernst. “Our customers rely on us to deliver and provide first-class service worldwide. That is exactly where our focus lies right now.”

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Nanoelectronics research center imec of Leuven, Belgium is evolving its 300mm RF silicon interposer into a system-level platform for the heterogeneous integration of III–V chiplets on Si-CMOS. By uniquely combining high-density embedded capacitors, a scalable modeling framework for passive components and laser-assisted bonding for III–V chiplet assembly, the platform lays the foundation for next-generation wireless (mmWave and sub-THz) systems, as well as RF-grade signal handling for ultrafast data-center applications...

Learning from and adapting the lessons of the past is wise, as long as it’s not taken to overly constraining excess. So, too, is adopting others’ ideas (in a non-patent-infringing way, of course).

As you already know if you read last week’s blog post (and if not, please do so first before continuing with today’s…I’ll be right here, waiting for your return…), I initially planned on covering this topic in a single writeup. It ended up, however, being at least twice as long as I’d originally envisioned, so I basically chopped it in two. Part 1 covered the historical precedents that led to the ongoing memory card innovations of more modern times, which I’ll discuss this time.

Interface evolutions

I’m spending all this time on past-history factoids and trends because, as you’ll soon see, they conceptually continue(d) to repeat themselves multiple times over with the passage of time. To that point, one other historical example, involving performance, also bears mention. PCMCIA, introduced in 1990, tackled a mid-life enhancement five years later, from the 16-bit ISA bus-derived PC Card to the PCI bus-based and 32-bit, but still backwards-compatible, CardBus.

A more radical transformation, ExpressCard (originally called NEWCARD), followed roughly a decade after that. Based on the combination of PCI Express and USB 2.0, it was not directly backwards compatible with CardBus, far from with PC Card, thereby either forcing systems adopters to include slots for both standards in designs or forcing users to use clumsy adapters:

More generally, as my attempted blending of two Wikipedia entry excerpts notes:

Despite being much faster in speed/bandwidth, ExpressCard was not as popular as PC Card, due in part to the ubiquity of USB ports on modern computers. When the PC Card was introduced, the only other way to connect peripherals to a laptop computer was via RS-232 and parallel ports of limited performance, so it was widely adopted for many peripherals. More recently, virtually all equipment has Hi-Speed USB ports, and most types of peripherals which formerly used a PC Card connection are available for USB (and have the advantage of being compatible with desktop computers as well as portable devices) or are built-in, making the ExpressCard less necessary than the PC Card was in its day.

Wash, rinse, repeat

Let’s now fast-forward to more modern times. CFast, short for CompactFast, which I mentioned in both of my 2023 writeups (in the context of their use by my Blackmagic cameras), is based on CompactFlash (and is also managed by the CFA) but migrates from ATA to SATA. CFast 1.x dates from 2009 and is based on SATA 2.0; the backwards-compatible CFast 2.0 upgrades to SATA 3.0 but has seen limited-at-best industry uptake since being initially unveiled in 2012.

Why? Enter, for example, the alternative CFexpress, also managed by the CFA, which switches from SATA to the solid-state media-optimized NVM Express (i.e., NVMe) as its command set and to PCI Express (PCIe) as its hardware interface foundation (as I’d mentioned at the end of 2023), as well as coming in multiple dimensional options. The smaller Type A (at left in the following image) and larger Type B (right) card variants are today commonplace in the industry, with the even larger Type C conversely not yet in production to the best of my knowledge:

In this context, an overview of the earlier XQD standard also bears mention. XQD, once again now managed by the CFA (albeit initially announced solely by Sandisk, Sony and Nikon), dates from 2010. It’s dimensionally and connector-compatible with CFexpress Type B and is also based on PCIe, albeit only in a single-lane implementation (with PCIe 3.0 support added with XQD 2.0 in mid-2012). The XQD and CFExpress standards are therefore cross-compatible, although only to a degree, generally requiring firmware updates which not all camera, memory card reader and other system manufacturers have provided.

CFexpress 1.0, announced by the CFA in September 2016 as the successor to XQD, launched with support for PCIe 3.0, albeit this time in higher-bandwidth dual-lane form (for the size option now known as Type B and used by my high-end Canon and Panasonic cameras, among others). CFExpress 2.0, following in February 2019, added the single-lane PCIe Type A and quad-lane Type C options, along with upgrading the NVMe command set from 1.2 to 1.3. And the latest iteration, August 2023’s CFexpress 4.0, upgrades the supported PCIe interface to 4.0 (again, at up to four lanes with Type C), and the NVMe command set to 1.4. CFExpress 4.0-optimized systems are not yet in the market, to the best of my knowledge, but cards (such as this OWC Atlas Pro) are prevalent and backwards-compatible with existing cameras and such:

No, I don’t know what happened to CFexpress version 3.0, either. While buying a CFexpress 4.0 card now will leave potential performance “on the table” with CFexpress 2.0-only systems, it does provide obsolescence protection for subsequent camera-or-other upgrades you might make in the future. And conversely, if future-proofing isn’t a concern, you’ll be able to (as I’ve personally done) get some great deals on CFexpress 2.0 memory cards right now, despite overall semiconductor memory supply constraints, as manufactures strive to “fire sale” deplete their inventories of legacy product variants.

Don’t count out Donkey Kong

And what about the SD and related microSD card standards; are they in danger of falling by the wayside as these high-performance newcomers ramp into the market? Not if the SD Association has anything to say about it, specifically with next-generation “Express” offerings. See if you notice anything familiar trend-wise in the paragraphs that follow:

When the SD Association (SDA) first announced SD Express in June 2018, it set the bar high and opened a world of possibilities for manufacturers to integrate supercharged removable storage into their designs. SD Express is capable of delivering SSD performance levels of up to 4GB/sec. This makes it perfect for use in high-performance electronic devices and products. With the introduction of advanced security features in May 2022 found in the SD specification version 9, performance and versatility merge to create an innovative, and advanced powerhouse solution for SD memory cards.

SD Express leverages the PCI Express and NVMe interfaces and uses the well-known SD memory card form factor for compatibility with existing SD slot architectures. The SDA also introduced a microSD Express memory card format that is backward compatible with devices. SD Express is not just about SD memory cards getting faster, it is also about SD memory cards doing more.

After languishing for several years awaiting market demand that stubbornly refused to emerge, “Express” variants’ fortunes are finally looking up. Specifically, the microSD Express card is used in the Nintendo Switch 2 game console, notably (and singlehandedly) increasing the likelihood of a high-volume long-term future for the standard.

Blazing a trail

I’ll wrap up this writeup with coverage of a recently emergent sole-source memory card option (in spite of my earlier comment that I planned to avoid diving into past-history proprietary offerings) that I’d earlier caught mention of at The Verge and elsewhere. It’s Biwin’s Mini SSD:

Biwin is, if you hadn’t already guessed from the coin at left in this “stock” image, a China-based memory subsystem manufacturer (to the right of the 1-yuan coin is the rare U.S. $1 coin). Most of the products on the company’s website are industry standards-based: PCIe NVMe internal SSDs, for example, along with USB flash sticks and drives, DRAM DIMMs and SoDIMMs, SD/microSD and CFexpress memory cards (an image of which you saw earlier), and memory card readers. But with the Mini SSD, the company has apparently decided to try its hand at also going proprietary.

Interestingly, the Mini SSD is slightly larger (at 15x17x1.4 mm) than the microSD Express (15x11x1 mm) counterpart. And at least from a latest-generation ratified-spec standpoint, it’s seemingly no faster than microSD Express, either; both are based on dual-lane PCIe 4.0 and NVMe (once again: sound familiar?). The key differentiator that Biwin seems to be betting on is timing; as Ars Technica notes, currently available microSD Express cards “top out around 900MB per second, roughly the amount of bandwidth available from a single PCI Express 3.0 lane.”

Conversely, Biwin was demonstrating functional products at CES in January, claiming read speeds up to 3,700 MB/s and write speeds up to 3,400 MB/s (at least in combination with the company’s own card reader peripheral), and with capacities ranging from 512 GB to 2 TB. Biwin also touts Mini SSD’s IP68-rated dust- and water-proof chops. One note: while the company was referring to them as the “BL100” series late last summer, it’s now calling them “CL100”. Why?

Will Biwin be able to gain a defendable beachhead (and then expand its addressable customer “footprint”) before SD Association members release similar-performance microSD Express products into the market? Let me know your thoughts on that question, or anything else I’ve discussed in this series, in the comments!

—Brian Dipert is the associate editor, as well as a contributing editor, at EDN.

Related Content

• Memory card interfaces keep pace with the internal bus evolution race: Part 1
• Memory cards: Specifications and (more) deceptions
• SD card speeds: question your assumptions
• Prosumer and professional cameras: High quality video, but a connectivity vulnerability
• 2024: A technology forecast for the year ahead

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Yesterday I started up an old Soviet gas discharge rectifier ВГ-176. submitted by /u/289_257 [link] [comments]

As India accelerates its transition to electric mobility, the focus is shifting from adoption to scale, efficiency, and affordability. Bosch is set to support this next phase by introducing its latest third-generation Silicon Carbide (SiC) semiconductors in India. Designed to improve the performance and efficiency of electric vehicles, the new chips will also contribute to the development of a stronger local mobility ecosystem.

Silicon carbide (SiC) semiconductors are central to improving the efficiency of electric vehicles. They control the flow of energy within the power electronics system – particularly in the inverter and ensure that energy from the battery to the electric motor is converted as efficiently as possible. With this new generation, Bosch is delivering approx 20% higher performance, supporting India’s rapidly growing EV market. For the end-user, this means longer driving ranges without larger batteries, improved battery utilization, and ultimately, a lower total cost of ownership.

“Our advanced SiC technology is designed to deliver the tangible benefits that Indian consumers demand – longer driving range, faster charging, and lower long-term costs,” said Sandeep Nelamangala, Joint Managing Director, Bosch Limited, and President, Bosch Mobility India. “By making high-efficiency power electronics more accessible, we are helping to unlock the full potential of the EV market, making clean, efficient mobility a reality for everyone in India.”

With over 60 million SiC chips already delivered worldwide, Bosch brings proven power semiconductor expertise to support the next phase of India’s electrification journey. The company continues to invest billions of euros in expanding its global semiconductor capabilities, creating a strong foundation for innovation, supply resilience, and future growth. As India advances its ambitions in electric mobility, localization, and advanced manufacturing, Bosch aims to support customers and ecosystem partners by bringing together global semiconductor expertise and local ecosystem development.

With its third-generation SiC chips, Bosch is taking this technology to the next level. “Our ambition is clear: we want to be a globally leading manufacturer of SiC chips,” said Markus Heyn, member of the Bosch board of Management and chairman of the Bosch Mobility business sector. “With our next-generation SiC chips, we are helping our customers put even more powerful and efficient electric vehicles onto the road.”

Bosch’s Gen 3 SiC technology enables more compact and efficient power electronics designs by reducing energy losses, improving thermal performance, and lowering system complexity and cooling requirements. Miniaturization is a key enabler for long-term cost efficiency, as it allows more chips to be produced per wafer. In this way, Bosch is contributing to making high-performance electronics more widely accessible.

The advantage makes advanced power electronics relevant not only for premium vehicles but also for mass-market EV segments, where efficiency, affordability, and reliability are critical due to the optimal combination. Bosch is bringing advanced semiconductor innovation closer to the needs of India’s evolving mobility landscape and supporting the next phase of efficient, scalable, and sustainable electric mobility in the country.

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Vishay Intertechnology, Inc. announces an expansion of its ILHB series of Automotive Grade multilayer chip ferrite beads for high current filtering. The Vishay Dale devices now offer higher current capability, smaller case sizes, and a wider range of impedance values to meet a broader set of EMC noise reduction requirements.

The ILHB series is now available in 0402, 0603, 0805, 1008, and 1206 case sizes with current handling up to 6 A and impedance values from 10 Ω to 2700 Ω. The expanded lineup allows designers to achieve higher current handling in smaller packages, while delivering two to three times the current capability for the same package size and impedance value.

The immense range of sizes, current handling, and impedance values allows the ILHB ferrite beads to be used in a wider array of EMC noise reduction applications. These include high current, high frequency, and signal-specific filtering in automotive energy distribution and management systems; industrial automation systems; home and building controls; computers and computer peripherals; consumer devices; white goods; medical instrumentation; avionics; and telecom infrastructure.

The ILHB product datasheets optimize with additional design parameters that help engineers estimate bead performance across more frequencies without consulting multiple performance graphs to simplify device selection. These parameters include impedance peak value and frequency, the frequency at which impedance drops below the nominal value, and the X- and R-frequency crossover point.

The AEC-Q200 qualified devices feature a silver (Ag) inner conductor with copper (Cu), nickel (Ni), and tin (Sn) plating. The ferrite beads operate over a temperature range from -55 °C to +125 °C and are RoHS-compliant, halogen-free, and Vishay Green.

Device Specification Table:

Part number	IHLB-0402	IHLB-0603	IHLB-0805	IHLB-1008	IHLB-1206
Case size	0402	0603	0805	1008	1206
Dimensions (mm)	1.0 x 0.5 x 0.5	1.6 x 0.8 x 0.8	2.0 x 1.2 x 0.85	2.5 x 2.0	3.2 x 1.6
Z at 100 MHz (W)	10 to 1800	22 to 2500	17 to 2700	300 to 600	19 to 1000
DCR max. (mW)	18 to 2400	7 to 1800	10 to 800	30	10 to 300
Rated DC current at 85 °C (1) (A)	0.05 to 3.1	0.05 to 6	0.2 to 6	4	0.5 to 6
Zpk (2) (W)	19 to 3738	28 to 2526	21.6 to 31 868	554 to 670	32.68 to 1167
F at Zpk (3) (MHz)	97 to 1329	78 to 1000	72 to 1132	122 to 155	61 to 2921
Z typ. at 100 MHz (W)	10 to 2038	22 to 2200	17 to 2713	309 to 517	17.2 to 1000
F at ZDO (4) (MHz)	125 to > 10 000	100 to 8000	84 to 8000	138 to 222	100 to > 10 000
XL / XR x over (5) (MHz)	31 to 710	26 to 439	23 to 298	100 to 117	25 to 120

 

• Rated current is the DC that causes a 40 °C temperature rise at 20 °C ambient
• Zpk = peak of impedance curve
• F at Zpk = frequency of Zpk
• F at ZDO = frequency above 100 MHz where Z drops to nominal Z
• XL / XR x over = crossover point for inductive reactance and resistance impedance

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Qorvo introduces an X-band radar front-end solution that enables defense system designers to achieve higher performance without increasing size, weight, or prime power. The design targets modern phase array and multifunction sensors. The solution combines transmit power, efficiency, and receive sensitivity in a single compact module, addressing key challenges in next-generation radar design.

 

The Qorvo QPF5012 is a fully integrated X-band transmit/receive front-end module operating from 8.5 to 10.5 GHz, delivering 10W of transmit power.  With 42 percent power-added efficiency and 2.1 dB noise figure in a 7 x 5 mm package, the QPF5012 enables designers to extend radar range, reduce thermal load, and improve detection sensitivity without increasing system complexity. 

“Radar designers have historically been forced to trade off output power, prime power, or sensitivity,” said Doug Bostrom, general manager of Qorvo’s Defense and Aerospace business. “With the QPF5012, Qorvo brings all three together in a compact integrated front-end module, helping customers simplify design, reduce thermal constraints, and improve real-world radar performance.”

 

QPF5012 is specifically built for X-band phased array radar applications where size, weight, and power (SWaP) and thermal performance are critical. Its high level of integration reduces component count and simplifies system design while maintaining constant efficiency and RF output power across changing antenna loads. This enables AESA systems to deliver more consistent RF performance across varying scan angles. Qorvo enables this integration through vertically integrated RF design expertise, advanced multi-technology packaging, and trusted manufacturing capabilities.

Key Features of QPF5012:  

• 10W saturated transmit power across 8.5 to 10.5 GHz  
• 42% power-added efficiency to reduce prime power consumption and thermal load  
• 2.1 dB noise figure to improve receive sensitivity and detection accuracy  
• Integrated T/R functionality in a compact 7 x 5 mm module to reduce SWaP and design complexity. 

 

By delivering power, efficiency, and sensitivity together in a single integrated module, Qorvo enables defense radar designers to overcome traditional design constraints and achieve higher system-level performance in a compact front-end architecture.

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US-based aerospace & defense technology company Northrop Grumman Corp has fabricated a new gallium nitride (GaN) chip that sets what is claimed to be a new performance standard for military and commercial use...

There’s considerable interest in leveraging the bandwidth and other potential virtues of terahertz waves that occupy the spectrum between the conventional RF and optical worlds, generally considered to span 100 GHz (3 mm wavelength) to 10 THz (30 μm). However, managing electromagnetic energy at these wavelengths presents many challenges, as they are too short for most electronics, yet too long for all-optical components.

Nonetheless, there’s a significant amount of ongoing research in developing the materials and components needed, especially with many potential applications, including the emerging 6G standards being developed now.

At these frequencies and corresponding wavelengths, signal energy must be conveyed via waveguides—discrete wires won’t do, of course. But making the needed waveguide physical transitions is difficult when they are fabricated in silicon as part of a larger set of on-chip functions.

Addressing this issue, a team of researchers at The Skolkovo Institute of Science and Technology—or Skoltech, a private institute in Moscow—working with a team from KTH Royal Institute of Technology in Sweden, has developed a key technology that could support silicon-based terahertz waveguides and their on-chip transitions.

Their solution is based on carbon nanotubes, one of those amazing materials that keeps offering solutions to diverse problems. The single-wall carbon nanotube (SWCNT) was discovered in 1991 (see “A Brief Introduction of Carbon Nanotubes: History, Synthesis, and Properties“). Like fullerene and graphene, SWCNTs are one of the allotropes of carbon.

Allotropes present a different structural form of the same chemical element within the same physical state; because their atoms are bonded differently, allotropes have vastly different physical and chemical properties from each other—think diamond versus graphite.

A key challenge in building these complex terahertz arrangements is devising properly matched terminations. Without proper termination, reflections at device discontinuities can cascade, thus degrading performance and altering the intended operational profile. In addition, these terminations are necessary for characterization of multi-port devices such as directional couplers, where the unused ports must be terminated with matched loads.

The conventional solution is to use adiabatic or impedance-matched tapering of the waveguide cross-section to free space, gradually expanding the guided mode to induce radiation losses while operating as a dielectric rod antenna. However, the efficiency of these structures depends on the length of the tapering, therefore consuming valuable chip area; it can also radiate power in undesirable directions, thus complicating packaging, limiting integration density, and creating electromagnetic pollution.

Note that in the adiabatic-coupling approach, the optical mode is coupled from one waveguide to another by a slow change of a waveguide parameter (width, thickness, or both) such that the optical mode remains in the fundamental mode and does not couple to unwanted higher-order modes. As a result, the tapered waveguides need to be long enough to meet the requirements of the adiabatic conditions of slow change of waveguide parameter. However, at the same time, they need to meet the device compactness requirement. Therefore, there is a trade-off to be made

The research team devised and tested a carbon nanotube-based coating that blocks electromagnetic radiation, thereby creating waveguides compatible with terahertz wavelengths. The ultrathin single-walled carbon nanotube films that they synthesized are similar to those that they used previously to create small-scale components, such as lenses and antennas, but with a big difference, as this time it’s not for standalone components. Instead, they leveraged carbon-based material to control electromagnetic radiation in 2D-integrated optical circuits, eliminate interference, and enable additional functionality.

They demonstrated a compact, broadband termination by coating silicon dielectric rod waveguides (DRW) with ultrathin single-walled carbon nanotube films. Fabricated via a floating-catalyst (aerosol) chemical vapor-deposition process, the film thickness varies from 2 to 53 nm and was characterized in the 140-220 GHz range. A 53-nm thick film introduced up to 47 dB of attenuation while maintaining over 20 dB reflection loss, confirming nearly reflection-free absorption (Figure 1).

Figure 1 Reflection measurements of the SWCNT-loaded DRWs show ∣S11∣ for the 6-mm long samples (a) and ∣S11∣ for the 12-mm long samples (b). The light grey line is baseline reflection after calibration by measuring a thru-standard (flanges of the frequency extenders connected); dark grey is the reflection coefficient of an unloaded DRW. Source: Nature Communications

Shielding analysis shows absorption dominates over reflection, and they achieved a record specific shielding efficiency of 5.5 × 109 dB cm2/g (Figure 2).

Figure 2 Shielding efficiency components for the SWCNT-coated dielectric waveguides: reflection component SER (a, b), absorption component SEA. (c, d), and total shielding SET (e, f) for 6-mm (left column) and 12-mm (right column) samples over 140-220 GHz, with light grey as the equivalent shielding efficiency of an unloaded silicon waveguide provided for reference. Source: Nature Communications

This approach offers a footprint-efficient solution for high-density terahertz circuits without bulky, radiative terminations. The work is presented in their paper “Ultrathin Single-Walled Carbon Nanotube Surface Wave Absorbers for Terahertz Dielectric Waveguides” published in Nature Communications. It’s unfortunate that the paper does not have any microphotographs of the SWCNT waveguide and transitions in silicon, so you’ll just have to visualize those yourself.

Have you had any interaction with or uses for carbon nanotubes? If so, in what way? Do you see a role for them in any of your projects, whether terahertz or other?

Bill Schweber is a degreed senior EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features. Prior to becoming an author and editor, he spent his entire hands-on career on the analog side by working on power supplies, sensors, signal conditioning, and wired and wireless communication links. His work experience includes many years at Analog Devices in applications and marketing.

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• Carbon nanotubes boost image sensor sensitivity
• Metadevices may fill the terahertz component gap
• Optical combs yield extreme-accuracy gigahertz RF oscillator

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Fixed a couple of old broken carriage clock recently with some STM32s, e-displays & some bling. Setup: * Microcontroller - NUCLEO_L432KC * Display - Waveshare 2.9" & 3.7" E-Paper Displays * Sensor - DHT Temperature & Humidity Sensor with 100k pull-up resistor between the 3.3V rail and the DATA/OUT line. * Power - Voltage Regulator HT7333 and Micro USB 18650 Lithium Battery Charger Module * Bling - Some pencil art with gold surround, gold run on transfers & corner protector gold filigree submitted by /u/spamonster [link] [comments]

The ASM330LHHG1 automotive qualifies as an Inertial Measurement Unit (IMU), which operates from -40°C to 125°C, mounts in vehicle zones, including those where the ambient temperature may be a concern. Combining low-noise sensors, temperature compensation, and a 6-channel synchronize output, the IMU fulfils the industry’s need for greater dead-reckoning accuracy to support navigation and positioning.

Today’s cars, vans, and trucks, as well as industrial and agricultural vehicles, can leverage increasingly accurate GNSS positioning technologies for applications such as routing, tracking, navigation, and driver assistance. These new and latest systems need high-quality dead reckoning to maintain continuity between satellite updates and provide effective fallback during GNSS outages or corruption, ensuring superior performance and greater resilience.

ST’s ASM330LHHG1 meets this need by delivering 3-axis accelerometer and 3-axis gyroscope data through its synchronized output that ensures consistent signal timing for dead-reckoning calculations, motion-data correlation, and GNSS fusion. Both sensors leverage the latest MEMS processes for low noise and benefit from built-in temperature compensation for enhanced stability.

The IMU provides accurate data for other non-safety applications throughout the vehicle, with an accelerometer full-scale range of ±16g and an extended gyroscope range covering ±125dps to ±4000dps with minimal bias drift. These include vehicle-to-everything (V2X) systems, telematics, eTolling, anti-theft, impact detection, crash reconstruction, driving comfort, vibration monitoring and compensation, and general motion-activated functions.

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Altera is now sampling its Agilex 9 Direct RF AGRW039 wideband SoC FPGA for aerospace, defense, and communication systems. According to Altera, the device delivers a 40% increase in compute capability per square millimeter. It also provides 45% greater logic and DSP density than the previous generation and supports DDR5 and LPDDR5 memory technologies.

With integrated 64-Gsample/s wideband RF and increased compute and memory resources, the programmable device eliminates the need for multichip designs and enables advanced beamforming, radar, and data cube processing. The AGRW039 provides high-bandwidth signal capture and generation, allowing customers to scale performance while maintaining design flexibility.

Agilex 9 Direct RF SoC FPGAs combine high-speed data converters, programmable logic, and processing elements in a single package. The integrated architecture helps reduce system complexity and power consumption for wideband RF applications that require real-time performance.

Production silicon and development kits for the Agilex 9 Direct RF AGRW039 are expected to be available in Q3 2026.

Agilex 9 Direct RF series

Altera

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Navitas has developed a TO-247 package offering more than 6000 V of isolation for its 1200-V, 2300-V, and 3300-V SiC MOSFETs. Designated the UHV-TO-247-4-ISO, the through-hole package supports direct-cooled thermal management through a reflow-compatible isolated thermal pad. It also provides over 12 mm of pin-to-pin creepage, enabling module-level performance in a compact discrete form factor.

Compared to standard non-isolated through-hole packages, the UHV-TO-247-4-ISO reduces the need for external high-voltage isolation while improving thermal and EMI performance. These benefits extend to high-voltage grid-tied power conversion systems, solid-state transformers, battery energy storage systems, and renewable energy applications.

The UHV-TO-247-4-ISO delivers integrated high-voltage isolation using an AlN substrate, reducing die-to-heatsink capacitance and helping lower common-mode noise and radiated EMI. Its reflow-compatible, direct-cooled thermal interface enables direct mounting to liquid- or air-cooled heatsinks, improving thermal performance while eliminating the need for external TIM and isolation materials. The package also enhances thermal cycling and power cycling lifetime through its AlN/AMB construction and robust heatsink interface.

To request samples or additional product information, please contact a Navitas sales representative or email info@navitassemi.com.

Navitas Semiconductor 

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Deposition equipment maker Aixtron SE of Herzogenrath, near Aachen, Germany has announced a strategic production partnership with ROHM Semiconductor, which has selected Aixtron’s G10-GaN metal-organic chemical vapor deposition (MOCVD) system to establish in-house gallium nitride (GaN) epitaxy at its Hamamatsu plant in Japan. The system is currently ramping for volume production of 8-inch GaN epitaxial wafers for 650V and 100V power device platforms...

Efficient Power Conversion Corp (EPC) of El Segundo, CA, USA — which makes enhancement-mode gallium nitride on silicon (eGaN) power field-effect transistors (FETs) and integrated circuits for power management applications — has introduced the EPC91132, a compact 3-phase BLDC motor drive inverter reference design based on the EPC33110 GaN three-phase module...

Efficient Power Conversion Corp (EPC) of El Segundo, CA, USA — which makes enhancement-mode gallium nitride on silicon (eGaN) power field-effect transistors (FETs) and integrated circuits for power management applications — says that its new EPC2378 25V eGaN power transistor has entered mass production, enabling high-density power system designers to achieve higher efficiency, faster switching and greater power density in demanding DC–DC conversion applications. EPC2378 is optimized for synchronous rectifier applications on the secondary side of a 48V-8 or 5V LLC converter. In addition to what is claimed to be the best-in-class 410µΩ typical RDS(on), the devices have an industry-leading low RDS(on) x QG figure of merit that enables higher-frequency and higher-efficiency operation. These capabilities are of particular value in fast-growth markets such as AI infrastructure, data centers, telecom, industrial systems and advanced computing platforms...

Lotus Microsystems’ vStrata vertical power delivery platform targets the electrical, thermal, and mechanical challenges of AI infrastructure. The first module in the vStrata Power Series, the LS0580, is a fully integrated power-system-in-package (PSiP) that places power conversion closer to the load to reduce distribution losses and board complexity. The device has completed tape-out for leading CPU, GPU, and AI accelerator platforms, with engineering samples shipping in Q3 2026.

Built on a silicon-based substrate, vStrata combines power delivery, thermal management, and packaging in a single architecture. Designed for kiloampere-class AI workloads, the platform delivers up to 96% point-of-load efficiency while reducing power losses and thermal constraints. Its low-profile vertical architecture is enabled by silicon PIT technology, supporting ultra-thin designs below 1 mm by placing power directly beneath the processor to shorten electrical paths and improve transient response.

The vStrata platform is compatible with existing power management controllers and reference designs. Lotus is currently evaluating the platform with hyperscale customers and additional partners through an early access program.

vStrata product page

Lotus Microsystems 

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The Melexis MLX92344 is a 2-wire, 2-bit Hall-effect switch for contactless detection of up to four positions in automotive body electronics. Unlike conventional microswitch-based approaches that often require multiple mechanical switches to detect intermediate positions, the MLX92344 simplifies system design by providing programmable current levels and magnetic thresholds. It is suited for applications such as seat track positioning, soft-closing doors, and multilevel trunk locks.

A dual programmable architecture lets designers assign output current levels directly to the device’s magnetic operating and release thresholds, with temperature compensation for both neodymium and ferrite magnets. Up to four different current levels can be configured between 3 mA and 28 mA, enabling the MLX92344 to emulate standard microswitch interfaces while maintaining compatibility with existing hardware and ECUs. The device can be sensed through standard I/O triggers or an ADC, requiring only software readout adjustments.

The MLX92344 offers a wide magnetic operating range from 0.5 mT to 200 mT. It is ASIL B SEooC compliant, AEC-Q100 qualified, and operates from 2.7 V to 28 V over a temperature range of -40°C to +150°C. The switch is available in both surface-mount and through-hole packages.

MLX92344 product page 

Melexis

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NVIDIA has unveiled the RTX Spark, a “superchip” delivering up to 1 petaflop of AI compute to enable Windows PCs to run personal AI agents. The device combines 128 GB of unified memory with an NVIDIA Blackwell RTX GPU featuring 6,144 CUDA cores and fifth-generation Tensor Cores that provide FP4 precision. The GPU connects to a high-performance 20-core Grace CPU via the NVLink-C2 chip-to-chip interconnect.

NVIDIA collaborated with MediaTek on the custom CPU design, contributing to strong power efficiency, performance, and connectivity. NVIDIA also partnered with Microsoft to deliver a secure Windows platform for on-device agents, incorporating new Windows security primitives and the NVIDIA OpenShell runtime to safely run autonomous AI agents.

RTX Spark brings NVIDIA’s AI and graphics technologies to creators, developers, and gamers. It can run 120-billion-parameter language models, render large 3D scenes, and accelerate 12K video editing. For gaming, the platform supports ray tracing and NVIDIA DLSS technologies for enhanced visual quality and performance.

RTX Spark-based laptops and compact desktops will be available this fall from leading manufacturers.

RTX Spark product page 

NVIDIA

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The first article in this silicon governance series established a fundamental reality: observability is not automatically governed evidence. Advanced AI silicon platforms generate a massive stream of runtime telemetry, including network-on-chip (NoC) counters, voltage diagnostics, thermal maps, memory-state logs, firmware traces, error signatures, and workload-dependent behavior. But raw observability alone lacks the context, synchronization, and causality required to explain physical system behavior.

The second article extended that thesis into runtime operation by introducing the firmware–hardware handshake. Hardware senses transient states. Firmware executes localized, bounded actions. A governance layer determines whether those runtime actions remain valid, safe, and causally justified.

This third article closes the loop.

Once complex AI accelerators, multi-die chiplets, HBM modules, advanced heterogeneous packages, and cloud-scale systems are deployed at enterprise scale, a new question appears. How does field evidence refine future silicon, package, firmware, and system decisions without creating an uncontrolled feedback loop of autonomous adaptation?

That question requires fleet learning to operate under bounded gate authority. The operating principle is simple: Fleet learning recommends and bounded gate authority approves.

Fleet learning can identify macro-scale failure signatures, detect structural drift across deployed systems, and recommend policy refinement. But fleet learning should not independently close development gates, alter firmware release criteria, rewrite operating envelopes, or approve lifecycle actions.

That final step requires bounded decision authority.

From single-chip handshake to cluster-scale drift

The firmware–hardware handshake begins locally.

A voltage droop appears on an internal rail.

• A thermal sensor reports a localized hot spot.
• A SerDes lane loses operating margin.
• A memory controller logs an error correcting code (ECC) event.
• Firmware responds through a pre-validated, bounded action envelope.

At the single-device level, this can preserve operation. But modern AI infrastructure does not operate as isolated silicon. Instead, a single accelerator becomes a board.

• A board integrates into a rack.
• A rack scales into a data-center cluster.
• A cluster becomes a globally distributed fleet.

At that scale, localized runtime compensation is no longer sufficient. Thousands of multi-die devices operating under shifting workloads begin to reveal multi-physics patterns that no isolated lab test, qualification plan, or pre-silicon simulation could fully predict.

A high-speed SerDes retraining event may appear harmless on one device. Across a fleet, it may reveal an advanced-package escape, connector-aging issue, or workload-dependent signal-integrity margin deficit.

A recurrent voltage droop may look like firmware tuning noise. Across many systems, it may correlate with one package substrate lot, one raw-material source, one board configuration, or one power delivery network (PDN) resonance condition.

A persistent thermal asymmetry may look like a local cooling issue. Across a data-center tier, it may expose thermal interface material (TIM) variation, substrate warpage, lid-attach tolerance, or airflow interaction. Next, scattered ECC events may appear random. Across workload, voltage, temperature, memory location, and package population, they may reveal a wafer-to-package interaction or localized timing drift.

The purpose of fleet learning is not to collect more telemetry; the purpose is to normalize field behavior into governed lifecycle evidence.

Telemetry is not convergence

Modern AI clusters are already saturated with logging mechanisms. They continuously capture physical, electrical, firmware, and workload states. But this raw telemetry stream is not system convergence. A monitoring dashboard can flag a symptom.

• A generic AI model can identify a statistical correlation.
• An error log can timestamp an interruption.
• A fleet database can reveal clustering.

But none of those observations automatically confirms physical causality.

A recurring signal-integrity degradation event may look like normal channel aging. In reality, the root cause could be board-level connector variation, package escape routing discontinuity, local thermal expansion, substrate variation, return-path interruption, or mechanical stress accumulation at the package-to-board interface.

A voltage instability event may look like a firmware behavior. In reality, it may originate from package inductance, PDN resonance, voltage regulator module (VRM) response, decoupling placement, silicon switching current, or thermal drift.

A thermal excursion may look like a cooling problem. In reality, it may involve workload placement, TIM thickness, lid attach, airflow, die placement, package warpage, or power-map concentration. This is why unconstrained AI analytics can be risky in high-reliability semiconductor environments.

A system that blindly changes operating bounds based on weakly governed telemetry may optimize the wrong variable, amplify false correlations, mask physical defects, or push firmware parameters outside validated design boundaries. But the objective is not more raw data; the objective is trusted, admissible evidence.

SEGA-AI response: A governed feedback architecture

Fleet learning within the SEGA-AI/governance for lifecycle stack is fundamentally different from standard cloud-level log analytics.

• It’s not generic telemetry analytics.
• It’s not unconstrained AI optimization
• It’s not self-modifying infrastructure

Fleet learning is a governed realization-feedback architecture. Its purpose is to connect deployed behavior back to the assumptions made during pre-silicon design, packaging floor-planning, post-silicon validation, qualification, manufacturing release, and firmware policy definition.

It asks: 

• Was the original design guardband correct?
• Was the package-level simulation model complete?
• Did the system EM corridor have enough high-frequency margin?
• Did the physical PDN respond as predicted under maximum dI/dt load steps?
• Did the firmware policy preserve global convergence or only local stability?
• Did one package lot behave differently from another?
• Did one board configuration or connector population age differently?
• Did field behavior expose a validation escape?

This transforms the field from a passive reliability archive into an active lifecycle evidence source. But the field does not rule the system. Instead, deployed behavior informs the governance stack, and bounded gate authority governs the decision.

Fleet learning recommends and bounded gate authority approves

The most important safety principle is that fleet Learning can recommend refinement, but bounded gate authority must approve action.

This prevents a dangerous failure mode: allowing field data, machine learning, or runtime analytics to directly modify firmware policy, release criteria, validation guardbands, or corrective-action rules without sufficient evidence authority.

In large fleets, an unsafe automated update can create systemic instability. A local firmware action that works on one device may create thermal imbalance across a rack. A voltage policy that improves one workload may reduce aging margin elsewhere. A SerDes retraining policy may preserve one link but increase synchronization overhead across a cluster.

Therefore, fleet-scale learning must pass through a multi-state decision gate. Here, bounded gate authority can issue one of six outcomes.

1. Close: The fleet evidence is mature, admissible, causally verified, and sufficient to advance the configuration.
2. Remain open: The evidence is immature, stale, incomplete, conflicting, or not yet tied to critical to quality (CTQ) parameters.
3. Reopen: Authoritative fleet evidence invalidates a previously closed validation, firmware, package, or release assumption.
4. Escalate: Uncertainty, risk severity, or cross-domain conflict exceeds the bounded authority envelope and requires human engineering review.
5. Approve bounded action: A limited mitigation is allowed inside a pre-validated safe envelope, such as narrowing a frequency range, changing a retraining threshold, adjusting a voltage policy, or applying a lot-specific firmware constraint.
6. Block release: A critical CTQ, causality path, or reliability condition remains unresolved.

This is the difference between learning from the fleet and being controlled by the fleet. Fleet learning identifies the pattern; bounded gate authority decides whether the pattern is mature enough to authorize action.

Example 1: SerDes retraining across a fleet

Consider a high-speed SerDes interface operating across thousands of deployed systems. A single lane retraining event may not be alarming. It may result from temperature, workload burst, supply noise, aging, or normal link management. But if fleet learning detects repeated retraining patterns across a specific package lot, board revision, connector family, thermal condition, or workload pattern, the signal becomes more important.

The system must ask:

• Is this random runtime behavior or a repeatable system EM corridor weakness?
• Does the pattern correlate with package escape, PCB material, connector transition, thermal gradient, return-path discontinuity, or voltage noise?
• Does it appear only under specific workloads or across all operating conditions?
• Does retraining preserve operation, or does it mask progressive margin loss?

Fleet learning can recommend a refinement: adjust validation thresholds, update link-margin assumptions, modify firmware retraining policy, or reopen a system EM corridor gate. But bounded gate authority decides whether that recommendation is admissible and actionable.

The gate should not close until the evidence is mature enough to distinguish a transient workload excursion from a real corridor degradation pattern.

Example 2: Voltage droop tied to one package lot

A runtime voltage droop may initially appear as a firmware or VRM issue. But fleet-scale evidence may show that the event occurs more frequently in systems built from one package lot, one substrate batch, one board stackup, one decoupling configuration, or one supplier population. That changes the engineering question.

The issue may involve package inductance, silicon switching current, decoupling placement, VRM response, PDN anti-resonance, substrate variation, thermal concentration, or workload-driven current transients.

Fleet learning can identify the population-level pattern. But the decision cannot be automatic. Bounded gate authority must determine whether the evidence is strong enough to reopen a package PDN assumption.

• Adjust firmware voltage policy
• Change validation stress conditions
• Hold a package lot
• Escalate to package reliability or failure analysis
• Approve a bounded runtime mitigation

The field may reveal the pattern, but the gate determines authority.

Example 3: Thermal asymmetry and package realization

Thermal asymmetry is common in AI systems because workloads are uneven, packages are large, and cooling solutions interact with board and chassis design. A single hot region may not prove a package problem.

But if repeated thermal asymmetry appears across a fleet and correlates with package construction, TIM behavior, lid attach, substrate warpage, airflow condition, or power map, it becomes lifecycle evidence. Here, fleet Learning may recommend updates to thermal guardbands.

• Package model assumptions
• Assembly admissibility criteria
• Firmware workload placement
• Throttling thresholds
• Future validation conditions

However, bounded gate authority must decide whether the evidence is mature enough to change policy. Otherwise, the system risks overcorrecting a local symptom and creating a new global instability.

Example 4: ECC events under workload and temperature

ECC events are another important fleet signal. An isolated ECC event may not indicate a major issue. But patterns across workload, temperature, voltage, memory stack, package lot, board configuration, or aging profile may reveal a deeper convergence problem. The source may be memory behavior, power noise, package stress, thermal gradients, firmware scheduling, silicon aging, or a wafer-to-package interaction.

Fleet learning can detect that the event population is no longer random. Next, bounded gate authority must determine whether to remain open and collect more evidence.

• Reopen a validation assumption
• Escalate to memory, package, or system teams
• Approve a bounded firmware mitigation
• Block a release configuration
• Refine next-generation design constraints

Again, the value is not only anomaly detection; it’s also governed lifecycle authority.

Example 5: When local firmware action creates fleet-level drift

The firmware–hardware handshake allows local corrective action. That is necessary. But local action can create fleet-level consequences.

A firmware policy that throttles one tile may preserve local thermal margin but shift workload stress to another region. A voltage adjustment may stabilize one condition but accelerate aging under another workload. A SerDes retraining rule may improve link continuity but increase synchronization overhead, operational variability, or latency across a cluster.

So, fleet learning is needed to detect these second-order effects. And bounded gate authority is needed to prevent uncontrolled policy changes.

So, the system must ask:

• Is the local action preserving global convergence?
• Is the firmware response still inside the approved action envelope?
• Does the correction create hidden thermal, timing, power, or reliability debt?
• Should the action remain approved, be narrowed, be escalated, or be retired?

This is the lifecycle version of the firmware–hardware handshake. Runtime action is not enough, and it must remain governed as fleet evidence accumulates.

Realization in practice: Reopening a validation assumption

Consider a next-generation AI accelerator cluster that successfully cleared pre-silicon signoff, post-silicon validation, and package-level qualification. After several months of deployment, firmware on multiple independent racks begins executing repeated SerDes link retraining sequences. A standard facility log may classify these events as isolated thermal excursions or normal link maintenance.

A governed fleet learning system treats the events differently. It aggregates the retraining events across the fleet, normalizes timestamps, maps them against package lots and board configurations, and compares them with workload signatures, thermal maps, substrate data, and system operating conditions.

The pattern becomes clear: the retraining events occur after localized multi-core workload bursts that generate a thermal gradient across a specific package/substrate population. This is no longer random operational noise. It’s a possible validation escape where real-world multi-physics interaction has violated an original design or package guardband.

Fleet learning generates the recommendation. And bounded gate authority evaluates the evidence package, checks admissibility, verifies causality, and may issue a Reopen outcome on the affected configuration milestone.

The system should not blindly mask the issue through continuous retraining. Instead, it can approve a bounded mitigation for the affected population while sending convergence-authoritative evidence back to validation, package engineering, firmware teams, and pre-silicon architecture groups.

That is the lifecycle loop. Field evidence does not simply become a log; it becomes governed input for the next design, package, validation, and firmware policy decision.

Closing the loop back to design and validation

The most important output of fleet learning is not only field mitigation; it’s lifecycle refinement. Mature fleet evidence should flow back into pre-silicon design assumptions.

• Package constraints
• System EM corridor models
• PDN and CPAM assumptions
• Firmware policies
• Thermal guardbands
• Qualification thresholds
• Design for test (DFT) and observability planning
• Manufacturing tolerances
• Supplier and lot-level evidence models
• Next-generation architecture decisions

This is how the silicon governance loop closes and the field becomes a governed evidence source for the next design cycle. But only if the evidence is admissible.

That requires the SEGA-AI stack in which test case generator (TCG) protects trust and admissibility.

• Convergence evidence maturity hierarchy (CEMH) defines evidence maturity
• Fleet learning recommends lifecycle refinement
• Bounded gate authority approves the decision

Without this structure, field telemetry remains operational logging. With this structure, field telemetry becomes lifecycle convergence evidence.

The SEGA-AI view

From a SEGA-AI perspective, fleet learning is not an uncontrolled feedback loop. It’s a governed lifecycle refinement system; it does not replace engineering judgment.

• It does not replace firmware teams.
• It does not replace validation.
• It does not replace failure analysis.
• It does not independently close gates.

It connects runtime behavior to governed decision authority. That allows deployed systems to improve future realization decisions while preserving deterministic control. And that is the difference between learning from the fleet and being controlled by the fleet.

Closing the silicon governance loop

The semiconductor industry has moved beyond isolated design-time closure. In the era of hyperscale AI platforms, multi-die chiplets, HBM systems, advanced packages, and volatile workloads, no single signoff event can guarantee long-term physical convergence across thousands of deployed systems.

The answer is not unconstrained autonomous adaptation. The answer is governed lifecycle learning.

Fleet learning provides the analytical path to uncover systemic patterns, detect drift, and recommend refinement. Bounded gate authority provides the engineering boundary that determines whether those recommendations are mature, admissible, causally aligned, and safe enough to act upon.

Together, they close the silicon governance loop.

Dr. Moh Kolbehdari is senior director of IC/packaging at Socionext US.

Editor’s Note

This is Part 3 of the article series about silicon governance framework. Part 1 explained why data movement alone cannot explain system behavior in modern AI chip designs. Next, Part 2 described the firmware-hardware handshake in a silicon governance system.

Related Content

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• Development tool evolution – hardware/firmware
• Hardware Root of Trust Essential for AI Chip Integrity
• What you need to know about firmware security in chips
• Hardware Verification: What AI Gets Right When It Generates Your Testbench

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