Новини світу мікро- та наноелектроніки

Automotive Skills Development Council (ASDC) hosted its 14th Annual Conclave 2025, themed “Stronger Together, Transform Tomorrow”, bringing together leaders from government, industry, and academia to deliberate on the future of skilling in the automotive sector.

The event commenced with the traditional lamp lighting ceremony. F.R. Singhvi, President, ASDC, presented the Annual Update, highlighting the Council’s 2024–25 impact—key achievements included forging partnerships with universities, advancing women’s skill development and employment, strengthening industry–academia collaboration, and expanding its international footprint. This was followed by addresses from the Guests of Honour: C.S. Vigneshwar (President, FADA), Shradha Suri Marwah (CMD, Subros Limited & President, ACMA), C.V. Raman (CTO, Maruti Suzuki India Ltd.), and Dr. Vinita Aggarwal, IES (Retd.), Executive Member, NCVET.

C.V. Raman, CTO, Maruti Suzuki India Ltd, emphasized that India’s mobility future will be driven by advanced engineering, digitalization, and disruptive technologies such as EVs, IoT, and AI. To realize the $5 trillion vision, he stressed the need for skilling to evolve by integrating experiential learning, fostering industry–academia collaboration, and leveraging startup innovation.

Dr. Vinita Aggarwal highlighted the importance of qualification standardization, stating: “India’s journey to becoming a global skill hub is powered by standardization and industry alignment. With over 180 automotive QPs under NSQF, we must ensure they remain dynamic—integrating hands-on training, apprenticeships, and micro-credentials. The automotive sector should actively adopt and upgrade these QPs to build a future-ready, tech-driven workforce.”

Speaking at the conclave, F R Singhvi, President, ASDC, remarked: “This conclave has reinforced our belief that India’s skilling ecosystem thrives on partnerships. Together, we are shaping a workforce that is not only job-ready but future-ready.”

A major milestone of the conclave was the release of a White Paper and the signing of MoUs with Hero MotoCorp, Bajaj Auto, Gandhi Auto, Delphi TVS, and Bosch India to scale up skilling initiatives nationwide.

The conclave also hosted two high-impact panel discussions: Academic Excellence to Industry Impact: Aligning Talent Pipelines with Future Mobility Technologies and From Garage to Gigabyte: Skilling for Next-Gen Automotive Technologies. These sessions examined how new-age skilling can bridge classroom learning with the demands of digital-first, tech-driven automotive industries.

Vinkesh Gulati, Vice President, ASDC, added: “Our collective responsibility is to ensure that every young aspirant finds a place in the industry’s growth story. ASDC is committed to bridging the gap between potential and opportunity.”

The Certified Candidates Convocation felicitated skilled candidates from ASDC’s flagship programs, underscoring its commitment to inclusive skill development. Presentations on CSR Best Practices by Bajaj Auto and Hero MotoCorp Ltd. showcased impactful industry-led skilling models. Recognitions included Internationally Placed Candidates, Rewards & Recognition Awards, and the ASDC Excellence and Special Recognition Awards, celebrating exemplary contributions to the skilling ecosystem.

The conclave firmly reiterated that public-private partnerships will be the cornerstone in addressing the evolving needs of the automotive industry and enabling India to emerge as a global leader in mobility technologies.

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The landscape of IC design is experiencing a profound transformation. With the physical and economic limits of conventional two-dimensional scaling, the industry is rapidly embracing three-dimensional integrated circuits (3D IC) to unlock higher performance, lower power consumption, and denser silicon utilization.

For semiconductor professionals, understanding the distinct nuances of 3D IC microarchitectures is no longer optional. It’s becoming essential for those seeking to maintain a competitive edge in next-generation system design.

Microarchitecting in the 3D IC era represents more than an incremental change from traditional practices. It entails a fundamental redefinition of how data and controls move through a system, how blocks are partitioned and co-optimized across both horizontal and vertical domains, and how early-stage design decisions address the unique challenges of 3D integration.

This article aims to provide essential context and technical depth for practitioners working toward highly integrated, efficient, and resilient 3D IC systems.

3D IC technology now stands at a pivotal juncture. Source: Siemens EDA

Putting things in context

To grasp the impact of 3D IC, it’s crucial to define microarchitecture in the IC context. System architecture typically refers to a design’s functional organization as seen by software engineers—abstract functions, data flows, and protocols. Microarchitecture, viewed through the hardware engineer’s lens, describes how those features are realized in silicon using components like register files, arithmetic logic units, and on-chip memory.

Microarchitecture centers around two domains: the datapath, which encompasses the movement and transformation of data, and the control, which dictates how and when those data movements occur. Together, they determine not only performance and efficiency but also testability and resiliency.

Furthermore, while traditional ICs optimize microarchitecture in two dimensions, 3D ICs require designers to expand their strategies into the vertical axis as well. Because data in 3D ICs no longer flows only laterally, it must be orchestrated through stacked dies, each potentially featuring its own process technology, supply voltage, or clock domain. Inter-die communication—typically realized with micro-bumps, through-silicon vias, or hybrid bonding—becomes critical for both data and control signals.

With the move toward submicron interconnection pitches, design teams must address tighter integration densities and the unprecedented task of partitioning logic and memory across multiple vertical layers. This process is not unlike assembling a three-dimensional puzzle.

Effective microarchitecture in this context demands careful co-optimization of logic, physical placement, routing, and inter-die signaling—with far-reaching implications for system latency, bandwidth, and reliability.

Moreover, some microarchitectural components can be realized in three dimensions themselves. Stacked memory sitting directly above compute units, for example, enables true compute-in-memory subsystems, affecting both density and performance but also introducing significant challenges related to signal integrity, thermal design, and manufacturing yield.

Taking complexity to the third dimension

A major trend shaping modern IC development is the shift toward software-defined silicon, where software can customize and even dynamically control hardware features. While this approach provides great flexibility, it also increases complexity and requires early, holistic consideration of architectural trade-offs—especially in 3D ICs, where the cost of late-stage changes is prohibitive.

The high costs of 3D IC design and manufacturing in general demand an upfront commitment to rigorous partitioning and predictive modeling. Errors or unforeseen bottlenecks that might be addressed after tape-out in traditional design can prove disastrous in 3D ICs, where physical access for rework or test is limited.

It is thus essential for system architects and microarchitects to collaborate early, determining both physical placement of blocks and the allocation of functionality between programmable and hardwired components.

This paradigm also introduces new questions, such as which features should be programmable versus fixed? And how can test coverage and configurability be extended into the post-silicon stage? Design teams must maintain a careful balance among performance, area, power, and system flexibility as they partition and refine the design stack.

Among the most significant physical challenges in 3D integration is the sharp increase in power density. Folding a two-dimensional design into a 3D stack compresses the area available for power delivery, while escalating local heat generation. Managing thermal issues becomes significantly more difficult, as deeper layers are insulated from heat sinks and are more susceptible to temperature gradients.

Test and debug also become more complex. As interconnect pitches shrink below one-micron, direct probing is not practical. Robust testability and resilience need to be designed in from the architecture and circuit level, using techniques like embedded test paths, built-in self-test, and adaptive power management long before finalization.

Finally, resiliency—the system’s ability to absorb faults and maintain operation—takes on new urgency. The reduced access for root-cause analysis and repair in 3D assemblies compels development of in-situ monitoring, adaptive controls, and architectural redundancy, requiring innovation that extends into both the digital and analog realms.

The need for automation

The complexity of 3D IC design can only be managed through next-generation automation. Traditional automation has centered on logic synthesis, place and route, and verification for 2D designs. But with 3D ICs, automation must span package assembly, die stacking, and especially multi-physics domains.

Building 3D ICs requires engineers to bridge electrical, thermal, and mechanical analyses. For instance, co-design flows must account for materials like silicon interposers and organic substrates. This necessitates tightly integrated EDA tools for early simulation, design-for-test verification, and predictive analysis—giving teams the ability to catch issues before manufacturing begins.

System heterogeneity also sets 3D IC apart. Diverse IP, technology nodes, and even substrate compositions all coexist within a single package. Addressing this diversity, along with long design cycles and high non-recurring engineering costs, demands multi-domain, model-based simulation and robust design automation to perform comprehensive early validation and analysis.

Meanwhile, traditional packaging workflows—often manual and reliant on Windows-based tools—lag far behind the automated flows for silicon IC implementation. Closing this gap and enabling seamless integration across all domains is essential for realizing the full promise of 3D IC architectures.

The evolving role of AI and design teams

As system complexity escalates, the industry is shifting from human-centered to increasingly machine-centered design methodologies. The days of vertical specialization are yielding to interdisciplinary engineering, where practitioners must understand electrical, mechanical, thermal, and system-level concerns.

With greater reliance on automation, human teams must increasingly focus on oversight, exception analysis, and leveraging AI-generated insights. Lifelong learning and cross-functional collaboration are now prerequisites for EDA practitioners, who will require both broader and more adaptable skillsets as design paradigms continue to evolve.

Artificial intelligence is already transforming electronic design automation. Modern AI agents can optimize across multiple, often competing, objectives—proposing floorplans and partitioning schemes that would be unfeasible for manual evaluation. Looking ahead, agentic AI—teams of specialized algorithms working in concert—promise to orchestrate ever more complex design sequences from architecture to verification.

Building failure resilient systems

As the boundaries between architectural roles blur, collaboration becomes paramount. In a world of software-defined silicon, architects, microarchitects, and implementation engineers must partner closely to ensure that design intent, trade-offs, and risk mitigation are coherently managed.

Real-world progress is already visible in examples like AMD’s 3D integration of SRAM atop logic dies. Such hybrid approaches demand careful analysis of read and write latency, since splitting a kernel across stacked dies can introduce undesirable delays. Partitioning memory and processing functions to optimize performance and energy efficiency in such architectures is a delicate exercise.

Heterogeneous integration also enables new microarchitectural approaches. High-performance computing has long favored homogeneous, mesh-based architectures, but mobile and IoT applications may benefit from hub-and-spoke or non-uniform memory access models, requiring flexible latency management and workload distribution.

Adaptive throttling, dynamic resource management, and redundancy strategies are growing in importance as memory access paths and their latencies diverge, and architectural resiliency becomes mission critical.

As failure analysis becomes more complex, designs must include real-time monitoring, self-healing, and redundancy features—drawing upon proven analog circuit techniques now increasingly relevant to digital logic.

Thermal management presents fresh hurdles as well: thinning silicon to expose backside connections diminishes its native lateral thermal conductivity, potentially requiring off-die sensor and thermal protection strategies—further reinforcing the need for holistic, system-level co-design.

3D IC moving forward

3D IC stands at a pivotal juncture. Its widespread adoption depends on early, multi-disciplinary design integration, sophisticated automation, and a holistic approach to resiliency. While deployment so far has largely targeted niche applications, such as high-speed logic-memory overlays, 3D IC architectures promise adoption across more segments and vastly more heterogeneous platforms.

For industry practitioners, the challenges are formidable, including three-dimensional partitioning, integrated automation across disciplines, and entirely new approaches to test, debug, and resilience. Meeting these challenges requires both technical innovation and significant organizational and educational transformations.

Success will demand foresight, tight collaboration, and the courage to rethink assumptions at every step of the design cycle. Yet the benefits are bountiful and largely untapped.

Todd Burkholder is a senior editor at Siemens DISW. For over 25 years, he has worked as editor, author, and ghost writer with internal and external customers to create print and digital content across a broad range of EDA technologies. Todd began his career in marketing for high-technology and other industries in 1992 after earning a Bachelor of Science at Portland State University and a Master of Science degree from the University of Arizona.

Pratyush Kamal is director of Central Engineering Solutions at Siemens EDA. He is an experienced SoC and systems architect and silicon technologist providing technical leadership for advanced packaging and new foundry technology programs. Pratyush previously held various jobs at Google and Qualcomm as SoC designer, SoC architect, and systems architect. He also led 3D IC research at Qualcomm, focusing on both wafer-on-wafer hybrid bond and monolithic 3D design integrations.

Editor’s Note

This is the first part of the three-part article series about 3D IC architecture. The second part, to be published next week, will focus on how design engineers can put 3D IC to work.

Related Content

• 3D IC Design
• Thermal analysis tool aims to reinvigorate 3D-IC design
• Heterogeneous Integration and the Evolution of IC Packaging
• Tighter Integration Between Process Technologies and Packaging
• Advanced IC Packaging: The Roadmap to 3D IC Semiconductor Scaling

The post Making your architecture ready for 3D IC appeared first on EDN.

Reinforcement Learning (RL) algorithms represent a class of machine learning methodologies where an agent learns to make decisions through interactions with an environment. The agent gets feedback in the form of rewards or punishments bestowed on it for the actions it takes, and the overall objective is to maximize cumulative rewards through time. Differing from supervised learning, RL does not rely upon labeled data, but rather it learns from experience. Through trial and error, reinforcement learning excels at solving sequential decision-making problems across domains like robotics, gaming, and autonomous systems especially when using value-based algorithms that estimate future rewards to guide action.

Main types of Reinforcement Learning (RL) algorithms:

1. Value-Based Algorithms

Value-based algorithms primarily work towards evaluating the potential benefits an action may have in a given condition while making a decision. Value-based methods usually learn a value function known as the Q-value, which specifies the expected reward in the future by taking a particular action in a certain state. The agent executes an action with the aim of maximizing this value. An example of such algorithms is the Q-Learning algorithm wherein Q-values are updated through the Bellman equation. More advanced versions are Deep Q-Networks (DQN) that approximate these values by using neural networks in high-dimensional environments such as video games.

2. Policy-Based Algorithms

Policy-based algorithms directly learn a policy that maps states to actions without estimating value functions. These methods optimize the policy using techniques like gradient ascent to maximize expected rewards. They are particularly useful in environments with continuous action spaces. One popular example is REINFORCE, a Monte Carlo-based method. Another widely used algorithm is Proximal Policy Optimization (PPO), which improves training stability by limiting how much the policy can change at each update.

3. Model-Based Methods:

These algorithms learn the model and simulate the evolution of states from an initial state and finally an action. Once the dynamics model is learned, the agent can use it to simulate the future states and choose the best action without ever interacting with the real environment. This family of algorithms is very sample-efficient and suitable for cases where acquiring data is either very costly or risky. An example that revolutionized the field is MuZero, which learns the model and the policy without ever being given the rules of the environment;at the same time, it attains state-of-the art performance in Go, Chess, and other board games.

4. Actor-Critic Algorithms 

Actor-Critic algorithms are a hybrid reinforcement learning technique that combine the advantages of both value-based and policy-based methods. Actor-critic methods maintain two perspectives: the actor decides what action to take, while the critic evaluates how good the action was by employing a value function. This idea of two perspectives given stability to the training process and fosters great performance. Examples of algorithms: Advantage Actor-Critic(A2C), Asynchronous Advantage Actor-Critic(A3C), and Soft Actor-Critic (SAC) These are typically used in continuous control problems such as in robotics and autonomous driving.

Examples of Reinforcement Learning Algorithms:

Some widely used RL algorithms are Q-Learning, Deep Q-Networks (DQN), Proximal Policy Optimization (PPO), and Soft Actor-Critic (SAC). Q-Learning is a basic algorithm that learns the value of actions in discrete environments. On the other hand, DQN uses deep neural networks to work with high-dimensional inputs such as images and videos. PPO is a policy-based algorithm known for its stability and efficiency in continuous control tasks and hence is often applied in robotics. SAC is an actor-critic method that uses entropy regularization to promote exploration and thus achieves a very good performance in brutally difficult environments.

Top 10 reinforcement learning algorithms:

1. Q-Learning

Since it is a value-based algorithm, Q-Learning is ideal for discrete action spaces. It learns by receiving rewards with which it updates Q-values for optimal action-selection policy. This makes it ideal, for example, in simple setups such as grid-worlds or basic games.

2. Deep Q-Network (DQN)

DQN is an extension of Q-Learning in which Q-values are approximated using deep neural networks, enabling it to handle high-dimensional inputs such as raw pixels. It has had a great impact on RL by offering a solution for agents to play Atari games straight from screen images.

3. Double DQN

Double DQN improves DQN by reducing overestimation bias through decoupled action selection and evaluation, resulting in more stable learning.

4. Dueling DQN

Dueling DQN extends DQN by splitting the state value estimation and action advantage estimation, which is particularly beneficial for problems with many similar actions.

5. Proximal Policy Optimization (PPO)

PPO is a policy algorithm that is both stable and efficient. It employs a clipped objective to avoid sudden policy updates and thus performs well in continuous control tasks such as robotics and locomotion.

6. Advantage Actor-Critic

Advantage Actor-Critic is policy and value learning combined, which makes it applicable to real-time decision-making in dynamic, multi-agent environments.

7. Deep Deterministic Policy Gradient (DDPG)

DDPG is geared for continuous action spaces and employs a deterministic policy gradient algorithm. It’s best applied to tasks such as robotic arm control and autonomous vehicles, where accuracy matters when it comes to actions.

8. Twin Delayed DDPG (TD3)

TD3 improves DDPG with the addition of twin critics to mitigate overestimation and policy update delay for improved stability. These features make it particularly suitable for high-precision control in difficult simulations.

9. Soft Actor-Critic (SAC)

SAC promotes exploration with the incorporation of an entropy bonus to the reward signal. This allows the agent to strike a balance between exploration and exploitation, making it extremely sample-efficient and powerful in deep exploration-requiring environments.

10. MuZero

MuZero is a model-based algorithm that learns an environment model without knowing its rules. It unifies planning and learning to deliver state-of-the-art performance on strategic games such as Chess, Go, and Atari, and it’s one of the most sophisticated RL algorithms to exist.

The post Top 10 Reinforcement Learning Algorithms appeared first on ELE Times.

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As technology remains the perennial growth factor across all industries, the automotive sector is no exception to this phenomenon. Ranging from System-on-Chips (SoCs) to ADAS, modern-day automobiles have turned into machines driven by software and semiconductors. The integration of technology in automobiles has led to the emergence of modern-day connected and software-driven vehicles. As these vehicles hit the roads, it’s essential to highlight the breakthroughs, challenges, and opportunities they bring to the table. 

The e-Mobility Conference returns for its third edition on September 17th, 2025, at BIEC, Bangalore, alongside electronica India and productronica India, serving as a platform for the industry to voice challenges, share concerns, explore opportunities, and highlight key breakthroughs and insights.

Click here to secure your free seat in the conference now! 

In its 3rd edition, the conference is set to take up the theme “Silicon to Mobility: EVs’ Quantum Leap,” where the eminent speakers and moderators will discuss the semiconductor components of EVs in detail. The conversations and discussions would focus on issues ranging from composition, implementation, observations, and others. As the conference unfolds, it will look into some specific issues that present some substantial opportunities for the automotive industry. 

One among them is the issue of standardization, where the panel would look into a wholesome integration and composition of semiconductors in EVs, keeping in mind the dynamics of the market and demand already in place. As the conference moves forward, the discussions over the composition and integration aspect will move into the subject matter of Software Defined Vehicles (SDVs), underlining how chips and software are transforming the way we perceive vehicles. It will talk about the emergence of SDVs and how this transformational shift is gradually pushing the ownership as well as after-sales revenue in the automotive sector. 

In its later part, the conference would take up Advanced Driver Assistance System (ADAS) to discuss how data-driven decisions and command and control can prevent accidents on the road, enabling a safer and healthier automotive landscape in the country and worldwide. Finally, the conference would rise to discuss the conundrum of semiconductor supply chains and how geopolitics is getting heavily in the way as nations double down on trade barriers and global trade receives a jolt from some specific policies. 

To witness all this firsthand for free and also get a chance to ask questions, register here!

As India and the world rise to adopt and embrace EVs, it becomes more important than ever to look into how we can shape these transformations to enable seamlessness and convenience for our people across the globe. 

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The company's newest SoC increases small-device edge computing performance while reducing cost and power consumption to deliver a 10-year operating life with a coin cell.