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Amid the stagnation of Moore’s law, NeoLogic develops a technology that overcomes the limitations of the existing 40-year-old chip design technology. It enables the design of more powerful chips with lower energy consumption and reduced costs for high-performance computing, artificial intelligence tasks, machine learning, machine vision, and more.

Israel-based processor technology startup NeoLogic announces raising an 8-million-dollar seed round led by Maniv Mobility venture capital fund with lool Ventures and M-Ventures. The company is also supported by the Israeli Innovation Authority. The funding is coming on the heels of a year in which venture capital funds’ appetite for making new investments has plummeted.

NeoLogic developed a unique chip design technology that they call Quasi-CMOS. It reduces the transistor count of a microprocessor by up to a third of its originally designed number of transistors. The technology makes it possible to develop processors of higher computing power and more energy-efficient while significantly reducing their price. It aims to meet accelerating workloads of artificial intelligence tasks, machine learning, video processing, data science, and the like in data centers and at the edge.

NeoLogic was founded in 2021 by Dr. Avi Messica (CEO) and Ziv Leshem (CTO), both of whom have decades of experience in R&D and management of microprocessors design and fabrication. It employs 13 employees and is currently recruiting additional employees. The company is already seeing a lot of strong interest from customers.

Dr. Avi Messica, co-founder and CEO of NeoLogic: “The processor market for data centers is currently estimated at 110 billion dollars. In the near future, AI accelerators will make up a significant percentage of data center processors. Current microprocessors rely on 40 years old (CMOS) technology. Chip designers are struggling to meet the current and future computation power and power consumption requirements. NeoLogic’s technology breaks through the limitations of CMOS, reduces the complexity of digital circuits, and offers a dramatic improvement in the price-performance ratio and chip area. We have filed three patent applications so far. We thank the funds that invested in the company and their vote of confidence in our technology and the team.”

Nate Jaret, a general partner at Maniv Mobility, a fund that invests in innovative technologies and business models that reimagine the world of transportation and who led the round, said: “NeoLogic’s innovative architecture represents a paradigm shift in the development of microprocessors at a period when groundbreaking innovations in the semiconductor industry generate exceptional economic value. We believe that NeoLogic has a unique opportunity to bring about a far-reaching change in the way processor manufacturers design the next generations of chips that will be more powerful, more energy efficient, and significantly cheaper. We are proud to join this journey of Avi and Ziv together with the other investors in the company.”

Yaniv Golan, managing partner at lool ventures, a leading Israeli seed fund, said: “Our investment in NeoLogic reflects our belief in the company’s groundbreaking technology and its ability to bring about a significant change in the way companies develop advanced processors.”

Dr. Avi Messica (Ph.D. Weizmann Institute of Science) is an expert in solid-state physics and quantum devices and in ultrafast transistors in particular with 25 years of managerial experience in a variety of hi-tech companies. Messica previously served as a device group manager at Tower Semiconductors and has hands-on experience in the design and fabrication of CMOS devices. He also served as VP of Engineering at Shellcase and founded and served as the CEO of three semiconductor companies in the fields of image sensors, MEMS-based optical switches, and photonic chips.

Ziv Leshem has 24 years of experience in processor design. He worked for some of the world’s leading semiconductor companies, such as National Semiconductors, DSPG, and Synopsys, and managed complex processor design projects. He was one of the founders of LogixL, a company that developed a hardware-based HDL simulator and also served as a manager at NewSight Imaging, a developer of LiDAR and iTOF sensors. Before founding NeoLogic he was the manager of the physical design group at Inomize where he managed a group of engineers and developed processors for customers in various industrial sectors in CMOS technologies ranging from 40 nm to 7 nm.

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Silicon carbide (SiC) power semiconductors, making headlines for their vital role in electric vehicle (EV) inverters and charging infrastructure designs, are also steading making headway in large-scale renewable energy installations like solar inverters. This wide bandgap (WBG) semiconductor technology is turning solar inverters—ranging from utility to residential—into smaller, lighter and more efficient systems while minimizing energy loss and reducing overall system cost.

Case in point: onsemi has secured $1.95 billion in long-term supply agreements for providing SiC-based power semiconductor solutions to leading solar inverter manufacturers. Earlier this year, Navitas Semiconductor announced that solar inverter manufacturer KATEK is adopting its GeneSiC power semiconductors for improved efficiency, size, weight, and cost.

Figure 1 GeneSiC MOSFETs claim to offer 30% longer short-circuit withstand time and stable threshold voltage for easy paralleling. Source: Navitas

The Munich, Germany-based KATEK develops and produces power electronics for grid inverters, energy storage, and control technology for photovoltaic and fuel cell systems. Its Steca solar inverters convert DC power from a string of solar panels into 4.6-kW AC power for use in the home, returning to the grid, or being stored locally for later use.

Solar inverters convert direct current (DC) electricity solar panels generate to grid-compatible alternating current (AC). In the conversion process, however, some energy is lost as heat. Here, SiC semiconductors, though more expensive than silicon solutions, offer higher switching speeds and efficiency, allowing transformers, capacitors, heat sinks, and ultimately, packages to be smaller.

When SiC devices facilitate a significant increase in switching frequency, it shrinks the size and weight of passive components, which optimizes the size and weight compared to legacy silicon-based inverters. That, according to Infineon’s senior executive Peter Wawer, saves cost at the system level.

Fronius Solar Energy, a solar inverter supplier based in Munich, Germany, has incorporated Infineon’s CoolSiC MOSFETs in its power modules. The company’s Symo GEN24 Plus solar inverters facilitate power for direct use in the household while also offering an interface for energy storage systems.

Figure 2 Fronius claims that the use of 1,200-V CoolSiC MOSFETs has significantly improved the functionality of its Symo GEN24 Plus solar inverter while its size remains comparable. Source: Infineon

According to “Renewables 2022,” a report published by the International Energy Agency (IEA), installed solar power capacity is expected to exceed that of natural gas in 2026 and coal by 2027. That will make solar power the world’s largest energy source while also recording a 3x increase in installed capacity from 2022-2027.

Next, research company BloombergNEF (BNEF) claims that the global levelized solar electricity cost is now 40% lower than coal and natural gas. That makes solar power one of the fastest-growing markets. And SiC devices seem prominent in this energy revolution encompassing power grids and energy storage systems.

Related Content

• Wafer supply deals herald the upcoming SiC boom
• SiC and resurgence of semiconductor vertical integration
• Chipmakers’ quest for wafers supply affirms SiC adoption
• Silicon carbide (SiC) and the road to 800-V electric vehicles
• APEC 2023: SiC moving into mainstream, cost major barrier

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AAEON’s newest developer board offers Intel Processor N-series processors, LPDDR5, and TPM 2.0 onboard.

AAEON’s UP brand, renowned for producing sophisticated developer boards with industrial-grade specifications, has announced the release of the UP 7000, the third generation of boards built on the 85mm x 56mm form factor of the original UP Board.

The UP 7000 boasts numerous upgrades compared to its predecessors, including 8GB of LPDDR5 system memory, onboard TPM 2.0, and support for both Windows and Linux OS. Most notably, it stands out as the world’s smallest board featuring onboard CPUs from the Intel Processor N-series platform.

The board is available in various SKUs, hosting Intel Processor N97, Intel Processor N100, or Intel® Processor N50 CPUs. Notably, these processors offer clock speeds up to 50% faster than those of previous boards from the same product line, and also support Intel AVX2 for energy-efficient AI acceleration.

Equipped with three USB Type-A ports for USB 3.2 Gen 2, one GbE LAN port supporting Realtek RTL8111H CG, and a Raspberry Pi-compatible 40-pin HAT for expansion, the UP 7000 provides a dense port configuration. This makes it ideal for applications requiring low latency but versatile connectivity, such as AMR and multifunction printing device solutions.

The UP 7000 also features an HDMI 1.4b Type-A port, which is dual-stacked with one of its three USB 3.2 Gen 2 ports for board space efficiency. AAEON emphasizes that this inclusion allows developers to harness the power of Intel® UHD Graphics, offering a higher number of execution units and greater frequency than the previous generation. This results in faster rendering and higher FPS for digital signage solutions.

Established in 1992, AAEON is one of the leading designers and manufacturers of industrial IoT and AI Edge solutions. With continual innovation as a core value, AAEON provides reliable, high-quality computing platforms including industrial motherboards and systems, rugged tablets, embedded AI Edge systems, uCPE network appliances, and LoRaWAN/WWAN solutions. AAEON provides industry-leading experience and knowledge to provide OEM/ODM services worldwide. AAEON also works closely with cities and governments to develop and deploy Smart City ecosystems, offering individual platforms and end-to-end solutions. AAEON works closely with premier chip designers to deliver stable, reliable platforms, and is recognized as a Titanium member of the Intel® Internet of Things Solutions Alliance. For an introduction to AAEON’s expansive line of products and services, visit www.aaeon.com.

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We’re always looking to harvest energy from diverse, nominally “free” sources such as wind, water, solar, and even less-dense possibilities such as vibration and friction. Then there are lightning strikes which are potential energy sources are wasted, as well as often being destructive. (Lighting strikes are surprisingly common; the European Meteosat Third Generation satellite launched in December with cameras which can track and record lightning strikes, even the smallest and fastest ones, day and night, over more than 80 percent of Earth’s surface.)

Could that wasted-energy situation change? Unlikely – but as we know, it’s “never say never” when it comes to technology and advances. Back in January, a European-based team published an interesting paper in Nature Photonics with the surprisingly simple title “Laser-guided lightning.”) It detailed how they blasted repeated pulses from a high-power laser to guide lightning strikes that were as far as two miles away down to a relatively small, grounded rod near their Swiss-mountain setup, Figure 1 [1].

Figure 1 a) Layout of the experimental setup on top of the Säntis Mountain in Switzerland. b) Photography of the experiment with the second harmonic of the laser beam used to visualize the laser path. Source: “Laser Guided Lightning”, Nature photonics, 2023

The likely explanation is that the laser pulses super-heated the air, which caused the air to become electrically conductive along the path of the laser, Figure 2. 

Figure 2 Snapshots of the lightning event of 24 July 2021 recorded in the presence of the laser. Source: “Laser Guided Lightning”, Nature photonics, 2023

This ability to perhaps direct a lightning strike brings up an obvious question: why not channel this energy to some sort of energy storage system (ESS)? After all, that energy is otherwise wasted since it is truly and literally grounded. (I’ve even seen so-called “experts” suggest this as a no/low-cost energy source.)

If only it were that easy. A good first question is this: how much energy and power is there in a lightning strike? The answer spans a wide range, but according to Tess Light in the Space and Remote Sensing group at Los Alamos National Laboratory, lightning is “both incredibly powerful and crazy fast” and each strike delivers about fifty thousand amps in just microseconds, with a megavolt punch.

Furthermore, while each strike delivers around five or ten gigajoules of energy (one GJ = 109 joules), much of that energy is lost in heating the air and so is not “capturable” electrical energy. (To give you some sense of scale, a large EV battery has a capacity of about 100 kilowatt hours, or 3.6 × 108 joules.) So even though lightning does seem to have a lot of energy, it’s really not that much and you’d need a lot of strikes.

Why not make it simple, and use a totally passive, simple lightning rod? The answer has to do with the lightning rod’s range of effectiveness.

Although the exact number is a function of atmospheric, ground, and other conditions, a general guide is that a standard rod can attract lightning within a radius equal to its height. Thus, you’d need a large “farm” of lightning rods with some combination of a large amount of land area and tall rods. The laser-based scheme increases the capture area and decreases the rod height requirements.

There’s yet another issue: Is directing lightning via lasers worthwhile from an energy-balance viewpoint? Even if it is technically viable, the laser scheme has its own major drawback, as it uses a lot of power itself. The researchers used a Yb:YAG laser emitting picosecond pulses at 500 MJ energy with a wavelength of 1,030 nm and a 1-kHz repetition rate. In other words, the energy cost of driving the lasers was greater than that of the captured lightning.

This imbalance is somewhat analogous to the recent fusion “success” report from the National Ignition Facility (NIF) in California. They focused about 2 MJs of energy from hundreds of lasers onto a tiny capsule of fusion fuel, sparking an explosion that produced about 3 MJ of energy. While this is a breakthrough in many ways and took years (and $) to happen, the laser-drive subsystem itself is only 1% efficient, so about 200 MJ was needed as the total project input energy—not a winning equation.

Even if the power-balance was favorable for harvesting lightning, it still doesn’t address another intractable problem between captured lightning and any known ESS. How do you get that much power (the rate of energy transfer) into the battery? No existing battery or ESS could survive that enormous power surge—and that’s what it is.

Of course, the next step in such research almost always involves “bigger” and “more money.” The lead researcher was quoted in news reports as saying that they would like to increase the distance that the laser can guide the lightning to hundreds of meters. That is theoretically possible with a bigger, more powerful laser, but the prototype laser used in this demonstration cost 2 billion euros. (If that’s out of your budget, you may have to stick with something simpler, such as a four-transistor DIY lightning detector, see “Simple analog-centric circuits expand STEM perspectives.”)

There’s an interesting historical link to this entire lightning-capture story. Before current-flow electricity as we use today existed, Benjamin Franklin actually captured some lightning energy in a Leyden jar (an early type of capacitor) during his famous kite-flying experiment. This is not myth or legend, as it was properly documented at the time (the Wikipedia entry “Kite experiment” has a clear discussion and credible reference links).

Franklin split the kite’s “downlead” by using wet hemp string as a conductive lead to the Leyden jar and an insulating silk thread on the other branch to his son who was flying the kite, who stayed in a shed so as to not get wet. He succeeded in showing the relationship between static electricity and lightning before electricity (static or otherwise) was understood or had any practical uses.

As for harvesting lightning today, it looks like it’s the same story: no matter how attractive it may seem at first, large-scale energy harvesting doesn’t come easy, and there is no “free lunch” out there.

Bill Schweber is an EE who has written three textbooks, hundreds of technical articles, opinion columns, and product features.

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LumeDEL LLC introduces the NewDEL Fiber-coupled LED sources that are designed to generate high radiant power with spectrally stable output and combining high performance with ease-of-use. NewDEL LED sources can be highly effective replacements for lasers and lamps in many applications for scientific and industrial applications such as spectroscopy, optogenetics, photodynamic therapy, fluorescence excitation and photocatalysis.

LumeDEL’s NewDEL fiber-coupled LEDs include 17 narrowband models with peak wavelengths from the UV to the near-IR spectral regions, as well as two white light LEDs and a continuum source. The models offer complete configurability, from a continuous operating mode to pulsed or triggered modes, so that users at any level can set up a light source ideally suited to their needs.

A NewDEL fiber-coupled LED is a compact, fully integrated product. Each NewDEL incorporates its own driver and microcontroller circuitry. A separate driver/controller module is not required. Operation of a NewDEL can be performed through a feature-rich Windows-based GUI or personally programmed using distinct serial commands.

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Enhancing the Integration of DC and RF Signals with Unparalleled Frequency Spectrum

Fairview Microwave, an Infinite Electronics brand and a leading provider of on-demand RF, microwave and millimeter-wave components, has just unveiled its latest innovation, ultra-wideband bias tees, enhancing the fluid application of DC and RF signals in electronic devices.

The bias tees, available immediately, establish the DC bias point of electronic components without interfering with their performance. They command a sweeping frequency range from 50 kHz to a massive 110 GHz, accommodating a broad spectrum of applications to meet customers’ diverse needs.

A testament to Fairview Microwave’s commitment to flexibility, the bias tees accommodate both male and female W1 RF connector configurations, as well as an SMC male DC connector. They showcase robustness with compact, durable aluminum encasements that confidently meet the MIL-STD-202F tests for thermal shock, mechanical shock and vibration.

The bias tees promise not just proficient DC biasing courtesy of the SMC connector but also exhibit metrology-grade quality. With their sturdy mechanical designs and W1 1 mm connectors, they ensure reduced signal interference, low insertion loss and superior return-loss characteristics.

Fairview Microwave remains steadfast in its commitment to environmental stewardship and sustainability. Upon launch, the ultra-wideband bias tees are compliant with the RoHS, adhering to the Restriction of Hazardous Substances directive.

“This product melds leading-edge technology with a sustainable approach, said Product Line Manager Kevin Hietpas. “Our ultra-wideband bias tees exemplify our dedication to superior quality and customer service and our commitment to making a positive contribution to the environment.”

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Count On Tools, Inc. (COT), a leading provider of precision components and SMT spare parts, is pleased to introduce its latest breakthrough: a special vacuum nozzle designed to handle all types of odd-shaped components with unmatched precision. Part number 2023-5260, the latest addition to its line of vacuum nozzles, revolutionizes the handling process of the SKT108775GQS 42-position 2 mm header.

Count On Tools’ Custom Machine Shop developed a compliant center nozzle, paired with two outlying supports, offering exceptional accuracy and consistency during the placement process. With this specialized vacuum nozzle, customers can now effortlessly and reliably place the challenging SKT108775GQS header — a feat that was previously reliant on a manual hand placement process.

The introduction of part number 2023-5260 exemplifies Count On Tools’ commitment to addressing the evolving needs of the electronics manufacturing industry. By providing a custom solution tailored to handle odd-shaped components, the company enables manufacturers to optimize their production processes and enhance overall productivity.

“We take pride in developing cutting-edge solutions that empower our customers to overcome manufacturing challenges,” said Curt Couch, Vice President at Count On Tools. “The specialized vacuum nozzle, part number 2023-5260, is a testament to our dedication to innovation and customer-centricity. It streamlines the handling of the SKT108775GQS header, enabling our clients to achieve greater accuracy and efficiency in their operations.”

Being a one-stop shop, the company strives to offer the widest range of SMT nozzles and consumables as possible. All COT products are NEW and meet or exceed all OEM specifications. COT parts are a direct replacement, ultimately saving over buying directly from the OEM.

Count On Tools is a leading provider of precision machined components, SMT spare parts and Swiss-made hand tools, locally and globally. The company has won numerous awards for its quality products and service.

Count On Tools holds and maintains current ITAR registration, 07FFL, 02SOT, and a first-class Quality Management System.

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Infineon Technologies AG announced the new TEGRION security controller family, the company’s broadest portfolio of 28 nm security controllers. It integrates the new Integrity Guard 32 security architecture and an advanced Arm v8-M instruction set for enhanced device performance. TEGRION security controllers offer ease of implementation, fast design-in and time-to-market, while supporting long product lifecycles. The broad portfolio of TEGRION security controllers is designed to support a wide range of applications from smart home, smart mobility and smart industry to payment, identity and lifestyle.

“By investing in and launching the TEGRION security controller family, Infineon is demonstrating its long-term commitment to the security market. It is the most powerful security controller family the company has ever launched,” said Ioannis Kabitoglou, Senior Vice President & General Manager Digital Security & Identity at Infineon. “Based on the positive customer feedback, we are confident that the TEGRION security controller family will meet current and future security application requirements. And, as a matter of fact, our customers will be able to develop their operating systems much faster.”

TEGRION features Infineon’s unique Integrity Guard 32 hardware security architecture, which greatly simplifies application development. It allows design-for-security conditions that are critical to sustainable success of today’s and tomorrow’s connected applications. Integrity Guard 32 enables higher levels of security without compromising on performance and reliability. It is based on a holistic approach that integrates the system’s processing core, on-chip memories, buses, caches, crypto accelerators and peripheral interfaces into a comprehensive security architecture.

Highly effective error detection/correction codes and a self-checking dual-CPU core protect the system. Power-efficient crypto accelerators enable fast data encryption and digital signatures and other crypto operations while protecting the system from side-channel, fault induction and physical attacks. Integrity Guard 32 pushes the boundaries of hardware security forward, while reducing the total cost of ownership over the entire product lifecycle, thus enabling easier application development with significantly less efforts for protection measures in software.

The first member of the new family, the SLC26P, was released in November 2022 and includes EMVCo certification for payment markets. Over the past six months, this product has experienced a very rapid ramp-up to volume production, driven by customer demand. The first implementation based on a TEGRION security controller, a SECORA Pay payment solution, has demonstrated industry-leading contactless and personalization performance. Based on the new Mastercard 2023 performance guideline with 144-byte keys, a payment card with the SECORA Pay security solution enables contactless transactions within 155 ms – almost halving the expected transaction time (less than 300 ms).

The first TEGRION security controller family, the SLC26P for payment applications, is available now and the portfolio is being continuously expanded. By the end of the year, Infineon plans to address the areas of government identification, transport ticketing as well as eSIM and Secure Element, bringing the benefits of advanced 28 nm technology to more applications.

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Today’s complex system-on-chip (SoC) designs can contain between tens to hundreds of IP blocks. Each IP block may have its own data width and clock frequency and employ one of the standard SoC interface protocols: OCP, APB, AHB, AXI, STBus, and DTL. Connecting all these IPs is a significant challenge.

Functional IP blocks connect to the network-on-chip (NoC) via sockets. In the case of an initiator IP, the socket serializes and packetizes the data generated by the IP, assigns an ID to the packet, and dispatches it into the network. When the packet arrives at its destination IP, the associated socket extracts the data from the packet and transforms it into the protocol required by the IP. A large number of packets can be in flight throughout the network at any given time.

Topological types and target applications

The term topology refers to how the constituent parts of something are interrelated or arranged. In these discussions, the topology of an NoC refers to how the IP nodes are connected.

NoCs are incredibly versatile. As illustrated in the figure below, in addition to an NoC implementation of a crossbar—this is not the same as a traditional crossbar switch implementation—other topologies commonly deployed in today’s SoCs include 1D stars, rings and trees, along with 2D meshes and toruses. More complex structures, including 3D cubes and 4D hypercubes, are also possible but are rarely employed in practice.

High-level representations are shown for common NoC topologies. Source: Arteris

When comparing different NoC topologies, a typical mega metric is the concept of wire cost, which essentially embraces all the expenses, power, area, and congestion associated with the interconnect portion of the NoC. Bearing this in mind, a high-level summary of the various NoC topologies illustrated in the above figure is as follows:

NoC crossbar topology

Advantages:

• Provides a direct and simultaneous connection between all nodes.
• No contention for shared resources.
• High throughput and low latency.

Disadvantages:

• High wire cost in terms of power for larger systems.
• Scalability issues due to the limited number of ports in the switch.

Comparison:

• Lowest latency and highest throughput.
• Highest power and wire costs.

Use cases:

• High-performance computing systems, such as supercomputers or data centers, require low latency and high throughput for transferring large amounts of data.
• High-end graphics processing units (GPUs) and other high-speed processing units require high bandwidth and low latency communication.
• Some commercial interconnect providers offer crossbar interconnects as general-purpose solutions. However, topologies like mesh or tree may be more appropriate for small embedded systems.

Star topology

Advantages:

• Simplicity

Disadvantages:

• Offers only a single point of failure in the central hub or switch—if the hub or switch fails, the entire system will fail.
• The total bandwidth of a star topology is limited by the capacity of the central hub or switch. If the processing elements require more bandwidth than the hub or switch can provide, the system’s performance will be limited.
• While a star topology is scalable to a certain extent, it may become difficult and expensive to scale beyond a certain number of processing elements.
• As messages must pass through the central hub or switch, a star topology may have higher latency than a mesh or torus topology.

Use cases:

• Can be a good choice for small embedded systems or consumer electronics with limited processing elements and low bandwidth requirements. However, it may not be suitable for systems with high bandwidth requirements or where fault tolerance and scalability are critical.

Ring topology

Advantages:

• Low power and wire costs.
• Provides a guaranteed path between nodes.

Disadvantages:

• Low scalability due to the fixed number of nodes in the ring.
• High latency caused by messages needing to traverse the entire ring.

Comparison:

• Lower power and wire cost compared to mesh and torus topologies.
• Higher latency than the mesh and tree topologies.

Use cases:

• Smaller designs with limited numbers of nodes, such as embedded systems or sensor networks.
• Systems in which messages must be delivered in a specific order, such as token rings in real-time systems.

Tree topology

Advantages:

• Scalable with low power and wire costs for larger systems.
• Fault tolerance due to having multiple paths between nodes.

Disadvantages:

• High contention and congestion at the root of the tree.
• Higher latency than mesh topology.

Comparison:

• Lower power and wire costs than crossbar topology.
• Lower latency than ring topology.

Use cases:

• Hierarchical systems include systems with an initiator-target structure or a central processing unit (CPU) with multiple peripheral devices.
• Clustered systems in which nodes are grouped and must communicate with their group leaders.
• Compared to a mesh topology, a tree topology can be more cost-effective and easier for small systems to implement, as they require fewer wires and switches. Tree topology can also be more energy efficient, as data can be routed directly to its destination without passing through multiple nodes.

Mesh topology

Advantages:

• Scalable with low power and wire costs for larger systems.
• Fault tolerant due to having multiple paths between nodes.

Disadvantages:

• High contention and congestion in the middle of the mesh.
• Higher latency than the crossbar topology.

Comparison:

• Lower latency and higher throughput than ring and tree topologies.
• Lower power and wire cost than the crossbar topology.

Use cases:

• Systems with many nodes and moderate communication requirements.
• For consumer electronics or small embedded systems, a mesh topology can be better than a crossbar topology. This is because a mesh topology is generally more cost-effective and simpler to implement than a crossbar topology. It uses fewer wires and switches, making it well-suited for smaller systems with limited resources.
• Multi-core processors where each core is connected to its nearest neighbors for inter-core communication.
• Mesh topologies can be beneficial for large-scale data center networks where scalability and fault tolerance are essential.
• Mesh topologies can also be a good option for AI applications. A mesh topology provides good fault tolerance and scalability and can adapt to different communication patterns and workloads.

Torus topology

Advantages:

• Provides a natural and regular layout for 2D or 3D chip designs.
• High fault tolerance is due to the multiple paths between nodes.
• Low latency and high throughput for small- and medium-sized systems.

Disadvantages:

• High power and wire costs for larger systems.
• More complex implementation compared to other topologies.

Comparison:

• Lower power and wire cost than the crossbar topology.
• Lower latency than the ring topology.
• Higher throughput than the mesh and tree topologies.

Use cases:

• Systems with regular 2D or 3D grid structures, such as graphics processors or video processing units.
• Large-scale systems with high fault-tolerance requirements, such as data centers or cloud computing systems.
• The torus is an alternative topology for AI applications as it provides redundant paths for data transmission and ensures high availability and reliability. The torus topology can also provide scalability, as it can be easily expanded by adding more nodes.

No “one size fits all”

While simple designs may still be satisfied with a single network, complex SoCs small and large will benefit from implementing NoCs with similar or disparate topologies.

Some SoCs employ hierarchical tree structures and multiple separate trees instead of a single tree topology. In some cases, one portion of the chip, such as a machine learning (ML) inference engine, may take advantage of a mesh topology. At the same time, other areas may be better served by one or more different topologies.

The main thing to remember is that each SoC presents unique interconnect challenges. NoCs offer the most powerful and versatile interconnect solutions available. Some SoCs can benefit from a mixture of NoC topologies. Most importantly, there is no one-size-fits-all solution when it comes to NoCs.

Selecting the best NoC topology or mix of topologies for a specific application is not always a simple task. Your IP partner can offer advice on the selection of the best technology for your design and its NoC requirements.

Andy Nightingale, VP of product marketing at Arteris, has over 35 years of experience in the high-tech industry, including 23 years spent on various engineering and product management positions at Arm.

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• Network on chip eases IP connect
• What is the future for Network-on-Chip?
• The network-on-chip interconnect is the SoC
• Arteris spins packet-based network-on-chip IP

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Simplicity and low cost sustain the popularity of passive PWM DAC ripple filters despite their limitations. One of these limitations is a high output impedance caused by the series sum of filter resistance(s) (Rf in Figure 1, one resistor for each cascaded filter RC stage), making overall DAC accuracy very sensitive to output loading. The designers’ recourse, unless they want to resort to active output buffering and thus lose some of that wonderful PWM simplicity and cheapness, is to make Rf as low as practical. 

So, how low is practical and what factors set the limit?

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 A generic passive PWM filter topology with one resistor (Rf) for each cascaded filter RC stage.

Although a ripple filter may comprise multiple stages, the first stage will generally take center stage in the “how low to go” decision, for these reasons:

1. In virtually all (even in multi-stage) ripple filter designs, Rf of later stages (if any) are proportional to the first stage’s Rf. So, when it’s known, they, and therefore the final DAC output impedance, are also known.
2. To a good approximation, the full peak-to-peak V+ PWM waveform amplitude usually appears across the first stage Rf, so that practicality-limiting factors like power and current draw are almost entirely determined by its resistance.  Worst case average power and current draw typically occur at or near 50% PWM duty cycle and are given by:

Imax = V+ / (4Rf + 2Rn + 2Rp)
Pmax = V+2 / (4Rf + 2Rn + 2Rp)

where Rn is the N-channel switch’s on-resistance and Rp is the P-channel switch’s on-resistance.

Suppose we choose 10 mW for maximum filter power dissipation and V+ = 2.5V. Then filter output impedance is given by:

Z10mW = Rf + (Rp + Rn)/2 = 2.5V2 / 10 mW / 4 = 156 Ω

This 156 Ω would be a usefully low and loading-resistant output impedance (capable of holding 8-bit accuracy against 40k load resistance) and is actually similar to that of rail-to-rail buffer op amps when in zero-voltage output saturation. For comparison, consider a representative RRIO op amp (the TLV237x) whose guaranteed minimum output V when sinking 1 mA is 150 mV which converts to an equivalent impedance of:

0.15 V / 0.001 A = 150 Ω.

See Low-level output voltage on page 8: https://www.ti.com/lit/ds/symlink/tlv2374-q1.pdf.

When Z =156 Ω, the ripple filter is almost as good as a buffered output in some circuit states. This is surprising performance for a simple and cheap passive filter. But is it ultimately practical? The arithmetic above implicitly assumes Rn = Rp. What happens if they’re not, as shown in Figure 2’s on resistance (Ron) versus source or drain voltage (V) graph for the sort of switch (TMUX4053) that might be used to generate a precision 2.5 V PWM waveshape? 

Figure 2 On-resistance versus source or drain voltage for the TMUX4053 with an unequal Rp and Rn at 25oC.

At 250C Rp is 77 Ω and Rn is 115 Ω. If we make:

Rf = 156 – (Rp + Rn) / 2 = 60 Ω

now the net resistance that charges the filter capacitor:

= Rf + Rp = 60 + 77 = 137 Ω

is significantly smaller than the resistance that discharges it:

= Rf + Rn = 60 + 115 = 175 Ω

by a symmetry factor of:                       

S = (Rf + Rp) / (Rf + Rn) = 137 / 175 = 0.78.

Unfortunately, while okay for minimizing output impedance, this much up/down resistance asymmetry is a bad thing for DAC integral linearity. Figure 3 shows the effect of S = 0.78 on linearity: A deal-breaking >6% of full-scale deviation from accurate linearity.

Figure 3 Linearity error versus PWM duty where S = 0.78 creates ~6% of integral nonlinearity.

In fact, this is a general result. For any given S, integral nonlinearity of approximately:

INL ~ (1 – S) / 4

can be expected, with deviation from linear going positive for S<1 and negative for S>1.

Therefore, if we want abs(INL) = 2-9 for honest ½ lsb 8-bit linearity, we need:

abs(1 – S) = 4 * 2-9 = 2-7

and for the example considered:

(Rf + Rp) / (Rf + Rn) = 1 – 2-7 = 0.9921875
Rf + Rp = 0.9921875 Rf + 0.9921875 Rn
(1 – 0.9921875) Rf = 0.9921875 Rn – Rp
Rf = 4749 Ω.

Thus, the output impedance must increase by 30-fold to 4.8 kΩ to restore 8-bit linearity, making minimum loading for 8-bit accuracy ~1.2M. Yikes!

But perhaps there’s a simple and cheap solution to even this badly bent linearity problem?

Actually, there is. It consists of a straightforward arithmetic correction:

1. Let Vo = desired DAC output.

Then, instead of setting PWM duty to T = Vo / V+ per usual practice, substitute T* from

2. T* = T / (T + (1 – T) / S)

Then integral linearity will be restored, provided that the value provided for S is accurate. Unfortunately, simply calculating S from typical Rn and Rp numbers taken from the switch datasheet will probably not be accurate enough. It would be preferable (maybe mandatory) to directly measure S for the actual devices used. But how can you measure Rn and Rp in an assembled circuit?

This easy in-circuit method will work with no need to bother trying to measure internal switch resistances:

1. Set PWM duty factor = 0.5 = 50%
2. Read Vo and V+ with a high impedance voltmeter.
3. Then S can be calculated as S = (1 – Vo/V+) / (Vo/V+).

Therefore, with this one-time voltage measurement and simple software-based correction, the minimal output impedance calculated above is compatible with 8-bit DAC linearity and is ultimately practical, after all. 

Moral: Yes, you really can go that low, no op amp required.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Nearly 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Double up on and ease the filtering requirements for PWMs
• Optimizing a simple analog filter for any PWM
• Cancel PWM DAC ripple with analog subtraction but no inverter
• Cancel PWM DAC ripple with analog subtractions

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Announcements of an IP acquisition deal and a substantial funding round for an analog IP reuse specialist last week underscore the critical importance of semiconductor IP at a time when more functionality is integrated into a single chip. High-quality IP reduces risk and enables chip designers to speed time-to-market.

On July 20, Thalia, an analog IP reuse specialist, announced it has secured a $2.7 million investment for its next phase of growth. Thalia claims that its proven IP-reuse solution enables system-on-chip (SoC) developers to quickly and efficiently migrate existing IP designs into the sub-20-nm nodes.

Figure 1 Thalia’s AMALIA IP platform claims to offer cost and time efficiency benefits in migrating SoC designs to new wafer fabs and process nodes.

The UK-based IP supplier also claims that its AMALIA platform has been validated on over 50 IPs, ranging from RF to baseband and power management IC (PMIC) to PLL and analog-to-digital converter (ADC). And many of these IPs are already in commercial use.

On the same day, Cadence Design Systems announced that it’s acquiring PHY IP assets of Rambus. That encompasses SerDes and memory interface PHY IPs, critical in artificial intelligence (AI), CPU architectures, data center and hyperscale applications, and networking designs. Additionally, Cadence will get hold of experienced PHY engineering teams in the United States, India, and Canada.

On the other hand, Rambus will retain its digital IP business, including memory and interface controllers and security IP. According to Sean Fan, senior VP and chief operating officer at Rambus, the company will increase its focus on AI and data center markets, which are driving ever-increasing demand for memory and security. “Rambus will expand the roadmap of novel memory solutions to support the continued evolution of the data center and AI.”

Figure 2 Cadence is steadily growing its IP offerings across vertical markets.

Here, it’s worth mentioning similar IP acquisitions that Cadence’s archrival Synopsys made a couple of years ago. In early 2020, Synopsys acquired certain IP assets of Invecas to broaden its DesignWare IP portfolio. That included logic library, general purpose I/O, embedded memory, interface, and analog IP. And Invecas retained its HDMI IP and ASIC design solutions businesses.

A couple of months earlier, Synopsys bolstered the DesignWare IP portfolio for embedded memory by acquiring eSilicon’s ternary content addressable memory (TCAM) technology and multi-port memory compilers as well as its interface IP portfolio with high-bandwidth interface (HBI) IP. The move was aimed to better serve design requirements in growing markets such as AI and cloud computing.

That clearly shows IP building blocks are steadily gaining prominence in the semiconductor design and manufacturing value chain. Especially when increasingly complex SoCs require a broad range of IPs to address stringent performance, power, and area requirements of advanced applications. Semiconductor design talent is another factor driving these acquisitions.

As Ashwin Kumaraswarmy of Mercia Ventures puts it, semiconductor chip design is a manual and painstaking process and skilled engineering teams are rare. Mercia Ventures is a major investor in Thalia.

Related Content

• IP business is still seeking to define itself
• Rambus: The making of an interface IP powerhouse
• Analog IP: Why silicon-proven is not what you think
• How formal verification saves time in digital IP design
• What’s new in analog IP? Digitally wrapped subsystems

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CynLr Technology is a tech company dealing in deep-tech robotics and cybernetics. They enable robots to become intuitive and capable of dynamic object manipulation with minimal training effort. CynLr has developed a visual object intelligence platform that interfaces with robotic arms to achieve the ‘Holy Grail of Robotics’ – Universal Object Manipulation. This enables CynLr-powered arms to pick up unrecognised objects without recalibrating hardware and even works with mirror-finished objects (a traditionally hard obstacle for visual intelligence).

To know more about robotics and the company, Sakshi Jain, Sr. Sub Editor-ELE Times had an opportunity to interact with Nikhil Ramaswamy, Co-Founder & CEO and Gokul NA, Founder – Design, Product and Brand at CynLr Technology. He talked about robots and their ability to mimic the intuitiveness and range of the human hand. Excerpts.

Nikhil & Gokul: Today, most modern approaches in AI and machine vision technology utilised in robotics heavily depend on either presenting an object to a robotic arm in a predetermined manner or by predicting object positions based on static images, regardless of whether they are in 3D or any other format. However, this approach presents significant challenges since the object’s orientation and lighting conditions can greatly alter its colour and geometric shape as perceived by the camera. This becomes even more complicated when dealing with metal objects that have a mirror finish. As a result, traditional AI methods that rely on colour and shape for object identification lack universality. The intuitiveness of vision and object interaction in human beings is taken for granted. Most tasks which are innate for human beings are so far difficult to replicate in automation systems even in extremely controlled environments.

At CynLr, we work to bring intuitiveness to machines, the key to which lies with machine vision being as close as possible to human vision. Of course, in comparing it to human beings we are competing against millions of years. However, we have been able to decipher the fundamental layers of human and animal vision to create the foundations of our visual object intelligence technology. We use cutting-edge techniques such as Auto-Focus Liquid Lens Optics, Optical Convergence, Temporal Imaging, Hierarchical Depth Mapping, and Force-Correlated Visual Mapping in our hardware and algorithms. These AI and Machine Learning algorithms enable robotic arms to perceive and generate rich visual representations, allowing them to manipulate and handle objects based on any environment.

Currently, the manufacturing industry faces challenges in automation for products with shorter life cycles. A change in model or variant means an overhaul of the entire automated line as automation is part specific. CynLr’s technology enables robots to become intuitive and capable of dynamic object manipulation with minimal training effort. The idea is to make one line capable of handling varied objects freeing the automation industry from part-specific solutions only. Whether it’s a packet of Lays chips, a metal part, or a mirrored finish spoon, the same robot can handle them all. These robots are future-proof and capable of performing a wide range of tasks. (You can refer to our demo videos – Untrained Dynamic Tracking & Grasping of Random Objects and Oriented Grasps and Picks of Untrained Random Objects).

Nikhil & Gokul: CynLr’s one of the major achievements is passing the Litmus paper test for AI – recognition and isolation of mirror-finished/reflective objects. Our visual robots can recognize and isolate mirror-finished objects without any training, under varying lighting conditions. Our highly dynamic and adaptive product eliminates the need for customised solutions, sparing our customers from dealing with multiple technologies and complex engineering.

We have vital interests in collaboration with the US and EU. We have currently begun engagements for reference designing our tech stack to build advanced assembly automation with two of the five largest automotive car manufacturers globally and a large component supplier from Europe. We are also entering new markets like the industrial kitchen and Advanced Driver Assistance Systems (ADAS) use cases.

We are strategically addressing the global challenge of part-mating and assembly automation by leveraging our advanced visual intelligence technology. This cutting-edge approach combines computer vision, machine learning, and robotics to tackle the complexity of automating intricate part-mating and assembly processes, which have historically been demanding to automate. Our visual intelligence technology allows robots to accurately perceive and interpret spatial relationships between parts, enabling precise alignment and assembly.

We go beyond visual perception alone. As a deep-tech company, we also recognize the successful automation of part-mating and assembly requires additional elements such as tactile feedback and knowledge of how to manipulate different components. By integrating tactile sensing capabilities and leveraging our expertise in robotics, we aim to create robots that can not only guide the assembly process visually but also interact with parts in a manner that emulates human-like dexterity and precision.

Our ultimate objective is to offer a holistic solution for part-mating and assembly automation, overcoming challenges related to complex spatial relationships, part geometry variations, and the need for meticulous manipulation. By automating these processes, we intend to empower manufacturers to achieve remarkable gains in efficiency, cost reduction, and increased production.

We also collaborate closely with global customers and run pilots across different regions, including the US, Germany, and India. We aim to further validate and refine our technology to find real-world applications.

Our new mission in automation revolves around revolutionising the manufacturing industry through advanced robotics and artificial intelligence technologies. Below are some highlights of the same:

1. Automation Transformation: We aim to spearhead a transformative shift in manufacturing by automating processes that were previously considered non-automatable. Our mission is to enable robots to perform complex tasks with precision, efficiency, and adaptability.
2. Addressing Industry Challenges: We are committed to tackling the challenges faced by manufacturers in part-mating, assembly, and other intricate processes. We aim to overcome the limitations of traditional automation methods by leveraging our expertise in visual intelligence, tactile feedback, and a comprehensive understanding of fundamental sciences.
3. Universal Factories: CynLr envisions the establishment of universal factories, where robots can seamlessly adapt to different tasks and products without the need for specialised infrastructure or extensive reconfiguration. This approach simplifies factory operations, enhances versatility, and optimises logistics.
4. Reduction of Manual Labor: With our visual intelligence technology, CynLr seeks to automate labour-intensive processes, reducing the reliance on manual labour and streamlining production lines. By automating tasks such as part-mating and assembly, we want to enhance productivity, minimise errors, and free up human workers for more strategic and value-added activities.
5. Global Impact: Our mission extends beyond regional boundaries. By collaborating with leading OEM players in Europe and the US, and aiming to expand our business in India, we strive to have a global impact, transforming manufacturing industries worldwide.

Overall, our new mission in automation revolves around pushing the boundaries of what is considered automatable, simplifying factory operations, reducing manual labour, and driving innovation in the manufacturing industry on a global scale.

Nikhil & Gokul: We feel that the Indian market is still premature for our solution. We need a space where customers can actively engage, invest their resources, and transform our technology into a practical and functional solution. This is precisely why we have constructed one of the most densely populated robotics labs focused on visual intelligence.

Although we possess the technological capabilities, without a viable customer solution, any technology will remain underdeveloped. Therefore, a comprehensive ecosystem is needed for the success of a foundational technology like ours. We further aim to engage with customers, channel partners and academic institutions who can further build on our machine vision stack and come up with viable solutions.

Nikhil & Gokul: Vision technology is severely limited in robotics today. The intelligence and eyes needed for robots to adjust to different shapes, and variations and adapt accordingly are simply not there. So, we saw an opportunity to enable that technology by working with the problem closely.

Our visual intelligence platform helps robotic arms to adapt to various shapes, orientations and weights of objects in front of it. We have developed a technology that can differentiate sight from vision and begins its algorithms from its HW using Auto-Focus Liquid Lens Optics, Optical Convergence, Temporal Imaging, Hierarchical Depth Mapping, and Force-Correlated Visual Mapping. It enables the robots with human-like vision and versatility to grasp even Mirror-Finished objects without any pre-training (a feat that current ML systems can’t achieve). CynLr’s visual robots can comprehend the features of an object and re-orient them based on the requirements. The AI & Machine Learning algorithms help robotic arms process the task even in an amorphous setting and align them in the best way possible.

Nikhil & Gokul: HW & SW Vision Platform is instrumental in building machines as it provides them perception, understanding, intelligent decision-making capabilities, automation, enhanced safety, and adaptability. By incorporating vision technologies, machines can effectively interact with their surroundings, analyze visual data, and make informed decisions, ultimately improving efficiency and expanding the possibilities of machine applications.

The HW component of the platform typically involves specialized hardware devices such as cameras, sensors, and image processors. These components capture visual data from the machine’s surroundings, convert it into digital information, and process it to extract relevant features and patterns. On the other hand, the SW aspect of the platform involves the software algorithms and frameworks designed to analyze and interpret visual data. These algorithms perform tasks such as image recognition, object detection, segmentation, and tracking, enabling the machine to comprehend its surroundings and make intelligent decisions based on that information.

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Closed fuse holders are a fine thing: the fuse is well protected and yet easy to replace. According to IEC-60127-6, however, the limit was previously 16 A. Thanks to an extension of this standard initiated by SCHURTER, this is now history. The new FXP fuse holder for 6.3×32 fuse links is designed for rated currents up to 25 A (IEC) or 45 A (UL).

The new SCHURTER FXP fuse holder for 6.3×32 fuses has been explicitly designed for highpower applications. Its nominal data is an impressive proof: according to IEC, the rating is 25A @ 500VAC (8 watts) or UL 45A @ 600VAC/VDC. This makes it the first fuse holder that already fulfils the upcoming extension of the IEC standard 60127-6.

What makes the FXP particularly interesting is its high current capability in use at elevated temperatures. The IEC and UL ratings are always based on normal conditions. In the case of a fuse holder, this means +23 °C (IEC) or +25 °C (UL). If a fuse holder is used above these temperatures, its capacity decreases with increasing temperature. The FXP fuse holder still achieves a maximum power of 4 watts even at 50°C ambient temperature. Today’s fuse holders of similar size only achieve such values at room temperature. This circumstance creates safety reserves at increased operating temperatures.

Thanks to snap-in mounting technology, the FXP is ready for use in no time. With its IP40 protection class, it is primarily designed for indoor applications. A solder connection is available on the connection side.

The post The new FXP Fuse holder for very high power appeared first on ELE Times.

Pasternack, an Infinite Electronics brand and a leading provider of RF, microwave and millimeter-wave products, has just launched its premier line of commercial marine-grade ship/boat RF antennas, specifically designed for the harshest marine environments.

Offering high performance for sea-bound communications, the freshly released product range is a beacon for ship-to-ship correspondence, distress signal transmission and harbor chatter.

Pasternack’s cutting-edge marine antennas operate within the vital marine frequency band of 156 to 163 MHz and CB-27 MHz, 10m-HAM, offering clear, continuous connectivity on the open sea.

With their versatile mounting options, integrating these antennas into any sea vessel’s design is a breeze. The trio of mount types are designed for the most effective marine use, providing outstanding flexibility.

Pasternack’s marine-grade antennas boast top-tier features like weather resistance, rated IP67 for water intrusion, ensuring enduring resilience. With an array of antenna lengths to choose from, signal performance can be customized to suit individual needs.

The GPS capabilities include L1 band and multiband capacities and a gain of 28 dBi, promising dependable navigation. Constructed with top-grade stainless steel or fiberglass materials, these antennas promise lasting durability and unparalleled performance.

“With the launch of our new commercial marine-grade antennas, we are elevating marine communications to new heights. These antennas not only offer unmatched connectivity within the vital marine frequency band but provide unprecedented versatility for easy integration into any sea vessel’s design,” said Kevin Hietpas, Product Line Manager.

The post Pasternack Launches Commercial Marine-Grade Ship/Boat RF Antennas appeared first on ELE Times.

The global automotive control cable market in 2022 was US$ 2.5 billion and is estimated to be US$ 3.6 billion in 2023. Future Market Insights has mentioned in its reports that the automotive control cable market is predicted to expand at a CAGR of 7.37% between 2023 and 2033, totaling around US$ 7.33 billion by 2033.

New vehicle models are being launched, where the anonymous rise in vehicles, has been the leading market influencing the growth of the market. Further, gains are mainly driven by the boost in demand for automotive vehicles, as the government mandates regarding anti-lock braking systems for passenger and commercial vehicles are, therefore, identified as remaining the key growth of the determinants for the market.

FMI also offers exclusive insights into how companies actively operating in the automotive control cable landscape. It is further focusing on competitive strengths and on improvement of technology, toward the transformation of the auto ancillary industry, since it is a low-volume and highly fragmented sector.

• Demand in the global automotive control cable market is expected to create an absolute dollar opportunity of nearly US$ 3.4 billion through 2029, expanding at a CAGR of 4.6% over the forecast period from 2022 to 2029.
• The global automotive control cable market expanded at a CAGR of 6.24% between 2018 and 2022.
• Japan is projected to account for the maximum sales in the automotive control cable market with a CAGR of 9.8%. India is said to dominate the market after China with a market share of 9.12%.

• Germany is expected to thrive at a significant pace at a value of 16.3%, assisting Europe’s market to hold around 27.2% of the total revenue share through 2022 whereas the United Kingdom expands at a CAGR of 7.82%.
• North America holds a value share of 38.3%, whereas the United States holds a key part with a value share of 32%.
• Sales of clutch cable might rise at a significant pace in the automotive control cable market with a market share of 49.8%.
• The polyethylene segment is projected to account for a significant share of the market with a market share of 60.2%.
• The compact car segment is anticipated to continue dominating the automotive control cable market at a value share of 55.2%.
• (OEM) segment is projected to hold the dominant share in the global market with a value share of 44.23%.

“Increasing in response to a substantial rise in road accidents, and government initiatives for enhancing overall safety is one of the major implementations of the automotive control cables market” – Future Market Insights analyst.

• In April 2023, Ficosa, a leading global company dedicated to the research, development, production, and marketing of advanced vision, safety, and efficiency solutions for the automotive industry, plans to sell more than 7 million cameras throughout 2023

In November 2022, DURA Automotive Systems announced the official ground-breaking of a state-of-the-art manufacturing facility in Muscle Shoals, Alabama. The latest addition to a family of 31 worldwide sites will be home to DURA’s first lightweight structures manufacturing facility in North America.

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The market for deception technology is expected to surge to US$ 2 billion in value by 2023. It is anticipated to increase to US$ 6.7 billion by 2033, representing a CAGR of 12.6% from 2023 to 2033. The market might offer a US$ 4.7 billion absolute dollar potential during the same time frame.

Security tactics have had to change due to the constantly evolving nature of cyber threats. Antivirus software and firewalls, once sufficient for protection, are no longer effective against modern, sophisticated threats.

Deception technology provides a proactive security mechanism by setting up a network of deceptive traps and decoys that detect and divert intruders. This novel strategy is expected to add an extra degree of protection for enterprises. As a result, it would be a desirable approach to counter new cyber threats.

The ability of an organization to identify and react is improved by deception technology. Organizations can divert attackers away from vital assets by using realistic decoys. Additionally, they can learn crucial information about their strategies, methods, and objectives.

Early detection enables quick response and correction, reducing the potential harm cyberattack brings. The ability to proactively identify risks and take appropriate action is a key factor driving demand for deception technologies.

Organizations might also be in danger from insider threats. Hence, it is essential to put precautions to lessen this risk. Deception technology can be important in combating insider threats by constructing decoys and traps that are only visible to insiders.

The strategy enables businesses to spot dishonest insiders or compromised accounts and take the necessary countermeasures. Deception technology will offer enterprises improved security and peace of mind by giving them a proactive way to identify and stop internal threats.

Demand for deception technologies would also be significantly influenced by compliance and regulatory needs. Strict data protection and security laws apply to several sectors, including healthcare, finance, and government.

Deception technology offers an advanced security solution that goes beyond fundamental compliance measures, assisting enterprises in meeting these criteria. Organizations might be sure to adhere to legal requirements and avoid penalties by exhibiting proactive security measures.

Corporations might also find deception technology to be a cost-effective security measure. Without making substantial investments in extra hardware, businesses can increase security by strategically installing decoys and traps. This makes the cost of developing deception technologies a viable investment.

Due to the sensitivity or importance of their intellectual property, certain sectors, such as defense, critical infrastructure, and high-tech manufacturing, have specific security requirements. Deception technology provides specialized answers to handle these particular challenges. Hence, it might offer specialized decoys and traps corresponding to threats and attack vectors unique to a given sector.

• China’s deception technology industry is projected to witness a CAGR of 5% from 2023 to 2033.
• The United States deception technology industry witnessed a CAGR of 1% in the historical period.
• The United Kingdom’s deception technology industry is anticipated to surpass a valuation of US$ 264 million by 2033.
• By offering, the solution segment displayed a CAGR of 0% in the historical period.
• By deception stack, the network security segment is predicted to witness a 2% CAGR from 2023 to 2033.

The deception technology market’s competitive environment is dynamic and ever changing. There are a variety of established businesses, new start-ups, and providers of specialized solutions in the market.

Several well-known businesses have emerged as market leaders in the field of deception technology. These businesses have a significant market presence, a sizable customer base, and a broad portfolio of deception technologies.

They frequently have a history of effective deployments and collaborations with other cybersecurity firms. To remain ahead of new threats and continuously enhance their products, market leaders often make significant investments in research & development.

The deception technology sector is heavily reliant on collaboration and strategic alliances. To increase their reach, businesses frequently form agreements with other cybersecurity vendors, managed security service providers, or system integrators.

They also want to increase the number of clients they serve and provide all-inclusive services. Through the harnessing of synergies and the pooling of capabilities, partnerships can increase market competitiveness.

The Cybersecurity & Infrastructure Security Agency (CISA), a Department of Homeland Security division, announced in April 2022 that its FedRamp Ready ShadowPlex platform had been included. Acalvio Technologies is a pioneer in the field of cyber deception. The business would be able to use and acquire cutting-edge deception technology with the addition of this platform. Additionally, the platform would aid them in thwarting sophisticated foes.

The post Uncovering the Lucrative Potential of the Global Deception Technology Market with an Estimated 12.6% CAGR by 2033 – Future Market Insights appeared first on ELE Times.

With advanced materials a critical enabler of semiconductor growth applications, Strategic Materials Conference (SMC 2023) will gather top executives and leaders from every segment of semiconductor manufacturing for insights into the latest developments in advanced materials October 2-4, 2023 at the Holiday Inn in San Jose, Calif., a change in venue from the DoubleTree by Hilton in San Jose.

SMC is the premier event focused on drivers of advanced materials, highlighting opportunities for key materials across the electronics supply chain in growth markets including computing and data storage, wireless communication, automotive, consumer and industrial electronics.

Themed Materials Readiness for the Next Semiconductor Super Cycle, SMC 2023 will feature the following sessions:

• Session 1: Market and Geopolitical Trends
• Session 2: Future Technology
• Session 3: Materials Driving Performance Session
• Session 4: More than Moore
• Session 5: Sustainability Session
• Session 6: Executive Panel: Outlook from Semiconductor Industry Executives

• Amkor Technology
• Analog Devices
• Applied Materials
• AT&S
• CEA
• DuPont
• Eastman Chemical Company
• Entegris
• GlobalFoundries
• Intel Corporation
• JSR Corporation
• Lam Research
• Macquarie
• Micron
• Omdia
• Prismark Partners
• Purdue University
• SCREEN SPE US
• SEMI
• Tokyo Electron (TEL)
• TSMC

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