Microelectronics world news

AOS offers the AOZ71137QI, a 3-rail, 7-phase controller that complies with Intel Mobile Voltage Positioning (IMVP) 8, 9, 9.1, and 9.2 specifications. Together with an AOS power stage, the hybrid digital controller offers a Vcore power management system for Intel Meteor Lake and Arrow Lake CPUs, as well as other notebook CPUs.

The step-down controller supports four separate SVID domains: up to four phases for the core voltage, two phases for graphics, and one phase for the auxiliary output. It also includes the Psys domain’s reporting functions. The part operates in a variable frequency hysteretic peak current mode, combined with a proprietary phase current sensing scheme. This design allows for fast transient response and optimal current balance for both transient and DC loads.

AOS offers a portfolio of DrMOS and Smart Power Stages (SPS) for use with the AOZ71137QI controller. According to the company, DrMOS devices meet Vcore power requirements with robustness, featuring a 30-V breakdown voltage and UIS testing. SPS devices integrate current and temperature monitoring for accurate reporting. The AOZ71137QI also works with industry-standard DrMOS and SPS components.

The AOZ71137QI controller is available now in production quantities, with lead times of 12 to 16 weeks. Prices start at $2.40 each in lots of 1000 units.

AOZ71137QI product page

Alpha & Omega Semiconductor 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Fabless semiconductor firm CGD announced two packages for its ICeGaN family of GaN power ICs that enhance thermal performance. Both are variants of the dual-flat no-leads (DFN) package and will debut at this month’s PCIM Europe exhibition.

The DHDFN-9-1, or dual heat-spreader DFN, is a thin 10×10-mm package featuring dual-side cooling. Wettable flanks enable more reliable optical inspection. This package supports bottom-side, top-side, and dual-side cooling, outperforming the TOLT package, particularly in top-side and dual-side cooled configurations. Additionally, a dual-gate pinout simplifies PCB layout and paralleling, enabling applications up to 6 kW.

The BHDFN-9-1, or bottom heat-spreader DFN, provides bottom-side cooling and wettable flanks. According to CGD, this package has a thermal resistance of 0.28 K/W, matching or exceeding other leading devices. Despite being smaller than a TOLL package, the 10×10-mm BHDFN package shares a similar footprint. This allows a common layout with TOLL-packaged GaN power ICs, simplifying use and evaluation.

ICeGaN power transistors operate with standard silicon gate drivers and do not require negative voltages for shutdown. They can be used in servers, data centers, inverters, motor drives, and other industrial applications.

Cambridge GaN Devices 

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Mitsubishi will be sampling its MGFS52G38MB GaN power amplifier module (PAM) capable of supplying 16 W of average output power starting this month. The device can be used in 32T32R antenna configurations to reduce the manufacturing cost and power consumption of 5G massive MIMO (mMIMO) base stations.

In September 2023, Mitsubishi introduced a GaN PAM offering 8 W (39 dBm) of average output power across a frequency range of 3.4 GHz to 3.8 GHz, suitable for 64T64R mMIMO antennas. The new GaN PAM increases average output power to 16 W (42 dBm) over a frequency range of 3.3 GHz to 3.8 GHz, targeting 32T32R mMIMO antennas. This advancement extends the coverage of 5G mMIMO base stations, while minimizing the number of required PAMs.

Key specifications for the GaN power amplifier module include:

Mitsubishi will exhibit the 16-W GaN PAM at this month’s IEEE MTT-S International Microwave Symposium. A datasheet was not available at the time of this announcement.

Mitsubishi Electric

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Microchip’s TimeProvider XT extension system migrates E1, T1, or CC synchronization outputs to a fully redundant TimeProvider 4100 grandmaster. The accessory device allows operators to replace existing SONET/SDH frequency equipment, while adding timing and phase, essential for 5G networks.

Each TimeProvider XT shelf is configured with two distribution modules and two plug-in modules. Together, they provide 40 redundant and individually programmable outputs with synchronization that meets ITU-T G.823 requirements for the control of wander and jitter. Operators can scale up to 200 fully redundant T1/E1/CC communication outputs by connecting five XT shelves to a pair of grandmasters. All configuration, status monitoring, and alarm reporting is done through the grandmaster.

TimeProvider is compatible with DCD, SSU 2000, TSG-3800, and TimeHub systems’ wire-wrap and output panels, eliminating the need to rewire network elements. A composite clock (CC) input allows for live in-service CC phase cutovers, typically performed during maintenance windows to ensure continuous network synchronization.

The TimeProvider XT extension system is available now for purchase. Contact a Microchip sales representative or authorized distributor.

TimeProvider XT product page

Microchip Technology 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

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Infineon Technologies AG introduces the 600 V CoolMOS 8 high voltage superjunction (SJ) MOSFET product family. The devices combine the best features of the 600 V CoolMOS 7 MOSFET series and are the successors to the P7, PFD7, C7, CFD7, G7 and S7 product families. The new superjunction MOSFETs enable cost-effective Si-based solutions that enhance Infineon’s wide-bandgap offering. They are equipped with an integrated fast body diode, making them suitable for a wide range of applications such as server and industrial switched-mode power supply units (SMPS), EV chargers, and micro-solar.

The components come in SMD QDPAK, TOLL and ThinTOLL 8 x 8 packages, which simplifies designs and reduces assembly costs. At 10 V, the 600 V CoolMOS 8 SJ MOSFETs offer 18 percent lower gate charge (Qg) than the CFD7 and 33 percent lower than the P7. At 400 V, the product family offers a 50 percent lower output capacitance COSS than the CFD7 and the P7. In addition, the turn-off losses (Eoss) have been reduced by 12 percent compared to the CFD7 and the P7 and the reverse recovery charge (Qrr) is 3 percent lower compared to the CFD7. Furthermore, the devices offer the lowest reverse recovery time (trr) on the market and the thermal performance has been improved by 14 to 42 percent compared to the previous generation.

With these features, the devices offer high efficiency and reliability in soft-switching topologies such as LLC and ZVS phase-shift full-bridge. They also provide excellent performance levels in PFC, TTF and other hard-switching topologies. Due to their optimized RDS(on), the devices offer higher power density, allowing products in a Si-based super junction (SJ) technology to be reduced to a single-digit value of 7 mΩ.

Infineon will showcase the 600 V CoolMOS 8 SJ MOSFETs at the Infineon booth (Hall 7 / Booth 470) at PCIM 2024 in Nuremberg.

Availability

Samples of the 600 V CoolMOS 8 SJ MOSFETs are now available. More information is available at www.infineon.com/coolmos8.

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Cambridge GaN Devices (CGD) has launched two new packages for their ICeGaN family of GaN power ICs. These new packages are designed to enhance thermal performance and simplify inspection, targeting applications in data centres, inverters, and more. Variants of the well-proven DFN style, both packages are noted for their extreme ruggedness and reliability. This development supports CGD’s mission to make greener electronics possible through innovative semiconductor technology.

1. DHDFN-9-1 (Dual Heat-spreader DFN)

Design: Thin, dual-side cooled package with a 10×10 mm footprint.

Features:

• Wettable flanks for simplified optical inspection.
• Low thermal resistance (Rth(JC).
• Flexible cooling options: bottom-side, top-side, and dual-side.
• Dual-gate pinout for optimal PCB layout and easy paralleling.

Advantages: Outperforms the TOLT package in top-side and dual-side cooling configurations, supporting applications up to 6 kW.

2. BHDFN-9-1 (Bottom Heat-spreader DFN)

Design: Bottom-side cooled package with a 10×10 mm footprint.

Features:

• Wettable flanks for easy inspection.
• Thermal resistance of 0.28 K/W, matching or exceeding other leading devices.
• Similar footprint to the TOLL package, allowing for a common layout and ease of evaluation.

Benefits of Improved Thermal Resistance

1. Increased Power Output: More power at the same RDS(on).
2. Lower Operating Temperatures: Devices run cooler for the same power, reducing heatsinking needs and system costs.
3. Enhanced Reliability: Lower temperatures lead to higher reliability and longer lifetimes.
4. Cost Efficiency: Designers can use lower-cost parts with higher RDS(on) while achieving the required power output.

These advancements in packaging technology enable the GaN power ICs to offer superior performance, reliability, and cost-effectiveness, contributing to greener and more efficient electronic solutions.

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Intel has adopted a new SoC design that triples the size and quadruples the performance of its AI accelerator.

With the help of a case study, we examine how adopting NoC technology can significantly improve the process of updating existing chip designs.

Fabless firm Cambridge GaN Devices Ltd (CGD) — which was spun out of the University of Cambridge in 2016 to design, develop and commercialize power transistors and ICs that use GaN-on-silicon substrates — is partnering with Qorvo Inc of Greensboro, NC, USA (which provides core technologies and RF solutions for mobile, infrastructure and defense applications) to develop a reference design and evaluation kit (EVK) that showcases GaN for motor control applications. CGD aims to speed the use of GaN power ICs in BLDC (brushless DC) and PMSM (permanent-magnet synchronous motor) applications, resulting in higher-power, highly efficient, compact and reliable systems. Qorvo is building an EVK for its PAC5556A motor/control IC that is powered by CGD’s ICeGaN (IC-enhanced GaN) technology...

Software engineers developing artificial intelligence (AI) models using standard frameworks such as Keras, PyTorch, and TensorFlow are usually not well-equipped to translate those models into silicon-based implementations. A new synthesizable tool claims to solve this design conundrum with faster and more power-efficient execution compared to standard AI processors.

Most machine learning (ML) experts working on AI frameworks—Keras, PyTorch, and TensorFlow—are not comfortable with synthesizable C++, Verilog, or VHDL. As a result, there has been no easy path for ML experts to accelerate their applications in a right-sized ASIC or system-on-chip (SoC) implementation.

Enter hls4ml, an open-source initiative intended to help bridge this gap by generating C++ from a neural network described in AI frameworks such as Keras, PyTorch, and TensorFlow. The C++ can then be deployed for an FPGA, ASIC or SoC implementation.

Siemens EDA joined hands with Fermilab, a U.S. Department of Energy laboratory, and other leading contributors to hls4ml while tying up its Catapult software for high-level synthesis (HLS) with hls4ml, an open-source package for ML hardware acceleration. The outcome of this collaboration was Catapult AI NN software for high-level synthesis of neural network accelerators on ASICs and SoCs.

Figure 1 Here is a typical workflow to translate an ML model into an FPGA or ASIC implementation using hls4ml, an open-source codesign workflow to empower ML designs. Source: CERN

Catapult AI NN extends the capabilities of hls4ml to ASIC and SoC design by offering a dedicated library of specialized C++ machine learning functions tailored to ASIC design. This allows designers to optimize power, performance, and area (PPA) by making latency and resource trade-offs across alternative implementations from the C++ code.

Design engineers can also evaluate the impact of different neural net designs to determine the best neural network structure for their hardware. Catapult AI NN starts with a neural network description from an AI framework, converts it into C++ and synthesizes it into an RTL accelerator in Verilog or VHDL for implementation in silicon.

Figure 2 Catapult AI NN provides automation of Python-to-RTL for neural network (NN) hardware designs. Source: Siemens EDA

“The handoff process and manual conversion of a neural network model into a hardware implementation is very inefficient, time-consuming and error-prone, especially when it comes to creating and verifying variants of a hardware accelerator tailored to specific performance, power, and area,” said Mo Movahed, VP and GM for high-level design, verification and power at Siemens Digital Industries Software.

This new tool enables scientists and AI experts to leverage industry-standard AI frameworks for neural network model design and synthesize these models into hardware designs optimized for PPA. According to Movahed, this opens a whole new realm of possibilities for AI/ML software engineers.

Catapult AI NN allows developers to automate and implement their neural network models for optimal PPA concurrently during the software development process,” he added. Panagiotis Spentzouris, associate lab director for emerging technologies at Fermilab, acknowledges the value proposition of this synthesis framework in AI designs.

“Catapult AI NN leverages the expertise of our scientists and AI experts without requiring them to become ASIC designers,” he said. That’s especially critical when A/ML tasks migrate from the data center to edge applications spanning consumer appliances to medical devices. Here, the right-sized AI hardware is crucial to minimize power consumption, lower cost, and maximize end-product differentiation.

Related Content

• Key technologies push AI to the edge
• C++ runs hardware/software designs
• Adapting the Microcontroller for AI in the Endpoint
• Edge AI accelerators are just sand without future-ready software
• Don’t Be Misled By “Accuracy” — 3 Insights For More Useful AI Models

The post Synthesis framework simplifies silicon implementation for AI models appeared first on EDN.

The VIAVI Automated Lab-as-a-Service for Open RAN (VALOR) has come out with the O-RU conformance, performance, security, and subsystem interoperability tests based on O-RAN ALLIANCE specifications. The services are well-suited for radio manufacturers aiming to participate in the National Telecommunications and Information Administration (NTIA) Public Wireless Supply Chain Innovation Fund (PWSCIF) Second Notice of Funding Opportunity (NOFO 2), which focuses on Open Radio Unit (O-RU) Commercialization and Innovation.

For radio manufacturers, VALOR offers an on-demand test suite, including O-RU conformance, performance, security, and interoperability testing. Additionally, VALOR provides Massive MIMO and beamforming over-the-air (OTA) validation, including system-level Massive MIMO performance testing for up to 16 parallel spatial layers, utilizing a full set of golden O-RAN compliant O-RUs, O-DUs, and O-CUs provided by several reputable partners and a large RF anechoic chamber.

VALOR, made possible by a $21.7 million grant from the first PWSCIF Notice of Funding Opportunity, provides fully automated, open, and impartial testing and integration for Open RAN. It provides a pathway to certification in the U.S. for new entrants, startups, and academia. Access to VALOR is free for academic institutions and NTIA co-grantees, subject to availability, enabling O-RU vendors to meet the comprehensive performance requirements needed by mobile network operators (MNOs) to deploy their equipment at scale as required by NOFO 2.

VALOR is based on VIAVI’s industry-leading NITRO Wireless Open RAN Test Suite, including the TM500 and TeraVM test platforms. The TM500 O-RU Tester enhances legacy conformance test tools with its Direct Performance Test capabilities, such as uplink and downlink data performance and capacity testing.

VIAVI also offers Test-as-a-Service (TaaS) supporting short-term and time-sensitive 5G and Open RAN projects. The TaaS offering provides a complementary alternative to handle peaks in lab demand for major NEMs and CSPs with customers’ in-house testing approach.

VIAVI Solutions has been directly involved in testing, assuring, and securing the largest communications networks around the globe for over 100 years, validating network products for all Tier-1 network equipment manufacturers.

Dr. Sameh Yamany, VIAVI’s Chief Technology Officer, expressed gratitude for the NTIA’s trust in awarding them the grant for VALOR, making Open RAN testing accessible, affordable, and sustainable for the entire ecosystem. He looks forward to partnering across the industry to realize the vision of Open Radio Commercialization and Innovation.

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Given their generally low cost, small size, robust construction, accuracy, versatility, and sensitivity, it’s no wonder that basic negative temperature coefficient (NTC) thermistors rate among the most popular temperature sensors available. However, their temperature response function is highly nonlinear (literally exponential), making excitation and signal digitization and processing interesting design exercises.

The typical NTC thermistor’s datasheet (e.g., Molex 2152723605) summarizes thermo-electric properties with four parameters (Equations 1 through 5), shown in Figure 1 (numbers borrowed from 2152723605 data):

To = rated/calibration temperature (25°C = 298.15 K)          (1)
Ro = resistance at To (10k ±1%)                                               (2)
b = beta (3892 K)                                                                         (3)
Dissipation (self-heating) factor (1.5 mW/°C)                       (4)

Wow the engineering world with your unique design: Design Ideas Submission Guide

Then thermistor resistance (Rt) as a function of temperature (T) in Kelvin is predicted by:

Rt = Ro exp(b(T-1 – To-1))                                                           (5)

Applying the classic KISS principle, we see in Figure 1 a candidate for the simplest possible circuit to wheedle a signal from a thermistor, and some basic math to winnow a temperature measurement from its output and parameters 1, 2, and 3 from above.

Figure 1 Basic thermistor passive excitation circuit: Cx = optional noise reduction, perhaps 100 nF; Rx = excitation resistor; Rt = Rx(V/Vref)/(1 – V/Vref); T = (Ln(Rt/Rx)/b + Tx-1)-1.

Other than the (very uncritical) Cx and the thermistor itself, the only component in Figure 1 is Rx. How best to choose its value?

Intuition suggests and math confirms that the optimum (at least nearly so) choice is to make Rx equal to the thermistor’s at the middle of the span of temperature measurement required by the application. Said mid-point temperature (call it Tx) will then output V = Vref/2 and thus distribute ADC resolution symmetrically over the range of measurement. Equation. 5 tells us how to get there.

Suppose we choose a measurement range of 0oC to 100oC, then Tx = 50oC = 323.15 K and Equation 5’s arithmetic tells us (using the 2152723605’s numbers):

Rx = Ro exp(b(Tx-1 – To-1))
Rx = 10000 exp(3892(323.15-1 – 298.15-1))
Rx = 3643 (closest standard 1% value = 3650)

Now, if we conveniently choose Vref = 5V for both input to Rx and to the reference input of the ADC (since this is a ratiometric measurement, the absolute value of Vref is relatively unimportant) we can set:

X = ADC/2N = V/Vref
Then,
T = (Ln(X/(1 – X))/b + Tx-1)-1
oC = (Ln(X/(1 – X))/3892 + 0.003095)-1– 273.15

 And the job is done! 

Or is it? What about that dissipation (self-heating) factor (1.5 mW/°C)? 

We obviously don’t want thermistor self-heating to significantly interfere with the temperature measurement. A reasonable limit for self-heating error might be half a degree and in the case of the 2152723803’s 1.5 mW/°C, this would dictate limiting maximum dissipation to no more than:

Pmax = (1.5 mW)/2 = 0.75 mW

Dissipation maxes out to Vref2/4/Rx when Rt = Rx and in this case of Vref = 5 V will therefore be:

Pmax  = Vref2/4/Rx
= 25/4/3650
= 1.7 mW
= 1.1°C

Yikes! That’s more than twice the stipulated maximum self-heating error. What to do? Not to worry, a solution is suggested by Figure 2.

Figure 2 Rvdd limits max thermistor self-heating to Pmax: Pmax = Vdd2/4/(Rx + Rvdd); Rvdd = Vdd2/4/Pmax – Rx if  > zero, else Rvdd = 0; (Vdd Rx/(Rvdd + Rx)) < Vref  < Vdd.

Dipping again into the 2152723605 numbers and keeping Vdd = 5 V:

Rvdd = 25/4/(0.75 mW) – 3650
Rvdd = 8333 – 3650 = 4.7k
Pmax = 0.749 mW
2.8 V < Vref  <  5 V

Note that if the Figure 2 math yields a zero or negative value for Rvdd, then no Rvdd is required, and the original Figure 1 circuit will work just fine.

Although Vref will vary with Rt and therefore temperature, external-reference monolithic ADCs are typically very tolerant of Vref variations within the range shown and will perform accurate ratiometric conversions despite them.

And now the job is done! We just had to keep thinking positive.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Linearize thermistors with new formula
• Designing with temperature sensors, part two: thermistors
• Pseudologarithmic thermistor signal conditioning spans wide temperature range
• Precision temperature controller has thermal-gradient compensation

The post Getting positive results from NTC thermistors with a simple passive interface appeared first on EDN.

The Indian semiconductor industry is projected to reach USD 55 billion by 2026. To address the global semiconductor shortage, the Indian government has established the India Semiconductor Mission (ISM), which includes four key schemes aimed at building a global hub for semiconductor manufacturing.

Prime Minister Narendra Modi has emphasized the country’s evolving role in technology, stating, “India is already a digital power, nuclear power, and space power; soon India will become an Electronic Power.” The vision of a “Made in India” and “Designed in India” semiconductor powerhouse underscores the nation’s ambition to lead in this critical sector.

To achieve this, India aims to overcome technological challenges, build a skilled workforce, create a resilient supply chain, and develop green energy solutions for sustainable manufacturing. At the heart of all advanced technologies—such as the Internet of Things (IoT), artificial intelligence (AI), nanotechnology, image processing, and augmented reality—lies electronics, making the semiconductor industry a crucial aspect of the global economy.

By investing in and prioritizing the semiconductor sector, India seeks to solidify its position as a key player in the global technology landscape.

Strong Ambitions Fostering Economic Growth

 

India is striking remarkable streaks in the semiconductor industry, reflecting strong ambitions fostering substantial economic growth. Here are the key developments:

1. Upcoming Semiconductor Manufacturing Units:

India plans to establish three new semiconductor manufacturing units with an investment of ₹1.26 lakh crore. This major investment underscores the country’s commitment to becoming a global leader in chip manufacturing.

2. Renesas and IIT Hyderabad Collaboration:

Renesas and IIT Hyderabad have signed a three-year Memorandum of Understanding (MoU) to collaborate on research in VLSI (Very-Large-Scale Integration) and embedded semiconductor systems. This partnership aims to drive innovation and enhance research capabilities in India.

3. Tata Group’s Semiconductor ATMP Facility:

The Tata Group announced in March this year the setup of a semiconductor ATMP (Assembly, Testing, Marking, and Packaging) facility worth ₹27,000 crore. This facility is crucial for strengthening the semiconductor supply chain and boosting India’s manufacturing capabilities.

4. Government Initiatives: Semicon India:

Launched in 2021, the Semicon India initiative aims to develop a robust and sustainable semiconductor and display ecosystem in the country. This initiative highlights the government’s strategic focus on advancing the semiconductor industry.

5. Design Linked Incentive (DLI) Scheme:

The DLI scheme offers financial incentives and design infrastructure support for the entire semiconductor lifecycle, including integrated circuits (ICs), chipsets, system-on-chips (SoCs), systems and IP cores, and semiconductor-linked design. This scheme is designed to foster innovation and attract investments in semiconductor design and manufacturing.

6. Job Creation:

The semiconductor industry is expected to create at least 1 million jobs over the next decade, significantly contributing to economic growth and employment in the country.

These initiatives and investments demonstrate India’s determination to become a global semiconductor manufacturing hub, leveraging public and private sector efforts to achieve this ambitious goal.

On the Way to Become a Sustainable & Self-Reliant Electronics SuperPower

India’s journey towards becoming a sustainable and self-reliant electronics superpower is driven by several key initiatives and strategic policies to boost its electronics manufacturing capabilities, foster innovation, and ensure environmental sustainability. Here are some of the significant steps and factors contributing to this transformation:

·  Government Initiatives and Policies

1. Make in India: Launched in 2014, this initiative encourages companies to manufacture their products in India to boost indigenous production and reduce dependency on imports.
2. Production Linked Incentive (PLI) Scheme: This scheme offers financial incentives to electronics manufacturers to boost domestic production and attract investments.
3. National Policy on Electronics (NPE) 2019: The policy aims to position India as a global hub for Electronics System Design and Manufacturing (ESDM) by promoting the growth of the semiconductor and display industry.
4. 4. Digital India: This campaign aims to ensure that government services are available to citizens electronically, promoting digital literacy and connectivity.

·  Strengthening the Supply Chain

1. Local Sourcing: Encouraging local sourcing of components to reduce reliance on imports.
2. Semiconductor Manufacturing: Plans to set up semiconductor fabrication plants (fabs) in India to establish a strong semiconductor ecosystem.
3. Electronics Manufacturing Clusters (EMCs): Establishing EMCs to provide state-of-the-art infrastructure and facilities to electronics manufacturers.

· Innovation and Research

1. Research and Development: Promoting R&D in the electronics sector to drive innovation and develop cutting-edge technologies.
2. Collaboration with Global Companies: Partnering with global technology companies to bring advanced manufacturing technologies and practices to India.

·         Environmental Sustainability

1. E-Waste Management: Implementing stringent e-waste management rules to ensure proper recycling and disposal of electronic waste.
2. Green Manufacturing Practices: Encouraging the adoption of eco-friendly manufacturing practices to minimize the environmental impact.
3. Renewable Energy: Promoting the use of renewable energy sources in electronics manufacturing processes to reduce the carbon footprint.

· Skill Development

1. Skilling Initiatives: Launching programs to train the workforce in advanced manufacturing technologies and electronics design.
2. Collaboration with Educational Institutions: Partnering with educational institutions to develop a skilled talent pool for the electronics industry.

· Global Competitiveness

1. Improving Ease of Doing Business: Simplifying regulations and providing incentives to attract foreign investments.
2. Export Promotion: Encouraging the export of Indian-made electronics to global markets.

The post India’s Semiconductor Dream: Building Manufacturing Prowess and Global Outreach appeared first on ELE Times.

Improved Shield Design Delivers Higher Voltage Ratings, Up to 20 dB of Radiated E-Field Reduction, and Polarity Marking for Additional EMI Control

Vishay Intertechnology, Inc. (NYSE: VSH) today expanded its IHLE® series of low profile, high current inductors featuring integrated E-field shields with a new second-generation Automotive Grade device in the 10 mm by 10 mm 4040 case size. Offering an improved shield design over previous-generation solutions, and polarity marked for more consistent EMI performance, the Vishay Dale IHLE-4040DDEW-5A lowers costs and saves board space by potentially eliminating the need for separate board-level Faraday shielding.

Compared to traditional composite inductors, the device released today contains the electric and magnetic fields associated with EMI in a tin-plated copper integrated shield. When the shield is connected to ground, the IHLE-4040DDEW-5A provides up to 20 dB reduction in radiated noise interference, and a further 6 dB reduction in magnetic flux leakage to minimize crosstalk to nearby board components. The inductor features continuous high temperature operation to +155 °C and improved operating and isolation voltage ratings of 75 V and 100 V, respectively.

The IHLE-4040DDEW-5A power inductor is optimized for energy storage in switch mode power supplies and provides excellent noise attenuation when used as a DC power line choke. AEC-Q200 qualified, the device is designed for filtering and DC/DC conversion in entertainment / navigation systems; LED drivers; and noise suppression for motors, automotive domain control units (DCU), and other noise-sensitive applications.

Packaged in a 100 % lead (Pb)-free, magnetically shielded, iron alloy encapsulant, the IHLE-4040DDEW-5A offers high resistance to thermal shock, moisture, and mechanical shock from the additional mounting support provided by its two shield terminals. The inductor is RoHS-compliant, halogen-free, and Vishay Green.

Device Specification Table: 

	Low End	High End
Inductance @ 100 kHz (μH)	0.47	68
DCR typ. @ 25 °C (mΩ)	1.55	240
DCR max. @ 25 °C (mΩ)	1.66	252
Heat rating current typ. (A)(¹)	32	2.6
Saturation current typ. (A)(²)	28	3.5
Saturation current typ. (A)(³)	40.1	4.9
SRF typ. (MHz)	32.0	3.5
Case size	4040	4040
Part number	IHLE4040DDEWR47M5A	IHLE4040DDEW680M5A

 (¹) DC current (A) that will cause an approximate ΔT of 40 °C
(²) DC current (A) that will cause L0 to drop approximately 20 %
(³) DC current (A) that will cause L0 to drop approximately 30 %

Samples and production quantities of the IHLE-4040DDEW-5A are available now, with lead times of 16 weeks.

The post Vishay Intertechnology Releases Second-Generation Automotive Grade IHLE® Inductor With Integrated EMI Shield in 4040 Case Size appeared first on ELE Times.

Infineon Technologies AG today announced two new CoolGaN product technologies, CoolGaN bidirectional switch (BDS) and CoolGaN Smart Sense. CoolGaN BDS provides exceptional soft- and hard-switching behavior, with bidirectional switches available at 40 V, 650 V and 850 V. Target Applications of this family include mobile device USB ports, battery management systems, inverters, and rectifiers. The CoolGaN Smart Sense products feature lossless current sensing, simplifying design and further reducing power losses, as well as transistor switch functions integrated into one package. They are ideal for usage in consumer USB-C chargers and adapters.

The CoolGaN BDS high voltage will be available at 650 V and 850 V and feature a true normally-off monolithic bi-directional switch with four modes of operation. Based on the gate injection transistor (GIT) technology, the devices have two separate gates with substrate terminal and independent isolated control. They utilize the same drift region to block voltages in both directions with outstanding performance under repetitive short-circuit conditions. Applications can benefit by using one BDS instead of four conventional transistors, resulting in higher efficiency, density, and reliability. Furthermore, significant cost savings are achieved. The devices optimize performance in the replacement of back-to-back switches in single-phase H4 PFC and HERIC inverters and three-phase Vienna rectifiers. Additional implementations include single-stage AC power conversion in AC/DC or DC/AC topologies.

The CoolGaN BDS 40 V is a normally-off, monolithic bi-directional switch based on Infineon’s in-house Schottky Gate GaN technology. It can block voltages in both directions, and through a single-gate and common-source design, it is optimized to replace back-to-back MOSFETs used as disconnect switches in battery-powered consumer products. The first 40 V CoolGaN BDS product has a 6 mΩ RDS(on), with a range of products to follow. Benefits of using 40 V GaN BDS vs. back-to-back Si FETs include 50 – 75 percent PCB area savings and a reduction of power losses by more than 50 percent, all at a lower cost.

The CoolGaN Smart Sense products feature 2 kV electrostatic discharge withstand and can connect to controller current sense for peak current control and overcurrent protection. The current sense response time is ~200 ns, which is equal or less than common controller blanking time for ultimate compatibility.

Implementing the devices results in increased efficiency and cost savings. At a higher RDSs(on) of e.g. 350 mΩ, the CoolGaN Smart Sense products offer similar efficiency and thermal performance at lower cost compared to traditional 150mΩ GaN transistors. Moreover, the devices are footprint compatible to Infineon’s transistor-only CoolGaN package, eliminating the need for layout rework and PCB respin, and further facilitating design with Infineon’s GaN devices.

Availability

Engineering samples of the CoolGaN BDS 40 V are available now for 6 mΩ and will follow in Q3 2024 for 4 mΩ and 9 mΩ. Samples of the CoolGaN BDS 650 V will be available in Q4 2024, and 850 V will follow early 2025. CoolGaN Smart Sense samples will be available in August 2024. Further information is available here: https://www.infineon.com/cms/en/product/promopages/GaN-innovations/

The post Infineon announces CoolGaN bidirectional switch and CoolGaN Smart Sense for higher performance and more cost-effective power systems appeared first on ELE Times.

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