Новини світу мікро- та наноелектроніки

Nordson TEST & INSPECTION today announced plans to exhibit at SEMICON West 2024, scheduled to take place July 9-11 at the Moscone Center in San Francisco, California. Visitors to booth 1233 will have the opportunity to see demonstrations of Nordson’s WaferSense® semiconductor sensors, Quadra Pro Manual X-Ray System (MXI), and Gen 7 Acoustic Micro Imaging (AMI) system. Additionally, the innovative SpinSAM AMI system will be unveiled in a video presentation for the first time at the show.

The new SpinSAM AMI system delivers industry-leading throughput with unparalleled sensitivity for accurately locating defects in wafer based assemblies. The SpinSAM’s innovative spin scanning method scans up to 4 (300mm) wafers simultaneously at 41 wafers per hour, with best-in-class defect capture and image quality.

With 4 matched waterfall transducers, the system was meticulously engineered to attain full wafer scans in less than 6 minutes. Ideal semiconductor mid-end applications include bonded wafers, Chip-on-Wafer, stacked wafers, MEMS, over-molded wafers and more.

Setting a new industry benchmark for 3D/2D manual inspection in back-end semiconductor applications, the Quadra 7 Pro MXI system revolutionizes the inspection experience with its Onyx® detector technology. This advancement ensures exceptional image clarity and elevated levels of precision and efficiency. The Dual Mode Quadra NT4® tube provides unprecedented flexibility. This innovative technology offers both brightness and resolution modes, enabling operators to seamlessly transition between them according to specific application requirements. This ensures optimal results for a wide range of semiconductor inspection needs.

The Gen7 AMI system powered by C-SAM technology, provides fast and highly accurate inspection for detecting delamination and voiding with the most sophisticated microscope. Ideal for lab analysis and specialized high-resolution applications.

Lastly, for front-end semiconductor tool set-up and maintenance, the WaferSense® ATS2 multi-camera sensor, paired with CyberSpectrum software captures offset data (x, y and z) to quickly teach wafer transfer positions in real-time without opening the tool.

Visit Nordson Test & Inspection at booth 1233 to experience the future of semiconductor inspection and metrology technology that improves yields, processes, throughput and productivity.

For more information, visit www.nordson.com/testinspect.

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Efficient Power Conversion Corp (EPC) of El Segundo, CA, USA — which makes enhancement-mode gallium nitride on silicon (eGaN) power field-effect transistors (FETs) and integrated circuits for power management applications — has launched the 50V, 8.5mΩ EPC2057 GaN FET, designed specifically to meet the evolving needs of high-power USB-C devices including those used in consumer electronics, in-car charging, and eMobility...

In booth 1-156 at Sensor+Test 2024 in Nuremberg (11–13 June), TRUMPF Photonic Components GmbH of Ulm, Germany (part of the TRUMPF Group) — which makes vertical-cavity surface-emitting lasers (VCSELs) and photodiodes for the consumer electronics, datacoms, industrial sensing, heating and automotive markets — is giving two live demonstrations to show the performance of its single-mode VCSEL solutions...

“With TI’s new GaN IPM, engineers can design motor driver systems that deliver all these expectations and operate at peak efficiency.”

Texas Instruments (TI)  introduced the industry’s first 650V three-phase GaN IPM for 250W motor drive applications. The new GaN IPM addresses many design and performance compromises engineers typically face when designing major home appliances and heating, ventilation and air-conditioning (HVAC) systems. The DRV7308 GaN IPM enables more than 99% inverter efficiency, optimized acoustic performance, reduced solution size and lower system costs. It is on display at the Power Electronics, Intelligent Motion, Renewable Energy and Energy Management (PCIM) Conference.

Texas Instruments Incorporated is a global semiconductor company that designs, manufactures, tests and sells analogue and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems.

Nicole Navinsky, Motor Drives business unit manager at TI said “Designers of high-voltage home appliances and HVAC systems are striving to meet higher energy-efficiency standards to support environmental sustainability goals around the world. They are also addressing consumer demand for systems that are reliable, quiet and compact. With TI’s new GaN IPM, engineers can design motor driver systems that deliver all these expectations and operate at peak efficiency.”

Advantages of the first GaN IPM                                                                                

1. Improves system efficiency and reliability with TI GaN

Worldwide efficiency standards for appliances and HVAC systems such as SEER, MEPS, Energy Star and Top Runner are becoming increasingly stringent. The DRV7308 helps engineers meet these standards, leveraging GaN technology to deliver more than 99% efficiency and improve thermal performance, with 50% reduced power losses compared to existing solutions.

In addition, the DRV7308 achieves industry-low dead time and low propagation delay, both less than 200ns, enabling higher pulse-width modulation (PWM) switching frequencies that reduce audible noise and system vibration. These advantages plus the higher power efficiency and integrated features of the DRV7308 also reduce motor heating, which improves reliability and extends the system’s lifetime. 

2. Advanced integration and high power density

Supporting the trend of more compact home appliances, the DRV7308 helps engineers develop smaller motor drive systems. Enabled by GaN technology, the new IPM delivers high power density in a 12mm-by-12mm package, making it the industry’s smallest IPM for 150W to 250W motor-drive applications. Because of its high efficiency, the DRV7308 eliminates the need for an external heatsink, resulting in a motor drive inverter printed circuit board (PCB) size reduction of up to 55% compared to competing IPM solutions. The integration of a current sense amplifier, protection features and inverter stage further reduces solution size and cost.

 

Visitors to PCIM can see new products and solutions from TI are enabling the transition to a more sustainable future with reliable high-voltage technology. TI is also demonstrating a new 800V, 750kW SiC-based scalable traction inverter system for EV six-phase motors, in collaboration with EMPEL Systems.

 

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Digital oscilloscopes are normally operated in real-time acquisition mode, where the analog input is sampled and digitized at a user-selected sampling rate and written continuously into the acquisition memory.

There are, however, other acquisition modes available in most oscilloscopes: random interleaved sampling (RIS), sequence mode, and roll mode (Figure 1).

Figure 1 The sampling mode selections in a typical oscilloscope include sequence, RIS, and roll in addition to the normally used real-time mode. Source: Arthur Pini

 These special modes are useful in applications for measuring specific types of signals. RIS mode increases the effective sampling of the oscilloscope rate for periodic signals. Roll mode is useful in displaying low-frequency signals having very long durations. Sequence mode reduces the dead time between acquisitions and is also applied to signals that have low-duty cycles with long dead times between significant events.

RIS acquisition mode

Let’s look at these acquisition modes,starting with RIS mode. RIS mode is a form of equivalent-time sampling that allows the oscilloscope to acquire repetitive signals at very high sampling rates. Multiple acquisitions are combined in RIS to create a composite waveform with a higher effective sampling rate. The trigger event and the sampling clock are not synchronous. The time between the trigger and the first sample in an acquisition is randomly distributed. Oscilloscopes use a time-to-digital converter (TDC) to measure the time delay between the trigger and the nearest sample of each sweep. This delay is called the horizontal offset. The acquisitions are grouped by delay to provide samples spaced by as little as 5 ps, an effective sampling rate of 200 giga-samples per second (GS/s). Selected waveforms are added together, creating a composite waveform, as shown in Figure 2.

Figure 2 Random interleaved sampling creates a composite waveform based on the measured delays between the trigger and the nearest sample point. Source: Arthur Pini

RIS requires a periodic input waveform with a stable trigger. The maximum effective RIS sampling rate is achieved by making multiple acquisitions and selecting those with horizontal offsets, yielding the desired sample spacing. The random timing between digitizer sampling times and the event trigger provides the time variation. The instrument uses multiple triggers to complete an acquisition. The number of acquisitions required depends on the effective sample rate. The higher the effective sample rate, the more triggers are required. Figure 3 compares real-time and RIS acquisitions of a high-frequency sine wave.

Figure 3 Comparing the real-time acquisition of a 5 GHz sinewave at 40 GS/s (lower trace) with a RIS acquisition at 200 GS/s (upper trace). Source: Arthur Pini

The real-time acquisition of the 5 GHz sine is sampled at 40 GS/s and produces a waveform with 8 samples per cycle. Viewing that waveform using linear display interpolation produces a ‘boxy’ display. The RIS acquisition has an effective sample rate of 200 GS/s, yielding 40 samples per cycle and a smoother display. Sin x/x interpolation could be used to smooth the waveform, but as the waveform bandwidth approaches the Nyquist frequency, especially for pulse-like signals, the potential for interpolator errors such as Gibbs ears increases and the RIS acquisition mode produces a more accurate representation of the acquired waveform. In the oscilloscope used, RIS is only available for timebase settings of 10 ns/division or less; similar restrictions will apply to all oscilloscopes.

Roll mode

Roll mode operates at slow sweep speeds, where the sampled data is acquired at a sufficiently low sampling rate and displays the samples in real time as they are acquired. This is important at slow sweep speeds because it eliminates “pre-trigger” acquisition delays. Usually, an oscilloscope holds off display until the acquisition is complete. If you are using a one-second per division horizontal scale setting, you have to wait at least ten seconds before you see the acquired waveform. At slow sample rates used with long acquisitions, roll mode writes to the display as the sample becomes available, eliminating that delay. In roll mode, the trace moves slowly to the left in the manner of a strip chart recorder display (Figure 4).

Figure 4 The simulated progression of a waveform acquired in roll mode. Source: Arthur Pini

This figure shows the progression of an electrocardiogram signal acquired in roll mode over time. The waveform is written starting on the right and moving to the left over time. Each grid in the figure, starting at the upper left, shows the waveform at a later time until it fills the display in the lower right when a trigger event is detected and the acquisition is complete. Roll mode can be entered depending on the sample rate. This oscilloscope enables roll mode at sweep speeds greater than 100 ms/division (higher if more acquisition memory is used).

Roll mode is useful with low-frequency signals like this electrocardiogram waveform.

Sequence mode

Sequence mode is ideal for capturing many fast signal events in quick succession or for capturing a few events separated by long time periods. This mode breaks the acquisition memory into smaller segments and allows multiple acquisitions within the acquisition memory. Sequence-mode acquisitions minimize dead time between acquisitions (typically <1 µs) by holding off display until all segments are captured. Each acquired segment is time-stamped at its trigger time with the real-time clock, the delay between segments, and the elapsed time since the first trigger.

Sequence mode has three main applications:

1. To acquire data at a high sampling rate when the input waveform has long periods of dead time.
2. To acquire data with minimum dead time between acquisitions.
3. To use the trigger time-stamp table to understand the event timing.

For an example of using sequence mode to analyze signals with long dead time, consider capturing several packets of an I2C data signal and measuring the time between packets and the rise time of the data (Figure 5).

Figure 5 Analyzing and I2C data signal for the inter-packet delay and the rise time of the data signal. Source: Arthur Pini

Four data packets were acquired at 20 ms/division at a sampling rate of 5 MS/s. Cursors measure the delay between packets at 43.5 ms. The duty cycle of the I2C signal is small. So, there is a great deal of memory used to show the dead time between packets, resulting in a low sampling rate. Measurement parameter P2 measures the rise time of the signal. It shows a rise time of less than 291 ns with a yellow warning indicator. The sampling rate is 5 MS/s, or a sample period of 200 ns, is the cause of the measurement warning.

Using sequence mode, we can acquire each packet in its own memory segment. The number of segments is model-dependent and is a function of the size of the acquisition memory. In the oscilloscope used, up to 2000 segments can be stored. The packets are much shorter than the whole data stream, and a higher sampling rate can be used (Figure 6).

Figure 6 A sequence mode acquisition captures ten data packets at a sampling rate of 500 MS/s. It also measures the time between packets using the sequence mode trigger time stamps. Source: Arthur Pini

The number of segments acquired is user-selected; in this example, ten packets were acquired with a sample rate of 500 MS/s (2 ns sampling period) horizontal scale of 200 ms/division. A zoom trace, Z1, horizontally expands segment 1. The rise time measurement now shows 28.19 ns, with the green check status icon indicating a valid measurement. The higher sampling rate provides more than adequate time resolution for the measurement.

Below the display grids, the sequence mode time stamps read the time of each trigger using the oscilloscope’s real-time clock. It also reads the time of each segment trigger from the first trigger as well as the time between triggers with a resolution of one nanosecond. The time between segments is nominally 43.6 ms. In this example, sequence mode eliminated the very long dead time between data packets and improved the measurements.

A second measurement provides an example of using sequence mode to minimize dead time between acquisitions. Looking at the signals generated by an ultrasonic range finder. The range finder emits a burst of five 40 kHz ultrasonic pulses each time a measurement is made (Figure 7).

Figure 7 Each measurement of an ultrasonic range finder emits five 40-kHz bursts. After each burst, it waits for an echo from the target before emitting the next transmitter burst, stopping after the fifth burst. Source: Arthur Pini

When a measurement is started, the range finder emits a 40-kHz burst. It waits to detect an echo before emitting the next burst and continues the process until five ultrasonic pulses have been transmitted. In real-time acquisition mode, trying to acquire five individual bursts would not work. After each acquisition, the oscilloscope would pause to display the data acquired and not be ready for the next burst in the series. That is where sequence mode has an advantage. It segments the acquisition memory into a user-set number of segments and acquires one acquisition into each segment without pausing to display the data until all the segments are filled or the acquisition is manually stopped by the user. The latency between acquisitions of each segment is less than a microsecond in the oscilloscope used. During the acquisition, it records the trigger time of each segment. Figure 8 shows an example of the five-segment acquisition.

Figure 8 The sequence mode acquisition of ultrasonic range finder signal with each of the bursts in its own segment appears in the upper left grid. Source: Arthur Pini

Sequence mode waveforms can be displayed in any of five different ways. The display shown is called an adjacent display. The segments can also be overlapped for comparison. They can be displayed as a waterfall display, with each display segment offset vertically. A perspective display provides a three-dimensional view with segments displayed with both vertical and horizontal offset. The final display type places each segment in its own grid and is called a mosaic display.

Each segment can be operated on as an independent waveform. Using zoom traces, each segment can be displayed independently of the others. In Figure 8, zoom traces Z1-Z5 show each of the segments. Any of the oscilloscope’s measurements and math functions can be applied to the segments independently. As an example, the math trace, F2, applies a 2 kHz bandwidth second-order Butterworth band pass filter centered about 40 kHz to segment 1. Averaging can be applied not only to individual segments as they are acquired, but it can also be computed across all the segments in a single sequence, as shown in math trace F1.

The sequence mode trigger time stamps table shows that ultrasonic bursts occur with a nominal 4.2 ms period and confirms that none were missed.

RIS, Roll, and Sequence modes

These examples provide evidence of the usefulness of RIS, Roll, and Sequence modes. They show how you can extend the capabilities of your oscilloscope.

 Arthur Pini is a technical support specialist and electrical engineer with over 50 years of experience in electronics test and measurement.

Related Content

• Understanding the importance of acquisition memory
• Debug CAN/CAN FD buses with an oscilloscope
• 10 More tricks to extend oscilloscope usefulness
• Using oscilloscope X-Y displays

The post Oscilloscope special acquisition modes appeared first on EDN.

Achieves industry-leading power density by integrating 4th Generation SiC MOSFETs in a compact package

ROHM has developed four models as part of the TRCDRIVE pack series with 2-in-1 SiC molded modules (two of 750V-rated: BSTxxxD08P4A1x4, two of 1,200V-rated: BSTxxxD12P4A1x1) optimized for xEV (electric vehicles) traction inverters. TRCDRIVE pack supports up to 300kW and features high power density and a unique terminal configuration – helps solve the key challenges of traction inverters in terms of miniaturization, higher efficiency, and fewer person-hours.

As the electrification of cars rapidly advances towards achieving a decarbonized society, the development of electric powertrain systems that are more efficient, compact, and lightweight is currently progressing. However, for SiC power devices that are attracting attention as key components, achieving low loss in a small size has been a difficult challenge. ROHM solves these issues inside powertrains with its TRCDRIVE pack.

A trademark brand for ROHM SiC molded type modules developed specifically for traction inverter drive applications, TRCDRIVE pack reduces size by utilizing a unique structure that maximizes heat dissipation area. On top, ROHM’s 4th Generation SiC MOSFETs with low ON resistance are built in – resulting in an industry-leading power density 1.5 times higher than that of general SiC molded modules while greatly contributing to the miniaturization of inverters for xEVs.

The modules are also equipped with control signal terminals using press fit pins enabling easy connection by simply pushing the gate driver board from the top, reducing installation time considerably. In addition, low inductance (5.7nH) is achieved by maximizing the current path and utilizing a two-layer bus-bar structure for the main wiring, contributing to lower losses during switching.

 

Despite developing modules, ROHM has established a mass production system similar to discrete products, making it possible to increase production capacity by 30 times compared to conventional SiC case-type modules. To obtain samples, please contact a sales representative or visit the contact page on ROHM’s website.

Product Lineup

TRCDRIVE pack is scheduled to be launched by March 2025 with a lineup of 12 models in different package sizes (Small / Large) and mounting patterns (TIM: heat dissipation sheet / Ag sinter). In addition, ROHM is developing a 6-in-1 product with built-in heat sink that is expected to facilitate rapid traction inverter design and model rollout tailored to a variety of design specifications.

Application Examples

・ Automotive traction inverters

Comprehensive Support

ROHM is committed to providing application-level support, including the use of in-house motor testing equipment. A variety of supporting materials are also offered, such as simulations and thermal designs that enable quick evaluation and adoption of TRCDRIVE pack products. Two evaluation kits are available as well, one for double-pulse testing and the other for 3-phase full bridge applications, enabling evaluation in similar conditions as practical inverter circuits.

For details, please contact a sales representative or visit the contact page on ROHM’s website.

Terminology

Traction Inverter

Traction motors in electric cars are driven by 3-phase AC power with a phase shift of 120°. Traction inverters convert direct current supplied from the battery into 3-phase alternating current.

2-in-1

To convert DC into 3-phase AC, one high-side and one low-side MOSFET are required per phase for switching. A 2-in-1 configuration combines both of these MOSFETs into a single module.

 

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Japan-based power semiconductor device maker ROHM Co Ltd has launched its EcoSiC brand as a trademark for products using silicon carbide (SiC)...

The V-harvester board is a photovoltaic (PV) harvesting backup demonstration circuit. It is a sophisticated stand-alone board charged using TEMD5080X01 micro PV cells or with micro USB. The input power goes into an e-peas low power AEM10941 controller, where it is stepped up to the supercapacitor voltage of 4.2 V. Upon power demands at the interface or ENLV, ENHV settings, the controller converts the supply voltage to the target voltages using low dropout regulators (LDO).

The post Energy Harvesting: Eliminating Battery Replacements for IoT Nodes With 196 HVC ENYCAP™ appeared first on ELE Times.

Using a modular fabrication process, the team created a quantum-system-on-chip that integrates artificial atom qubits onto a semiconductor chip.

Tokyo-based Mitsubishi Electric Corp has begun shipping low-current 3.3kV/400A and 3.3kV/200A versions of a Schottky barrier diode (SBD) embedded silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) module...

Gordon Bell, known by many peers as the father of computer architecture, defined the classification framework for the computer industry and helped design the first minicomputers.

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As system-on-chip (SoC) designs become more complex and powerful, catching potential errors and issues in specifications at the front-end of the design cycle is now far more critical. An EDA outfit based in Gentbrugge, Belgium, claims to have employed a shift left of simulation and synthesis tasks to catch specification errors early in the chip design cycle and fix inefficiencies in hardware description language (HDL)-based design flow.

The traditional HDL-based design flow is no longer viable, says Dieter Therssen, CEO of Sigasi, a privately held and self-funded firm founded in 2008. That’s because the traditional HDL workflow cannot accommodate the massive amounts of design specifications encompassing high-level synthesis results, complex SoC intellectual property (IP), and special features like generative artificial intelligence (genAI) creations.

Such levels of abstraction call for a plug-and-play approach for large HDL files containing functionality created with domain-specific knowledge to integrate hundreds of billions of transistors on a chip. In other words, HDL creation, integration, and validation must be redefined for the chip design cycle to fix the inefficient HDL-based design flow.

Therssen claims that Sigasi’s new HDL portfolio provides hardware designers and verification engineers the workflow makeover they need, enabling them to work in a powerful environment to create, integrate, and validate their designs while leveraging shift-left principles. Sigasi Visual HDL portfolio, an integrated development environment (IDE), employs the shift-left methodology to give hardware designers and verification engineers better insight during the design process.

It enables them to easily manage HDL specifications by validating code early in the design flow, well before simulation and synthesis flows. So, it’s a shift left of simulation and synthesis tasks, which flags problems while users enter the HDL code. While doing so, it enforces coding styles as recommended by safety standards such as DO-254 or ISO 26262 and catches Universal Verification Methodology (UVM) abuses.

Sigasi Visual HDL or SVH is fully integrated with Microsoft’s Visual Studio Code (VS Code), the most popular IDE according to Stack Overflow’s 2019 survey. That allows hardware designers and verification engineers to use git, GitHub Source Control Management, and a selection of utilities to facilitate mundane tasks like extracting TODO comments or bookmarking important sections in HDL code.

Sigasi Visual HDL will be available at the end of June 2024.

Sigasi Visual HDL, built as a tiered portfolio, offers three commercial editions and one community edition to meet specific SoC design and verification challenges.

1. Designer Edition

It meets the specific requirements of individual engineers who need introspection of their HDL projects. The Designer Edition includes all the essential guidelines and tools to create quality code, from hovers and autocompletes to quick fixes, formatting, and rename refactoring.

2. Professional Edition

It builds on the Designer Edition to incorporate more complex features focused on verifying HDL specifications. That includes graphic features like block diagrams and state machine views as well as UVM support.

3. Enterprise Edition

It offers features needed by large engineering teams, including command-line interface capabilities to safeguard the code repository and ensure a better handoff to verification groups. The Enterprise Edition also includes documentation generation as part of a better HDL handoff.

4. Community Edition

It lets users explore its features for non-commercial uses and is commonly used by students and teachers who want to better learn the fundamentals of HDL design. So, students no longer need to request a limited-time educational license; they can download the VS Code extension and upgrade their HDL education.

Sigasi Visual HDL—to be made available at the end of June 2024—will be displayed at Booth #2416 on second floor during Design Automation Conference (DAC) at Moscone West in San Francisco on 24-26 June 2024.

Related Content

• HDL: A Design Flow Runs Through It
• Opinion: Why IDEs for hardware design fail
• Introduction to High-Density Programmable Design
• HDL design methods for low-power implementation
• HDL-design challenges and philosophies for real-world ASIC implementations

The post HDL makeover from creation to integration to validation appeared first on EDN.

Farnell Global (which trades as Farnell in Europe, Newark in North America and element14 in Asia Pacific) has announced a new global distribution partnership with Transphorm Inc of Goleta, near Santa Barbara, CA, USA, which designs and manufactures JEDEC- and AEC-Q101-qualified high-voltage gallium nitride (GaN) field-effect transistors (FETs) for power conversion applications...

Vector Photonics Ltd (which was spun off from Scotland’s University of Glasgow in 2020, based on research led by professor Richard Hogg) has received £1.667m in equity investment and £1.27m in additional research funding for the continued commercialization of its unique Surface Coupling Laser (SCL) technology, which is claimed to enhance performance in applications as diverse as next-generation data centers, co-located optics, artificial intelligence (AI), metal and plastic printing, LiDAR, and optical sensing...

Showcasing their latest advancements in battery systems, Bosch Rexroth’s automation technologies are prominently featured at the Michigan CIC, with a centrally located Battery Module Demonstration Room. Resembling a pilot line, this room features a broad spectrum of Bosch Rexroth technologies from its automation portfolio, covering cell production, modular assembly, and end-of-line testing, among other functions.

Process Reliability

Various types of batteries necessitate distinct production methods for converting electrode films into cell elements. Whether it’s pouch cells, prismatic cells, or cylindrical cells, high dynamics and precision are essential for separating or stacking the cathodes and anodes. Bosch Rexroth boasts deep expertise in dry room and clean room production, including long-term component testing, ensuring high-quality standards and reliable production processes.

Technologies on Display for Cell Production:

1. VarioFlow plus Conveyor System:

• A tight turn radius minimizes tool footprint.
• Swift and efficient transportation of cells within process stations and between machines
• Items can be conveyed either on pallets or directly on the conveyor system
• Configurable for utmost design flexibility, handling high-volume products horizontally, vertically, and around obstacles.

2. Rexroth Flexible Transport System Pallet Boost:

• A highly dynamic transfer system propelled by magnets, ideal for high-throughput machines and assembly lines
• Synchronous and asynchronous bi-directional transfer.
• Compatible with standard TSplus modules for creating a complete loop or as a stand-alone section.
• Precise motion profile and stopping control with acceleration up to 30 m/s² and speed up to 5 m/s.
• Positioning repeatability down to ±20 μm.

Battery Pack Assembly

Process-reliable smart conveyor and positioning systems are crucial for battery module assembly. The Battery Customer Innovation Center showcases Bosch Rexroth’s advanced automation technology, including linear modules and Cartesian systems for precise positioning, as well as advanced resistance welding systems.

Linear Modules and Cartesian Systems:

• Pre-configured components designed to reduce engineering, assembly, and start-up time.
• The LinSelect system configurator swiftly integrates with the latest BOM and CAD models
• High system dynamics and stiffness, with repeatability to ±50 μm.
• Compatible with dry-room environments.

Resistance Welding Systems

The Battery CIC includes a resistance welding lab featuring Bosch Rexroth’s modular system with advanced welding controls, AC or MFDC inverters, and control software, along with interfaces for all popular fieldbuses. These systems are designed to enhance the overall system and process reliability, with Weld Spot Analytics software assisting welding engineers in making better, more assured decisions. Together with adaptive control, these features ensure high-quality welds and minimize inefficiencies in high-production environments.

End-of-Line Testing

Battery packs are complex devices that must meet stringent safety standards. Bosch Rexroth’s end-of-line (EOL) test systems at the Battery CIC feature scalable IndraDrive ML and fastPLC system ILC, offering:

• Efficient utilization of shared hardware for power supply, drive inverter, and DC/DC converter
• Efficient line regeneration and low harmonics.
• High power handling (up to 1000V DC and 500kW).
• Achieving the lowest ripple of DC voltage and current
• Compact footprint, cabinet size, and system weight.
• Future-proof open connectivity with protocols such as PROFINET, EtherCAT, Sercos, Ethernet/IP, Modbus TCP, OPC-UA, LabView, Simulink, and Java.

Bosch Rexroth’s innovative automation technologies at the Michigan CIC demonstrate their commitment to advancing battery system production, ensuring process reliability, and enhancing overall efficiency and performance.

The post Bosch Rexroth Unveils Latest Battery Production Innovations appeared first on ELE Times.

•  Infineon takes a pioneering role in the semiconductor industry and creates transparency for its customers regarding the climate impact of individual product families
• Infineon aims to eventually cover its entire product portfolio
• Providing carbon footprint data at the product level is another major milestone in Infineon’s sustainability strategy

Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY) will provide customers with comprehensive Product Carbon Footprint (PCF) data, taking a pioneering role in the semiconductor industry. The company is committed to eventually providing PCF data for its entire product portfolio, starting now with about half of its portfolio. The initiative will empower customers to advance their own sustainability goals and reduce their carbon footprint effectively along the entire supply chain. The Product Carbon Footprint is a metric that quantifies the greenhouse gas emissions associated with an individual product, allowing the comparison of different products’ climate impact. Infineon will share more insights with customers at the upcoming PCIM trade fair in Nuremberg, Germany, from 11 to 13 June 2024.

“By providing comprehensive Product Carbon Footprint data, we are driving the vision of a net-zero society and empowering our customers to reduce carbon emissions even more effectively,” says Elke Reichart, Member of the Management Board and Chief Digital and Sustainability Officer at Infineon. “Infineon is taking a leading role in carbon transparency by committing to include the entire product portfolio over the coming years. This underlines our ambition to be a leader not only in terms of technology, but also sustainability.”

The specific data Infineon provides on its individual products is essential for the growing number of customers who want to increase transparency on their own carbon footprint. Moreover, it supports informed decision making to leverage additional potential for reducing emissions along the value chain.

In the absence of established industry standards, Infineon has developed a robust methodology to calculate the Product Carbon Footprint, incorporating customer needs and best practices. Infineon includes emissions from raw materials and supplies, its own manufacturing processes, manufacturing partners and transportation to the customer (“from cradle to gate”). This means that the Product Carbon Footprint reported by Infineon covers scope 1 and 2 emissions as well as scope 3 emissions from suppliers and manufacturing partners, all the way to the customer’s gate. The Product Carbon Footprint is expressed in kilograms of carbon dioxide equivalent (kg CO2e).

Infineon has published the assessment of reference product families on the Infineon website.

Driving transparency goes hand in hand with Infineon’s strong commitment to decarbonization and digitalization. Infineon’s products make a major contribution to the global energy transition and thus to a net-zero society. They are used in solar and wind power plants, electric cars and increase energy efficiency in numerous applications, including AI data centers. Over their lifetime, the company’s chips overall save 34 times the amount of CO2e emitted during their production.

Breaking the carbon footprint down to the product level is another major milestone in Infineon’s sustainability journey. Infineon has already pledged to achieve carbon neutrality by 2030 for direct and indirect emissions (scope 1 and 2). Last year, the company additionally committed to setting a science-based target encompassing supply chain emissions (scope 3) as well.

 

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Editor’s Note: This DI is a two-part series.

Part 1 discusses audio oscillators, namely the Wien bridge and biquad, state-variable, or two-integrator-loop configuration.

Part 2 will add distortion-free feedback to the biquad to produce a pure sine wave.

Over the years, the Design Ideas (DI) column has featured many interesting oscillators, but none that I can recall was specifically designed to produce a really clean sine wave. Putting that omission together with the need to rebuild my old sub-0.01% sine generator gave me the perfect excuse to do some exploring, ending up with this DI, which is in two parts. First, we’ll look at ways not to do it, then part 2 will show how to get Audio Precision® distortion levels for RadioShack prices.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The alternatives

We won’t even consider squashing a triangle wave to give something reasonably sinusoidal, as 0.3% THD is the best that this approach can give without complex, multi-breakpoint “squashing” networks. Similarly, phase-shift oscillators are out; their q-factor is low, and three-gang pots are not catalog items. And if I were designing something for modern production, the starting-point would be a 24-bit DAC fed by a small processor containing a large look-up table, but that’s not something that can be knocked up from available parts in an afternoon.

So, what’s wrong with a good old Wien bridge circuit? The relevant Wikipedia page contains much historical, practical, and mathematical detail, and it reports that distortion levels down to 0.0003% (3  ppm) can be achieved, so we have one benchmark, though that’s most likely for a spot frequency rather than for a multi-range, fully-tunable device. A practical target is 96 dB or 0.0015%, which is the absolute limit for CD-type 16-bit linear PCM audio, while a more arbitrary goal is 120 dB, or 1 ppm. At these levels, THD may be dominated by circuit noise, which we’ll conveniently ignore for now.

Wien bridge oscillator

To check things out, I breadboarded a basic circuit using an LM4562 op-amp, carefully-matched resistors and polystyrene capacitors, and amplitude-stabilised using a photoconductive opto-isolator (essentially an LED and an LDR) driven by some heavy filtering. (A thermistor only works for higher output levels and is very bouncy.) Figure 1 shows the schematic and Figure 2 the output spectrum at close to 1 kHz for a level of -20 dBV (about -22 dBu, or 0.283 Vpk-pk).

Figure 1 A simple Wien bridge oscillator, using a photoconductive opto-isolator to help stabilise the amplitude.

Figure 2 The spectrum of the oscillator running at ~1 kHz, its output being at -20 dBV.

The spectrum implies a THD of about -76 dB or 0.02%: only so-so. However, I have learnt to be cautious of FFTs when the dynamic range of the signal to be examined exceeds about 90 dB, and prefer to notch out much of the fundamental, allowing a clearer view of the harmonics. Figure 3 shows the result of this: much better, with a THD of perhaps -88 dB, or 0.004%.

Figure 3 The spectrum of the same signal, but with the fundamental mostly notched out to show the harmonics more accurately.

Better, and not bad for a lash-up, but still off-target. (Note that the scale now shows the relative level of the harmonics, in dBc, as the oscillator’s output is at 20 dBV and the notch filter has a voltage gain of 10 dB or 20 dB.) With a little more thought and a lot more fiddling—or vice versa—we could probably improve its performance to the benchmark level, but a different starting-point looks more promising. The biggest problem is the amplitude control loop because removing all the ripple effects the damping badly, increasing the loop settling time. The low Q-factor of a Wien bridge, 1/3, does us no favours at all.

Bi-quad loop filter

My favourite circuit for comprehensive filters and oscillators has always been the bi-quad(ratic), state-variable, or two-integrator-loop configuration, one topology of which is shown in Figure 4.

Figure 4 A classic bi-quad or two-integrator-loop filter, with its high-pass, bandpass, and low-pass outputs.

You may well recognise something like this from a hundred and more NatSemi/TI datasheets and app notes. Its basics go back to the 1950s, I think, when “operational amplifiers” usually meant racks of glowing bottles, and it is versatile, designable, and controllable. This version is cut for a Q-factor of ~16 and a gain of ~10. We’ll now package it with a dashed line and treat it as a module. Assume ±5 V to ±15 V supplies, with plenty of decoupling caps.

To make it oscillate, we take the bandpass (BP) output and feed it back to the input at a suitable level. This is often done by limiting the BP signal with a pair of back-to-back diodes, much as shown in Figure 5.

Figure 5 The filter with added diode-limited feedback becomes an oscillator, but with plenty of harmonics, giving a THD of around 0.0%.

With the values shown, the diodes compress the signal to ~2/3 of the output level. Less than this, and we lose stability; more, and the harmonics become excessive. The feedback network shown keeps the impedances around the diodes low to allow clean operation up to 100 kHz and beyond, while the added thermistor improves the amplitude stability with temperature. Match the diodes for forward voltage to minimise even-harmonic distortion. The third harmonic produced by the diodes is reduced by about 22 dB by the time it reaches the LP output, higher harmonics being attenuated even more.

The spectrum for the raw (LP) output shows a THD of ~0.08%, which is about the best that this approach can give. (The “notched” spectrum—not shown—showed fewer and lower peaks, but the third harmonic—the limiting factor—was still at the same level.) Because there is no control loop as such, there can be no loop stability issues, though the settling-time is appreciable at low frequencies. It’s still a good basis for a multi-range general-purpose AF oscillator.

With correspondingly larger capacitors and resistors, it also works well at very low frequencies, though FET-input op-amps are needed to avoid leakage. With tuning components of 5µ7 (= 4µ7 + 1µ0; PET dielectrics) and 3M3 resistors, and with TL072s fitted in place of the LM4562s, the waveform at ~8 mHz, or a calculated 118.2 s/cycle, looks like Figure 6.

Figure 6 Using µF and MΩ for tuning, a diode-stabilised bi-quad will easily work down in the mHz region—about 8 mHz, in this case.

Why anyone would want to use a purely analog approach to generating such low-frequency signals escapes me, but trying it was irresistible, even if it took an hour or so to settle down properly. (I lacked the patience to try even larger values of timing components. And don’t even think of asking for the spectrum.)

To be continued…

In part 2, we will take the bi-quad filter and add distortion-free feedback, similar to that used with the Wien bridge but on steroids, to produce a seriously pure sine wave.

—Nick Cornford built his first crystal set at 10, and since then has designed professional audio equipment, many datacomm products, and technical security kit. He has at last retired. Mostly. Sort of.

Related Content

• Squashed triangles: sines, but with teeth?
• Building a JFET voltage-tuned Wien bridge oscillator
• Injection-lock a Wien-bridge oscillator
• Switched-Capacitor Filters Beat Active Filters at Their Own Game
• Oscillator keeps THD below 1 ppm
• 555 triangle generator with adjustable frequency, waveshape, and amplitude; and more!
• Inductor-based astable 555 timer circuit

The post Ultra-low distortion oscillator, part 1: how not to do it. appeared first on EDN.

Generative AI is revolutionizing Windows applications and games by enabling new capabilities, such as unscripted, dynamic NPCs, novel works of art, and significant frame rate boosts in gaming. As generative AI’s applications and capabilities expand, the demand for computing power to support these workloads increases. Hence comes into play Hybrid AI, which is an amalgamation of onboard AI acceleration of NVIDIA RTX and cloud-based GPUs to meet these requisites effectively.

Hybrid AI: A Harmonious Solution

Hybrid AI synergizes local PC and workstation computing with cloud scalability, offering flexibility to optimize AI workloads based on specific use cases, cost, and performance:

1. Local AI on RTX GPUs:

• Delivers high performance and low latency.
• Always available, even offline.

2. Cloud-based AI:

• Runs larger models and scales across many GPUs.
• Serves multiple clients simultaneously.

By leveraging both local and cloud resources, Hybrid AI ensures AI tasks run optimally, whether locally or in the cloud, and accelerates these tasks using NVIDIA GPUs and AI stacks, including TensorRT and TensorRT-LLM. This results in reduced wait times and enhanced AI-powered features for users.

Tools and Technologies Supporting Hybrid AI

Several tools and technologies from NVIDIA support hybrid AI workflows for creators, gamers, and developers:

For Creators: Dream in the Cloud, Realize Locally

Generative AI empowers artists to ideate, prototype, and brainstorm new creations. For example:

Generative AI by iStock, powered by NVIDIA Edify:

• Provides a generative photography service built for and with artists.
• Offers extensive tools to explore styles, and variations, modify parts of an image, or expand the canvas.
• Allows artists to ideate multiple times and bring concepts to life quickly.

Once the creative concept is ready, artists can utilize RTX-powered PCs and workstations for AI acceleration in over 125 top creative apps, including Photoshop, DaVinci Resolve, and Blender.

For Gamers: Hybrid ACE Revolutionises NPC Interaction

Hybrid AI, through NVIDIA ACE, enables interactive PC gaming by integrating generative AI models into digital avatars on RTX AI PCs. This allows developers to create NPCs that can understand and respond to human player text and speech in real time, enhancing the gaming experience.

For Developers: A Hybrid Tool That Runs Anywhere

Hybrid AI assists developers in building and tuning new AI models. NVIDIA AI Workbench helps developers:

• Create, test, and customize pre-trained generative AI models and LLMs on RTX GPUs.
• Access repositories including Hugging Face, GitHub, and NVIDIA NGC.
• Reproduce, collaborate on, and migrate projects easily.
• Scale up projects when additional performance is needed, and bring them back to local RTX systems for inference and light customization.

The Hybrid RAG Workbench project allows developers to:

• Create customizable RAG applications.
• Embed documents locally and run inference on local RTX systems or cloud endpoints.
• Adapt projects to use various models, endpoints, and containers.
• Quantize models to run on their preferred GPU.

Conclusion

Hybrid AI powered by NVIDIA GPUs offers a seamless integration of local and cloud resources, providing creators, gamers, and developers with optimized AI workflows. This enables the realization of cutting-edge AI-powered features, driving innovation and performance across a wide range of applications. Whether developing new AI models, creating art, or enhancing gaming experiences, hybrid AI solutions provide the best of both worlds for AI enthusiasts and professionals.

The post Tap into Hybrid AI Workflows with NVIDIA AI-Powered Tools appeared first on ELE Times.

The United States Department of Commerce will provide funding to promote the deployment of open networks in the U.S. and abroad. Rohde & Schwarz and VIAVI offer joint test solutions to meet the needs of radio equipment manufacturers who plan to apply for the funding.

Rohde & Schwarz and Viavi Solutions Inc. (VIAVI) today announced an expansion of their partnership delivering state-of-the-art O-RU testing. These solutions are ideally suited to the needs of radio manufacturers planning to bid for the United States Department of Commerce’s National Telecommunications and Information Administration (NTIA) Public Wireless Supply Chain Innovation Fund (PWSCIF) Second Notice of Funding Opportunity (NOFO 2), which focuses on Open Radio Commercialization and Innovation. Since the launch of this partnership, Rohde & Schwarz and VIAVI have established a reputation for compact, flexible solutions drawing from the strengths of both companies while delivering a seamless user experience. The two companies offer:

O-RU Conformance Test

Fronthaul conformance tests, defined by the O-RAN ALLIANCE, ensure that O-RUs are interoperable with the O-RAN distributed unit (O-DU). The joint test solution includes:

• The R&S SMW200A vector signal generator, R&S FSVA3000 signal and spectrum analyzer and the R&S VSE signal analysis software from Rohde & Schwarz, to emulate a real-world radio environment by generating, capturing and analyzing RF signals, extended for O-RAN applications.

• The TM500 O-RU Tester from VIAVI, implementing the O-RAN Distributed Unit (O-DU) side of the M-plane and C/U-plane functionality necessary to configure the interface with the O-RU and exchange of I/Q data over the Open Fronthaul.

• The O-RU Test Manager application, providing a single point of control for the integrated system, simplifying testcase workflow while allowing deeper data inspection and analysis as needed.

The same set-up can be also used for performing conformance cases defined by 3GPP TS 38.141/36.141 for 5G/LTE base stations (BS).

Test Scalability

As O-RAN radios move to commercial deployment, development testing needs to move beyond lab validation of conformance to greater use case and functionality testing within R&D. These newer use cases prioritize simplicity, speed and cost effectiveness in testing. The R&S PVT360A is a compact, single-box vector signal analyzer (VSA) and vector signal generator (VSG) that combines with the VIAVI TM500 O-RU Tester and VIAVI O-RU Test Manager Application for a more scalable solution, providing a cost-optimized and simpler setup that is well-suited for R&D teams that require multiple test lines to accelerate time to market. The TM500 O-RU Tester can also be scaled to provide direct performance testing such as uplink and downlink data performance and capacity testing.

Network Energy Saving

O-RAN radio units (O-RU) consume the majority of power in 5G radio access networks. Network equipment manufacturers and service providers are prioritizing O-RU energy efficiency without sacrificing performance. Rohde & Schwarz and VIAVI have developed a fully automated testbed to verify O-RU energy efficiency, including the R&S RTO6 oscilloscope, R&S NGP800 power supply and the VIAVI TM500 O-RU Tester. The TM500 O-RU Tester emulates the DU, synchronizes and configures the O-RU and offers several test scripts to verify O-RU energy efficiency under different load conditions. The R&S equipment can then monitor dynamic device activities versus power consumption: The oscilloscope monitors energy dynamics under various traffic conditions by tracking power changes over time, while the power supply – besides powering the O-RU – also provides high measurement resolution and accuracy over a long period of time. The O-RU Test Manager Application ensures a seamless user experience across the testbed.

Alexander Pabst, Vice President Market Segment Wireless Communications at Rohde & Schwarz, said: “Our joint O-RU conformance test solution has been used to test a wide range of different O-RUs at global plugfests of the O-RAN ALLIANCE over the last years. It has a solid presence at Open Testing and Integration Center (OTIC) labs worldwide and was instrumental in initial O-RU certifications in Asia and most recently also in the first certification in Europe. With this long track record, we are now set to serve the efforts of the NTIA to bring forward Open Radio technology. This is putting the successful collaboration between Rohde & Schwarz and VIAVI to the next level.”

Ian Langley, Senior Vice President and General Manager, Wireless Business Unit, VIAVI, said: “Rohde & Schwarz and VIAVI are proud to support the NTIA Open RAN Innovation and Commercialization based on our best-of-breed approach with a unified customer experience. Since we first began offering O-RU conformance testing, open radios have advanced significantly, and test requirements – from scalability for use across the development cycle, to energy saving, have become critical. We are pleased to expand our partnership into these new areas.”

For more information on O-RAN testing solutions from Rohde & Schwarz, visit: https://www.rohde-schwarz.com/wireless/O-RAN

The post Rohde & Schwarz and VIAVI offer joint network test solutions supporting Open Radio Commercialization and Innovation appeared first on ELE Times.