Новини світу мікро- та наноелектроніки

Courtesy: Infineon

Do you wonder how a traditional SIM works? Today, through this blog, I will talk about the working process of SIM as well as eSIM Remote SIM Provisioning (RSP). So, let’s jump into the techy details.

Working of physical SIM cards

Let’s first take a look at the figure 1 below:

Figure 1: Cases explaining the working of physical SIM cards

Did you understand anything from this given figure? Well, I’ll explain it now.

Traditional SIM cards were owned and issued by a particular network operator. The Figure 1.1 above showcases that an end user signs up a contract with their selected network operator, they pay the amount for the service and gets the physical SIM card (Case (a)).

Later, the same end user signs-up a contract with a different network operator, pays the service charges and gets the new physical SIM card (Case (b)).

Here, we see that if the end user has to use (a) network or (b) network, he needs to swap the SIM cards on their own.

eSIM remote SIM provisioning

After reading about how physical SIM works, you must be wondering how an eSIM differs from traditional SIMs?

Take a look at the image below:

Figure 2: Remote SIM Provisioning

For remote SIM provisioning, no physical SIM card is required, but an embedded SIM in your handset/device (also called eUICC) – a single eSIM can accommodate and securely store multiple profiles in a single device and each profile comprises operators as well as subscriber’s data.

Let’s see what this figure 2 explains. ­­

At first, in step (a) the end user signs-up a contract with their preferred network operator, pays the required charges, and instead of getting a physical SIM, he receives instructions to connect to operator’s Remote SIM Provisioning system (RSP) [e.g., QR code]. This QR code contains the address of RSP system (SM-DP+ (Subscription Manager Data Preparation) server within the GSMA specifications), which allows the end user to download and install a SIM profile (as shown in step (b)). Once the profile is active, the user can connect to the network successfully (as shown in step (c)).

Important note: In Figure 2, the end user can repeat the process to install more profiles on a single device as shown below in Figure 3. This allows users to switch between profiles 1 and 2 as per their needs.

Figure 3: Multiple Installed Profiles on eSIM

Some important terms:

Profile: A profile comprises of the operator data related to a subscription. It includes data like – operator’s credentials and provided third-party applications.

eUICC: Embedded Universal Integrated Circuit Card (eUICC) is a secure element in the eSIM solution which can accommodate multiple profiles.

Profiles are always remotely downloaded over-the-air into a eUICC. Although the eUICC is an integral part of the device, the profile remains the property of the operator as it contains items “owned” by the operator (International Mobile Subscriber Identity (ISMI), Integrated Circuit Card ID (ICCID), security algorithms, etc.) and is supplied under licence.

Hence, the eUICC acts as a secure element to store the eSIM Profiles in the device.

We now know how traditional SIM cards VS embedded SIMs (eSIMs) functions differently. In the next blog, I’ll discuss about GSMA M2M solution – The first RSP solution developed by GSM Association (GSMA) for Machine to Machine (M2M) connectivity. 

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Qromis Inc of Santa Clara, CA, USA (founded in 2015) has received the Frost & Sullivan 2024 Global Enabling Technology Leadership Award. Frost & Sullivan presents this award each year to a company that develops a pioneering technology that enhances current products and enables new product and application development...

A look at the simplest FM demodulation technique. It doesn’t give the lowest possible output distortion, it doesn’t reject amplitude distortion effects, but it is simple and can be used at virtually no cost.

Demodulation of frequency modulation (FM) signals can be done in many ways. There are FM discriminators, ratio detectors, quadrature detectors, phase lock loop designs, and even methods of getting down to first principles as shown on here.

However, one more method we can add to the toolkit is slope detection which is perhaps the simplest approach of them all.

Imagine a receiver of some sort which has some sort of bandpass characteristic. Typically, this would be a superheterodyne receiver whose bandpass properties are achieved in the intermediate frequency (IF) amplifier stage(s). We can tune our receiver so that the center frequency of the FM signal appears on one slope of the receiver’s bandpass characteristic meaning off to the side of the characteristic’s peak rather than at that peak itself (Figure 1).

Figure 1 Slope detection method where a bandpass slope below the resonant peak is used to create a slope-induced amplitude modulation where a simple envelope detector can be used to recover the modulation signal.

The figure above shows use of the bandpass slope below the resonant peak, but the slope above the resonant peak could be used just as well.

Whatever frequency deviation the input FM signal may have will result in an output signal in which an amplitude modulation property will have been imparted. A simple envelope detector can then be used to recover the modulation signal.

There will of course be some distortion because the bandpass scale factor versus frequency is not linear, but if that distortion is deemed tolerable, this very simple demodulation technique can work.

John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).

Related Content

• Build your own superheterodyne receiver
• A Quadrature Demodulator Tutorial
• Modulation basics, part 1: Amplitude and frequency modulation
• How to design a digital FM radio
• Understand Radio Architectures, Part 1
• Measuring pulsed RF signals with an oscilloscope

The post Slope detection for FM demodulation appeared first on EDN.

congatec – a leading provider of embedded and edge computing technology – presents new high-performance computer-on-modules (COMs) with i.MX 95 processors from NXP, thereby expanding its extensive module portfolio with low-power NXP i.MX Arm processors. In doing so, congatec underlines its strong partnership with NXP. Customers benefit from straightforward scalability and reliable upgrade paths for existing and new energy-efficient edge AI applications with high security requirements.

In these applications the new modules offer the advantages of up to three times the GFLOPS computing performance compared to the previous generation with i.MX8 M Plus processors. The new neural processing unit from NXP called ‘eIQ Neutron’ doubles the inference performance for AI accelerated machine vision. In addition, the hardware-integrated EdgeLock® secure enclave simplifies the implementation of in-house cyber security measures.

The new conga-SMX95 SMARC modules are designed for an industrial temperature range of -40°C to +85°C, are robust in mechanical terms and optimised for cost- and energy-efficient applications. The integrated high-performance eIQ Neutron NPU makes it possible for AI accelerated workloads to be performed even closer to the local device level. Specific applications for the new SMARC modules can be found in AI accelerated low-power applications in sectors such as industrial production, machine vision and visual inspection, rugged HMIs, 3D printers, robotics controllers in AMR and AGV, as well as medical imaging and patient monitoring systems. Other target applications include passenger seat back entertainment in buses and aircraft, along with fleet management in transportation, and construction and farming applications.

The feature set in detail

The new conga-SMX95 SMARC 2.1 modules are based on the next generation of the NXP i.MX 95 application processors with 4-6 Arm Cortex-A55 cores. NXP is now using the new Arm Mali 3D graphics unit for the first time, which delivers up to three times the GPU performance compared to predecessors based on i. MX8 M Plus. Also new is the image signal processor (ISP) for hardware accelerated image processing. Particularly noteworthy is the NXP eIQ Neutron NPU for hardware accelerated AI inference and machine learning (ML) on-the-edge in the new SMARC modules. The corresponding eIQ® software development environment from NXP offers OEMs a high-performance development environment which simplifies the implementation of in-house ML applications.

In addition, the new SMARC modules integrate a real-time domain for real-time controllers. The conga-SMX95 SMARC modules offer 2x Gbit Ethernet with TSN for synchronised and deterministic network data transmission, LPDDR5 (with inline ECC) for data security. For display connectivity the new modules offer DisplayPort as the standard interface and the still widely used LVDS display interface. For direct camera connectivity the modules have 2x MIPI-CSI.

congatec also offers an extensive hardware and software ecosystem as well as comprehensive design-in-services for simplified and accelerated application development. These include, among other things, evaluation- and production-ready application carrier boards and custom-tailored cooling solutions. In terms of services, congatec offers comprehensive documentation, training and signal integrity measurements for application development.

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Ever feel like the only constant in the data center industry is that things are always changing? You’re not alone. From rising densities to evolving environmental policies, there’s never a shortage of change in our field. Navigating this constant change is especially difficult for large enterprises with legacy infrastructures.

We believe that every data center should have its own digital twin to ensure data center teams are ready to adapt to these rapid changes. We put together an eBook that details several case studies from large enterprises in various industries with different pain points and needs that have found great success using Cadence data center digital twin solutions.

Aerospace Enterprise Dramatically Improves Data Center Performance

One of the world’s largest aerospace companies uses Cadence Reality DC Digital Twin for data center performance efficiency modeling and asset management. They initially needed a data center solution to help address cooling, compliance, and low operating efficiency issues. Before implementing Cadence Reality DC Digital Twin, the data center management team was using a manual, trial-and-error approach to IT installation planning, which was both time consuming and risky. At one point, they even experienced an outage.

This large aerospace enterprise began using Cadence Reality DC Digital Twin to perform engineering simulations. They built and calibrated models to form a digital twin model of their data halls, enabling them to see what would happen in different scenarios by testing them in the virtual model. Using Cadence’s built-in library items, which include cabinets, IT devices, and more, the aerospace enterprise could easily simulate how new deployments would perform in their data center environment. They also used Cadence Reality DC Digital Twin to examine cooling and power capacities and search for greater efficiency gains.

With help from Cadence tools and services, the company was able to simulate the changes in IT equipment in a virtual environment to understand the performance impact. Cadence Reality DC Digital Twin enabled the company to be more proactive in their approach to data center management. This simulation-based methodology for IT installation planning enabled the data center management team to adjust environments for maximum performance before installation. The company has quantified that it has been able to reduce power consumption and increase performance by 30-40% (depending on the data center).

This large enterprise now operates its data centers more reliably and sustainably, reducing power consumption without increasing environmental compliance risk, so much so that the management team was able to drop PUE at one of their data centers from PUE 4 to 1.6. They continue to use Cadence data center software to assess new deployments and efficiently perform monthly IT asset audits. Implementing Cadence Reality DC Digital Twin into their workflow for these purposes saves their engineering department a significant amount of time. Cadence Reality DC Digital Twin helps this aerospace enterprise overcome the challenge of fulfilling the competing objectives of compliance and efficiency at the same time.

Effectively Design and Operate Enterprise Data Centers

Large global companies in automotive, healthcare, finance, and aerospace are using Cadence data center solutions to effectively design and operate their data centers.

Danielle Gibson | Cadence Systems

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Ganga Sivaraman | Product Marketing Director, Optical Patterned Wafer Inspection | Applied Materials

Semiconductor production is an expensive and complex endeavor. The journey from R&D to high-volume manufacturing is a race, and whoever crosses the finish line first wins competitive advantage in terms of revenue, market share and profitability. Advanced chips are built up one layer at a time, and each of the billions of individual features must be perfectly patterned and aligned to create working transistors and interconnects with the best performance and power characteristics.

In both advanced logic and memory, the number of processing steps is increasing as we add more and more complexity to the latest and greatest chips. Defects introduced in between the process steps directly impact wafer yields and ultimately slow down an economy that runs on silicon. Patterned wafer inspection – the scientific study of defects across the entire wafer manufacturing lifecycle – has always been critical to controlling and perfecting the chipmaking process. However, as chip structures become ever smaller and the process grows in complexity, the way we inspect leading-edge chips needs to evolve.

More Complexity Calls for More Inspection

Management guru Peter Drucker is credited as saying, “what gets measured, gets managed.” Often, fab inspection strategies analyze data from a limited number of intermediate and end-of-module steps. But as process complexity increases, and techniques like multipatterning invite minor defects to become magnified, we need to gather data from all key process modules. Otherwise, defects and process drift may not become visible until engineers are faced with costly and inexplicable yield issues.

When determining where and how often to inspect, the right technical answer is, “more is better.” At the same time, fab managers need to control costs, which is why they must deploy an optimized approach that uses the most cost-efficient tools for the job. A mix and match of optical inspection approaches – both brightfield and darkfield – is the key for cost-effective yield monitoring and control.

Brightfield and darkfield wafer inspection technologies are complementary and typically used for addressing different application needs. Brightfield primarily collects reflected light, with the source of illumination oriented perpendicular to the wafer’s surface. Light bounces off the surface and returns a “bright” image showing a realistic view of the patterned features on the wafer, similar to the way a mirror shows a clear and precise reflection of a person’s face. With darkfield, the wafer can be imaged using either normal illumination or oblique illumination, where the light is at an angle to the wafer surface. Darkfield focuses primarily on collecting scattered light. When a beam of light encounters angled or rough surface features within a chip’s nanoscale patterns, its trajectory is altered. Collecting this scattered light produces images of the edges of 3D structures against a dark background.

Brightfield inspection primarily targets high-sensitivity applications and delivers lower inspection throughput. Darkfield is suited to lower-sensitivity applications — typically targeting defects of 20nm or greater in size — and delivers very high inspection throughput.

Wafer Inspection at a Crossroads

New challenges in advanced logic and memory are calling for a new playbook for optical wafer inspection. Chipmakers are telling us that they need new capabilities which maintain the high throughput and low cost-of-ownership characteristic of darkfield inspection while delivering optimal sensitivity for both 3D surface defects and surface pattern defects.

For example, defects in the sub-20nm range have traditionally been considered too small to have a significant impact on wafer yield and therefore have not been a priority for optical inspection. As the critical dimensions of devices continue to shrink, defects in this size range become more problematic. If left undetected, these small particles can block etching and cause pattern defects in subsequent steps. Traditional darkfield tools do not have the resolution to detect these critical defects of interest.

Likewise, when creating the vias that connect vertical layers of metal interconnects, tiny micro-scratches can be left behind in the oxide layer after chemical mechanical planarization (CMP) steps. These scratches must be detected early before they turn into bridge defects when the vias are filled with metal.

Applied Materials has a strong presence in the optical inspection market with its Enlight wafer inspection system which offers brightfield and darkfield modes. We believe chipmakers who are pushing the leading edge of logic and memory will eventually need a next-generation darkfield tool that can deliver a new combination of darkfield application sensitivity and throughput.

Based on extensive customer engagements, we are preparing to introduce a state-of-the-art wafer inspection system designed to deliver the industry’s highest darkfield application sensitivity at higher throughput. Our solution is designed to make it cost-effective for chipmakers to inspect more inter-module process steps, enabling them to effectively monitor and control wafer yield. With more than 10 customer engagements in 2023, we have successfully demonstrated our capabilities in high-throughput wafer inspection in a variety of processing modules such as deposition, CMP, lithography, etch, implant and a few custom modules.

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Courtesy: Anritsu

In our increasingly mobile-dependent world, the need for reliable wireless coverage and capacity inside buildings has become paramount.  This blog will delve into the concept of In-Building Wireless (IBW) systems, their significance, and the various architectures and technologies used to provide enhanced network coverage and capacity indoors. Understanding these systems is crucial as they are the backbone of our modern communication, enabling seamless connectivity in our homes, offices, and public spaces.

The demand for IBW systems becomes apparent when the existing macro network fails to meet the need for coverage and capacity within buildings adequately.  However, challenges such as building structure, low emissivity glass, and RF barriers created by adjacent buildings can lead to subpar coverage.  Overcoming these challenges is a testament to the importance and complexity of IBW systems, especially in densely populated urban areas and high-density venues like stadiums and convention centers.

The funding and ownership models for IBW systems are diverse, reflecting the various benefits derived from enhanced wireless services.  Operators sometimes negotiate leases with building owners, taking on the costs of designing, installing, and maintaining the IBW system in exchange for exclusive coverage rights.  In other cases, building owners are mandated by regulations to provide public safety coverage and cover the entire cost of the IBW system.  Cost-sharing is arranged in venues like shopping centers and stadiums, where both the building owner and mobile operators benefit, showcasing the adaptability and flexibility of IBW solutions.

IBW solutions are not one-size-fits-all. They can be categorized into three main architectures, each with its own unique features and benefits: Distributed Antenna Systems (DAS), Distributed Radio Systems (DRS), and Distributed Small Cells (DSC).  The choice of architecture is a critical decision, depending on various factors, including coverage objectives, budget, venue size, number of operators, and required technologies, emphasizing the importance of this selection process.

DAS is the most common method used to achieve IBW coverage and capacity.  It involves distributing signals from RF sources throughout the venue using passive components like coaxial cables, splitters, and directional couplers.  DAS can accept RF inputs from various signal sources, making it technology-neutral and suitable for multi-operator applications.  There are different types of DAS, each with its own unique characteristics: passive DAS, active DAS, hybrid DAS, and digital DAS, each with its strengths and weaknesses.

Passive DAS

Passive DAS uses only passive components to distribute signals throughout the venue.  It relies on coaxial cables, splitters, and directional couplers to divide the signal and achieve the desired signal level at each antenna.  Signal sources for passive DAS can include repeaters, bi-directional amplifiers (BDAs), and small cells.  Passive DAS is cost-effective, reliable, and suitable for multi-operator systems.  However, it can be challenging to modify after installation and may encounter passive intermodulation (PIM) issues.

Active DAS

Active DAS involves converting signals to light and distributing them over fiber optic cables to radio units distributed throughout the venue.  It offers greater flexibility in modifying sectorization and fine-tuning radiated power levels. Active DAS requires higher upfront costs but provides benefits such as easier cable routing, longer battery life for mobile users, and the ability to monitor system performance.  It is suitable for large venues and multi-operator applications.

Hybrid DAS

Hybrid DAS combines active and passive components to mitigate costs while maintaining performance.  It uses active components for long-distance signal transport and passive components for signal distribution within each zone.  Hybrid DAS provides a balance between cost, performance, and maintainability, making it suitable for multi-operator systems serving large and complex venues.

Digital DAS

Digital DAS utilizes radios manufactured by the DAS equipment provider and can accept RF inputs from various network equipment manufacturers.  It uses digital transport protocols to distribute signals and offers dynamic resource allocation within the venue.  Digital DAS supports centralized radio access network (C-RAN) and enables the backhaul of IP traffic.  It provides flexibility and scalability, making it suitable for venues with changing coverage requirements.

Conclusion

In-building wireless systems are crucial in providing reliable coverage and capacity inside buildings. The choice of IBW architecture depends on various factors, including coverage objectives, budget, and venue size.  Passive DAS, active DAS, hybrid DAS, and digital DAS each have their strengths and weaknesses, and the selection should be based on the specific requirements of the application.  As mobile devices evolve and data demands increase, IBW systems will continue to play a vital role in meeting the growing demand for indoor wireless connectivity.

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Few methods for analog to digital conversion are more “mature” than the classic combination of a voltage-to-frequency converter (VFC) with a counter. VFC digitization is naturally integrating, so good noise rejection is inherent, as is programmable resolution (if you want more bits, just count longer). Unfortunately, and for the same reason, high conversion speed is not. Accurate, high resolution, microsecond VFC conversion times are defiantly difficult, but at least millisecond rates are definitely doable as shown in this design idea. 

Nearly four decades ago (in his Designs for High Performance Voltage-to-Frequency Converters), famed analog guru Jim Williams cataloged five fundamental techniques for voltage to frequency conversion. First on his list, described as “most obvious”, was the “Ramp-Comparator” type. Since I’ve always been a big fan of the obvious, the simple VFC shown in Figure 1 is a variation on that basic theme. It’s adapted for operation from a single supply rail, with convenient and flexible differential bipolar inputs, and acceptable linearity while running at frequencies up to 200 kHz. Here’s how it works.

Figure 1 A Ramp-Comparator style 200 kHz VFC that operates from a single supply rail, with differential bipolar inputs, and an acceptable linearity.

Wow the engineering world with your unique design: Design Ideas Submission Guide

A2, R1, and Q2 combine to make a precision (Q2 α~0.998) current sink with Q2 collector current:

Ic2 = (V1 –V2)/R1 = 100µA(V1 –V2)

Non-inverting input V1 can range from 0 to (2 – V2), has a nicely high input impedance (>1 TΩ) and a low bias current (10 pA). Inverting input V2 has a lower impedance (10 kΩ) but will accept a voltage span from as positive as V1 to as negative as (V1 – 2). If only one input is used, the other should simply be grounded. Zero offset is about 200 µV (0.01%).

As shown in Figure 2 (yellow trace), Ic2 ramps 1-nF timing capacitor C1 from its reset voltage of 3.5 V down to the 2.5-V trigger level provided by voltage reference U1. The ramp time required to do this is given by:

T = C1(3.5 – 2.5)/Ic2 = C1R1/(V1 – V2)
= 1nF 10k/(V1 – V2) = 10µs/(V1 – V2)
Fout = 1/T = 100kHz (V1 – V2) < 200kHz

Figure 2 VFC oscillation waveshapes where: Vc1 is the VFC timing ramp, Fout is the output to counter, and A1p5 is the comparator’s non-inverting input.

Comparator A1’s inverting input is connected to C1, while its non-inverting input watches the 2.5-V reference. When the Vc1 ramp descends to 2.5 V, a sequence of (quite quick) events are set in motion.

First, A1’s output transitions toward 5 V, completing the move at 30 V/µsec in about 160 ns, the speed being enhanced by positive feedback via C4. This provides an output pulse (Figure 2 green trace) on Fout and turns on Q3 to begin the ramp-reset recharge of C1. Meanwhile C3 couples Q3’s output to D1, reverse biasing the diode and temporarily diverting Ic2 away from C1, which creates the funny little flat spots seen on Figure 2’s yellow and red traces. More on this later.

C1’s recharge current is routed via Q3’s emitter to Q1’s base, driving Q1 into saturation, accurately pulling R3’s top end to +5 V and thereby A1’s non-inverting input (pin 5) to 2.5(R5/(R3 + R5)) + 2.5 = 3.5 V (Figure 2 red trace). C1 recharge continues until A1 pin 5 reaches pin 6’s 3.5 V, whereupon A1 switches back to 0, turning off Q3 (fast because Q3 never saturates) and completing the Fout pulse.

Meanwhile, Q3’s turnoff has removed base drive from Q1, allowing it to recover from saturation (which takes about 500 ns consisting mostly of storage time), turn off, and release R3. This allows A1’s pin 5 to return to U1’s 2.5-V reference, where it waits for the end of the next timeout and VFC cycle.

It also dumps integrated Ic2 charge accumulated on C3 during ramp reset through D1 onto C1. The D1 C3 circuit feature thus cancels out an integral nonlinearity error that typically bedevils Ramp-Comparator VFCs due to charge lost during the ramp reset interval. Williams advises about this defect in his analysis of the Ramp-Comparator topology “A serious drawback to this approach is the capacitor’s discharge-reset time. This time, ‘lost’ in the integration, results in significant linearity error…” The D1 C3 connection prevents this nonlinearity by allowing integration of Ic2 to continue uninterrupted during ramp reset, so no time is “lost”. Thanks for the warning, Jim!

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

Related Content

• New VFC uses flip-flops as high speed, precision analog switches
• Inexpensive VFC features good linearity and dynamic range
• “Hippasian” nonlinear VFC stretches dynamic range
• Voltage-to-period converter improves speed, cost, and linearity of A-D conversion
• VFC makes simple capacitance meter

The post Single supply 200kHz VFC with bipolar differential inputs appeared first on EDN.

• Industry’s first use of ruthenium in high-volume production enables copper chip wiring to be scaled to the 2nm node and beyond and reduces resistance by as much as 25%
• New enhanced low-k dielectric material reduces chip capacitance and strengthens logic and DRAM chips for 3D stacking

Applied Materials, Inc. introduced materials engineering innovations designed to increase the performance-per-watt of computer systems by enabling copper wiring to scale to the 2nm logic node and beyond.

“The AI era needs more energy-efficient computing, and chip wiring and stacking are critical to performance and power consumption,” said Dr. Prabu Raja, President of the Semiconductor Products Group at Applied Materials. “Applied’s newest integrated materials solution enables the industry to scale low-resistance copper wiring to the emerging angstrom nodes, while our latest low-k dielectric material simultaneously reduces capacitance and strengthens chips to take 3D stacking to new heights.”

Overcoming the Physics Challenges of Classic Moore’s Law Scaling

Today’s most advanced logic chips can contain tens of billions of transistors connected by more than 60 miles of microscopic copper wiring. Each layer of a chip’s wiring begins with a thin film of dielectric material, which is etched to create channels that are filled with copper. Low-k dielectrics and copper have been the industry’s workhorse wiring combination for decades, allowing chipmakers to deliver improvements in scaling, performance and power-efficiency with each generation.

However, as the industry scales to 2nm and below, thinner dielectric material renders chips mechanically weaker, and narrowing the copper wires creates steep increases in electrical resistance that can reduce chip performance and increase power consumption.

Enhanced Low-k Dielectric Reduces Interconnect Resistance and Strengthens Chips for 3D Stacking

Applied’s Black Diamond material has led the industry for decades, surrounding copper wires with a low-dielectric-constant – or “k-value” – film engineered to reduce the buildup of electrical charges that increase power consumption and cause interference between electrical signals.

Applied today introduced an enhanced version of Black Diamond, the latest in the company’s Producer Black Diamond PECVD* family. This new material reduces the minimum k-value to enable scaling to 2nm and below, while offering increased mechanical strength which is becoming critical as chipmakers and systems companies take 3D logic and memory stacking to new heights.

The latest Black Diamond technology is being adopted by all leading logic and DRAM chipmakers.

New Binary Metal Liner Enables Ultrathin Copper Wires

To scale chip wiring, chipmakers etch each layer of low-k film to create trenches, then deposit a barrier layer that prevents copper from migrating into the chip and creating yield issues. The barrier is then coated with a liner that ensures adhesion during the final copper reflow deposition sequence, which slowly fills the remaining volume with copper.

As chipmakers further scale the wiring, the barrier and liner take up a larger percentage of the volume intended for wiring, and it becomes physically impossible to create low-resistance, void-free copper wiring in the remaining space.

Today, Applied Materials publicly introduced its latest IMS (Integrated Materials Solution) which combines six different technologies in one high-vacuum system, including an industry-first combination of materials that enables chipmakers to scale copper wiring to the 2nm node and beyond. The solution is a binary metal combination of ruthenium and cobalt (RuCo), which simultaneously reduces the thickness of the liner by 33 percent to 2nm, produces better surface properties for void-free copper reflow, and reduces electrical line resistance by up to 25 percent to improve chip performance and power consumption.

The new Applied Endura Copper Barrier Seed IMS with Volta Ruthenium CVD is being adopted by all leading logic chipmakers and began shipping to customers at the 3nm node. An animation of the technology can be viewed here.

Customer Comments

“While advances in patterning are driving continued device scaling, critical challenges remain in other areas including interconnect wiring resistance, capacitance and reliability,” said Sunjung Kim, VP & Head of Foundry Development Team at Samsung Electronics. “To help overcome these challenges, Samsung is adopting multiple materials engineering innovations that extend the benefits of scaling to the most advanced nodes.”

“The semiconductor industry must deliver dramatic improvements in energy-efficient performance to enable sustainable growth in AI computing,” said Dr. Y.J. Mii, Executive Vice President and Co-Chief Operating Officer at TSMC. “New materials that reduce interconnect resistance will play an important role in the semiconductor industry, alongside other innovations to improve overall system performance and power.”

A Growing Wiring Opportunity

Applied is the industry leader in chip wiring process technologies. From the 7nm node to the 3nm node, interconnect wiring steps have approximately tripled, increasing Applied’s served available market opportunity in wiring by more than $1 billion per 100,000 wafer starts per month (100K WSPM) of greenfield capacity, to approximately $6 billion. Looking ahead, the introduction of backside power delivery is expected to increase Applied’s wiring opportunity by another $1 billion per 100K WSPM, to approximately $7 billion.

The new chip wiring products, along with other materials engineering innovations for making future AI chips, will be discussed at Applied’s SEMICON West 2024 Technology Breakfast. The presentation and other materials from the event will be available on the Applied Materials website at: https://ir.appliedmaterials.com on Tuesday, July 9, 2024 at approximately 9:00 a.m. ET / 6:00 a.m. PT.

*PECVD = Plasma-Enhanced Chemical Vapor Deposition

*CVD = Chemical Vapor Deposition

Forward-Looking Statements

This press release contains forward-looking statements, including those regarding anticipated benefits of our new products and technologies, expected growth and trends in our businesses and markets, industry outlooks and demand drivers, technology transitions, and other statements that are not historical facts. These statements and their underlying assumptions are subject to risks and uncertainties and are not guarantees of future performance. Factors that could cause actual results to differ materially from those expressed or implied by such statements include, without limitation: failure to realize anticipated benefits of our new products and technologies; the level of demand for semiconductors and for our products and technologies; customers’ technology and capacity requirements; the introduction of new and innovative technologies, and the timing of technology transitions; market acceptance of existing and newly developed products; the ability to obtain and protect intellectual property rights in technologies; our ability to ensure compliance with applicable law, rules and regulations; and other risks and uncertainties described in our SEC filings, including our recent Forms 10-Q and 8-K. All forward-looking statements are based on management’s current estimates, projections and assumptions, and we assume no obligation to update them.

The post Applied Materials Unveils Chip Wiring Innovations for More Energy-Efficient Computing appeared first on ELE Times.

Author: STMicroelectronics

What questions will ST answer at electronica China 2024? Too often, attendees don’t take the time to step back and ask what challenges they would need to solve or think of the answers they should seek. It’s easy to get caught up in the event’s excitement and the flood of information. That’s why we decided to highlight some of the questions our readers may have and provide answers. Hence, even if members of our community can’t physically attend this event, they will still get tools and ideas that can help them find innovations and efficiency.

What would it take to build an ST car? A powertrain domain controller!

Attendees at electronica China 2024 will probably be surprised when they see the ST car, a small mock-up electric vehicle. The demo aims to show a modern approach to domain controllers by grouping multiple systems under one host MCU. Thanks to its multiple cores and virtualization capabilities, the Stellar P3 can support mid-level integrated electrification applications, while the Stellar P6 could run even more highly integrated electrification systems. We also increased the battery management system from a previous demo to support 800 V and worked to create an ASIL-D-ready system. In a nutshell, we show how ST solution advantages can help design teams shorten the development cycle and gain market shares.

In our demo car, the host MCU runs the onboard charger and DC-DC converter, the vehicle control unit, which is responsible for the relays, pumps, charger-lock, and more, the battery management system, and the inverter. Additionally, we provide solutions for engine management systems (EMS), transmission control units (TCU), thermal management systems, and more. Integrators can focus on the application instead of worrying about how the electronics will work together. The platform we are showing is continuously evolving, and we’ll release a new version before the end of the year. In the meantime, we continue to show how car makers can take advantage of the computational throughput and safety features of a device like the Stellar P.

As readers of the blog will remember from our power liftgate demo, the industry is looking into consolidating resources. It is one of the simplest ways to bring new features to mainstream vehicles. It simplifies development and helps reduce costs by sourcing more components from the same company, which significantly helps with overall pricing. The ST mock-up vehicle is another example of how ST is helping makers jump on the bandwagon. We also try to make critical technologies more accessible, like over-the-air updates, thanks to our phase-change memory, which is capable of increasing its capacity to enable flashing a new firmware without requiring hardware partitioning like A/B memory banks.

How do you promote sustainability? With integrated hybrid photovoltaic, energy storage, and charging solutions!

Too often, cities know they need to implement new energy strategies that combine solar panels, energy storage, and charging solutions. Moreover, car makers must learn to utilize these new systems, which can lead to a lack of cohesion or slow adoption. Consequently, ST is featuring an energy storage and management solution demo at electronica China 2024 that shows how our devices can help deliver power across infrastructures. It uses our third-generation SiC MOSFETS, enhancement mode PowerGaN transistors, high-performance MCUs, galvanic isolation gate drivers, and more to control and protect the entire system. Put simply, it’s about achieving higher efficiency, better stability, and greater reliability than the industry traditionally offers today.

E-meter

It starts with a power line and hybrid platform for e-meters that uses the STM32WL3, which includes two radios and one ultra-low power wireless MCU. The board also comes with the ST8500 programmable powerline modem and the STLD1 driver.

Micro-inverter

Many charging solutions rely on solar energy to further improve their environmental impact. Hence, an efficient micro-inverter that transforms what solar panels capture is critical. That’s why we are featuring a micro-inverter powered by our MASTERGAN1L solution, which is key to such a small factor thanks to its wide bandgap. Additionally, the module runs on an STM32G4, thanks to its high-resolution timers and high-precision ADCs.

Main inverter

To ensure greater efficiency when converting solar energy and distributing it, ST developed an inverter powered by silicon carbide: the SCT070W120G3-4AG and SCT055W65G3-4AG. After 25 years of innovations, ST can offer a 15kW three-phase three-level Active Front End bidirectional PFC converter. We even provide design tools like STPOWER Studio to help engineers design their PCBs quickly.

Battery charging

To send power from the charger to the battery, we offer a couple of systems, both running on an STM32G4. We even provide the STGAP2SICS for SiC MOSFETs, which implements an under-voltage lockout (UVLO) to ensure the safe, stable, and efficient operation of the entire system.

Battery management

Finally, to manage the energy stored in the car’s batteries, we offer the AEK-POW-BMS63EN, a development platform for the L9963E that makes battery management solutions vastly more accessible. Indeed, thanks to its battery holder, its ability to daisy chain up to 31 nodes in minutes, its board dedicated to isolation, and software that helps take advantage of its features, engineers can significantly reduce their time to market.

How do you detect the orientation of a cup and its liquid level in a short time? Smart Cup Detection

 

It’s a complex problem because it requires fast computing, vision, and other sensors to determine where the cup is and how much liquid is in it. Or, one could just use the VL53L7CH or VL53L8CH time-of-flight sensors from ST. That’s what we will show at electronica China 2024 with a demo of a simulated coffee machine that can measure 64 different zones, represent the data in a compact normalized histogram, and enable the creation of a machine learning algorithm capable of detecting if the cup is upside down, off-center, absent, its height, and how much liquid it contains.

The only significant difference between the VL53L7CH and VL53L8CH is that the former has greater coverage and field of view for applications that monitor a larger area. The demo uses an X-NUCLEO-53L8A1 development board and a 3D-printed housing shaped like a coffee machine. Put simply, it showcases how integrators can create a complex detection system with few components and processing requirements, making this technology highly accessible.

The post electronica China 2024: 3 questions and a slew of solutions appeared first on ELE Times.

I find the white too bright. I think I am stuck using a permanent marker instead. I believe that is 4,470 ohms. submitted by /u/traisjames [link] [comments]

I touched the back of a 40kHz ultrasonic transducer. submitted by /u/Oceanmaan1 [link] [comments]

Sensors: The Key Driver of Automotive Innovation

Since the 20th-century introduction of semiconductors in automobiles, sensing technologies have steadily expanded. Initially aimed at enhancing powertrain efficiency, sensors like ABS, ESC, and airbags have become indispensable due to increasing safety priorities. Technological advancements have transitioned these innovations from luxury vehicles to mid-range and budget models, creating a multi-billion-unit industry. In 2023, 6.5 billion automotive sensors were shipped globally, generating $9.3 billion in revenue. With a 7% revenue CAGR from 2023 to 2029, the market is expected to reach $14.3 billion, with 8.8 billion sensors shipped worldwide. The automotive industry is poised for massive transformations in all four car domains:

1. Powertrain and Electrification: The industry is shifting from internal combustion engine (ICE) cars, which constituted 91% of production in 2019, to electrified cars, expected to represent 43% of production by 2029. The Powertrain and Electrification sensor market will exceed $1.4 billion by 2029, growing at a 3% CAGR from 2023 to 2029. Electrification will drive critical changes in the sensor landscape, creating new applications and phasing out others.
2. ADAS and Safety: Cars are becoming more intelligent, with sensors like cameras, LiDARs, and radars enabling cars to understand and react to their environment. The ADAS and Safety segment is projected to generate $8 billion in revenue by 2029, making it the largest segment.
3. Infotainment and Telematics: This sector is driven by increased functionality and in-cabin comfort, with customers demanding better entertainment options. It is projected to achieve a 7% CAGR from 2023 to 2029, surpassing $2.9 billion by 2029.
4. Chassis and Others: To enhance passenger safety, send valuable data to the ADAS computing unit, and eliminate hydraulic parts, sensor volumes are expected to grow at a 3% CAGR from 2023 to 2029. Revenue from this segment is expected to reach almost $1.9 billion by 2029.

Advancements in ADAS, autonomous driving, and electrification, alongside widespread sensor adoption, are set to transform automotive sensor technology. This will lead to substantial industry reorganization and supply chain changes, necessitating strategic business planning and partnerships to capitalize on emerging opportunities.

pic courtesy: Yole Group The Changing Automotive Market: Impacts on Sensor Manufacturers

The growth or decline of sensor manufacturers will depend on their strategic positioning within the market as vehicles increasingly embrace electrification and advanced driver assistance systems (ADAS) and safety features.

• ICE Applications: Suppliers of sensors used in traditional ICE applications (e.g., engine pressure sensing, emission control, engine management systems) will face declining demand. This impact will become more pronounced by the decade’s end, especially with the 2035 ban on new ICE cars in Europe.
• New Prospects: Suppliers of MEMS pressure sensors and gas & particle sensors, such as Bosch, TE Connectivity, NXP, and Infineon, will find new opportunities in thermal runaway and CO2 sensing applications. Preventing thermal runaway at the battery level is critical for OEMs, and CO2 sensing is becoming a key in-cabin comfort feature.
• Magnetic and Temperature Sensors: Suppliers like Allegro Microsystems, Melexis, Infineon, and Sensirion will see significant opportunities. Monitoring current and temperature parameters is essential for understanding EV performance, leading to robust revenue growth for these players.

The increased presence of ADAS and safety components will primarily impact companies involved in image, radar, and LiDAR sensors.

• Safety Applications: As airbags and ESP become standard in nearly all vehicles, the expansion of MEMS accelerometers and inertial combo/IMUs will depend on vehicle sales growth. This trend is expected to generate substantial sales volumes for leading players such as Bosch, Murata, NXP, and STMicroelectronics.
• Image and Radar Sensors: These sensors are projected to experience significant growth due to the expanding adoption of Autonomous Emergency Braking (AEB) features in semi-autonomous vehicles.

pic courtesy: Yole Group Projected Future Technological Developments Spanning All Car Domains

Though electrification and ADAS & safety are primary drivers, technology will evolve in all car domains.

1. Powertrain and Electrification: Increasing battery capacities and advancing 800V batteries will drive the adoption of magnetic (isolated) technologies for current sensing in components like OBC, DC/DC converters, inverters, and power modules. Magnetic sensors will replace shunt sensors due to their lack of galvanic isolation. Additionally, maintaining optimal battery temperature is crucial for performance, safety, and lifespan. Magnetic sensors on thermal valves will regulate cooling or heating fluids more precisely, keeping sensor content per BEV around $15 per car.
2. ADAS and Safety: CMOS image sensors will evolve to increase frame rates, dynamic range, and temperature resistance, meeting the needs of Tier-1s and OEMs. Radar sensors will advance with 4D imaging radar achieving a 1° angular resolution. LiDAR technology will improve in range, transitioning from avalanche photodiodes to more sensitive SPADs and SiPMs. The introduction of FMCW LiDAR by the end of the decade could change the technology landscape, with semiconductor content for ADAS and Safety sensors per car growing from $51 in 2023 to $82 in 2029.
3. Infotainment and Telematics: Integration of sensors for comfort features will increase. MEMS sensors will improve phone call quality and enable noise-canceling functionalities. Capacitive sensors will replace physical buttons, and radar technology will be used for occupant monitoring. Environmental sensors will enhance in-cabin air quality.
4. Chassis and Others: Innovations will focus on brake and drive-by-wire technologies to eliminate hydraulic components. Magnetic sensors will be essential for pedal position sensing and motor position monitoring. Intelligent TPMS modules will measure tire pressure and provide insights into tire quality and vehicle load. Additionally, applications for monitoring driver’s seating position and making slight adjustments during extended journeys will emerge.

pic_courtesy: Yole Group

 

Citations from Yole Group

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Courtesy: Analog Devices

Today’s automobiles are becoming increasingly sophisticated, especially with the advancement of self-driving technology. This includes features such as automated steering, acceleration, and braking, as well as convenient options like touchscreen controls and voice commands. Cars are now capable of performing tasks autonomously, such as activating high beams, parking themselves, detecting blind spots, and applying brakes to prevent accidents. These capabilities are made possible by electronic control units (ECUs) that connect to various parts of the vehicle, supporting systems like advanced driver assistance, power management, infotainment, and security. These parts must meet strict manufacturer specifications to ensure safety and performance. However, how does the automotive company ensure these requirements are being met?

One approach is through car part pairing, which involves cryptographic authentication and association between different vehicle subsystems to establish mutual trust. In simpler terms, car part pairing is a unique association of a part with a vehicle. So, trust in automotive components, such as sensors and actuators, requires OEM approval, provability, and secure control throughout their lifecycle.

You may wonder, what are the benefits of car part pairing for the automotive company? Let’s explore a few in this blog.

Benefits of pairing parts with cryptographic authentication and association of vehicle subsystems Knowing the Benefits

The primary benefit of pairing is to provide strong cryptographic identification and authentication of car parts. By securely linking specific car parts to specific vehicles, manufacturers can ensure that only authorized parts are used, improving safety and preventing fraud, theft, and counterfeiting. Risks are mitigated through this authentication scheme, as any replacement part must now be authentic and valid, eliminating counterfeit or stolen parts.

Another benefit of pairing is the ability to store and attest to the lifecycle of a car part, including calibration, manufacturing steps, maintenance, mounting, calibration, decommissioning, and relevant traceability information. Cryptographic methods using digital signatures provide formal proof of the car part’s state. This additional information can be used by the car’s ECUs to manage otherwise authentic parts, such as rejecting improperly calibrated OEM ADAS cameras or parts mounted into another car without proper authorization. This attestation of a part’s lifecycle reduces the risk of using invalid parts, even if they are authentic, provided the ECU is secure enough to prevent bypassing part verification.

Ensuring secure lifecycle data is crucial for trust. Tampering with this information could allow refurbishment of worn-out or malfunctioning parts, posing safety risks or using stolen parts. By employing cryptographic-based access control, manufacturers can ensure only authorized parties can modify the car part’s lifecycle information memory and other data used to bind the part to an ECU. Approved OEM dealers can then replace a part, associate it with the car chassis, and perform necessary calibrations.

Applying the Benefits

One of the notable benefits lies in the application of cryptographic methods to establish the authenticity of a car’s installed ADAS camera in relation to the car’s ECU. This is commonly achieved through the utilization of the Elliptic Curve Digital Signature Algorithm (ECDSA) for challenge-response authentication with prior certificate verification.

Challenge-response authentication between ADAS camera and vehicle ECU

To provide clarity, challenge-response authentication involves the following steps:

1. Challenge Initiation:The ECU verifier initiates the process by sending a “challenge” (a randomly generated number) to the ADAS prover.
2. Response Generation:The ADAS prover, using a private key, digitally signs the received random number, generating a “response.” Additional information, such as unique identification data, life cycle data and calibration data, may be concatenated with the random number for contextualization.
3. Transmission of Response: The ADAS prover then transmits the generated “response” to the ECU.
4. Verification Process:The ECU verifier runs a verify, with the public key, using the prover’s identification data and ECDSA signature response to ascertain authenticity. Importantly, this authentication process is bidirectional, capable of being performed in both directions.

This framework ensures robust authentication, affirming the integrity of the ADAS camera’s association (i.e., proving it is paired) with the ECU.  Subsequently, cryptographic methods can prove a car’s mounted ADAS camera is paired with proper car’s ECU.

All these benefits listed in this blog can be assured with the DS28C40 Automotive I2C Authenticator IC. Analog Devices offers both the software and experience to implement car part pairing, contributing to building safer automobiles.

The post Securing the Automotive Intelligent Edge appeared first on ELE Times.

Recently, I was working on a project that needed a couple of LEDs on its front panel for status indication. I realize many, if not most, pieces of electronic equipment now use graphic LCDs, Bluetooth to phones or tablets, or connections to PCs for informational display. But some things are way too simple for that, like on/off indicators when a temperature reaches its setting or when there is a short detected. The project I was working on did not need a graphic LCD or other major display but needed a little more than a one-color LED. I needed multiple colors—two wasn’t enough, not even three—four would work. I could use a three-color four-pin LED and mix colors, but I was not enamored with the mixes. What I wanted was a simple solution that would give me multiple color choices along with brightness control.

Wow the engineering world with your unique design: Design Ideas Submission Guide

I used one of those multicolor LED strips before, on a parking assist project and it worked well and was easy to get working. Also, it only needed one digital I/O line (besides the power and ground) which is important if you’re running low on I/O pins. But for this new project, I didn’t need a strip of 100 LEDs, I just needed two LEDs. Also, I was looking for a small solution like a 5MM T-1 3/4 LED. So, what if I took one of the LEDs from the long strip and 3D printed a holder in the shape of a 5mm LED?

First let’s take a quick look at the LED strip I’m talking about. Just search for a “WS2813B LED Strip”. You’ll see that this has 3 pins: +5v, ground, and one data line. You’ll find firmware drivers for a number of processors, but I chose a library called FastLed created for Arduino boards as that was used on the project. Typically, you would use FastLed to talk to each of the LEDS on a strip through the single data line as the data is forwarded to the next LED in line so the data propagates to the last LED. In FastLed, the data is nicely abstracted so, along with many other functions, you can set each individual LED in the strip with unique red, green, and blue (RGB) values. R, G, and B are each given a value from 0 to 255. This allows for a vast number of colors and brightness’s that can be used (essentially all colors of the rainbow). If you prefer using hue, saturation, and value (HSV) in lieu of RGB values, there is a function call for that as well. These LED strips also allow you to cut them to any length. When one is cut out, it is a single LED with solderable patterns on both in and out of the LED, see Figure 1.

Figure 1 Single LEDs cut from a WS2813B LED strip, the wires can be soldered to the single LED, connecting the data line from the Arduino.

Let’s look at how to use these. Wires can be soldered to the single LED making sure to connect the data line coming from the Arduino to the side with the arrow pointing to the LED chip, let’s call this the left side. If you want to test this out quickly, connect the power and ground to an Arduino Nano’s +5v and GND. Then, connect the LED’s data line (middle trace) to D7 on the Nano. Next, load the program in Listing 1 into the Nano and run it. You should see the color changing and then repeating. (Note, you may need to load FastLed.h using the Arduino Library Manager.) See “Program Listing 1” below:

1 #include <FastLED.h> 2 3 #define LED_PIN 7 4 #define NUM_LEDS 1 5 6 CRGB leds[NUM_LEDS]; 7 uint8_t h = 0; 8 9 // ====================== SETUP ===================== 10 void setup() { 11 FastLED.addLeds<WS2812, LED_PIN, GRB>(leds, NUM_LEDS); 12 } 13 14 // ====================== LOOP ===================== 15 void loop() { 16 17 for (h = 0; h < 256; h++) { 18 leds[0] = CHSV ( h, 255, 255); // Set values in the LED 19 FastLED.show(); 20 delay(40); 21 } 22 }

Obviously, this isn’t a panel mount LED yet, so let’s look at the adapter that holds the single LED. Provided in the download location are 3D files for printing the adapter parts. For the 5-smm LED adapter, print the main part of the adapter and the back cover.

First place the cut LED in the slot at the bottom of the adapter (LED chip facing the domed head). This is then held in place by the back cover that slides over the LED (see Figure 2). There is no need for adhesive; in fact, don’t peel off the plastic exposing the sticky back on the LED.

Figure 2 Parts and mounting of the LED into the adapter (a link to the 3D design files for these parts can be found at the end of this article).

The adapter’s main body is printed with a transparent filament (or resin if you’re using that type of printer). I used a transparent PLA and a layer height of 0.12 mm. I tested different percentages for infill and found 15% gave me good light transmission. The sliding back cover can be printed in any color; I used grey PLA and a 0.12 mm layer height.

The top of this adapter is essentially a 5 mm LED shape and dimensions so it can be used with commercial panel mount LED holders. If you’d rather, the LED fits nicely, and snuggly, into a 5 mm hole when using a 3D printed front panel with a 5 mm printed hole—I’ll show an example later.

I also designed an adapter with a square lens, made for panel mounting in a 16×16 mm hole in a 3D printed panel. It is assembled in a similar fashion (Figure 3).

Figure 3 Parts and mounting of the LED into the square adapter (a link to the 3D design files for these parts can be found at the end of this article).

Note that after some testing, the infill of 15% again gave the best light transmission while spreading the light across the full surface. But this is subjective and you may want to try different infill percentages and a different number of bottom layers (the face of the adapter is the bottom of the print).

To test these adapters, I design a test stand that holds one square adapter and two 5 mm adapters. It also allows for the mounting of three potentiometers to adjust colors and brightness. First let’s look at the schematic (Figure 4).

Figure 4 Schematic of the string lights-to-LED adapter where the 5v is supplied by a USB connection to the Arduino Nano and the potentiometers are connected to the three analog inputs to digitally read their positions.

As you can see, it’s pretty simple. There is no power supply as 5v is supplied by a USB connection to the Arduino Nano. The potentiometers are connected to three analog inputs so we can digitally read their positions. The LEDs share power and ground. Also, the D7 pin of the Nano is routed to the first LED, the square one. This should be a connection to the labeled D1 trace, with the arrow, (left side) on the LED strip. Then connect the right side D1 trace the next LEDs D1 with the arrow, (left side). Finish by connecting the right side D1 to the last LEDs left side D1. See this arrangement in Figure 5.

Figure 5 The LED wiring for the test stand where the D7 pin of the Nano is routed to the first LED.

This ordering of the LEDs is used in the c code as the LED wired directly to the Nano’s D7 pin will be addressed with index “0”. The LED connected next will be addressed as index “1”, and the last LED as index “2”.

Now, after 3D printing the test stand’s two parts, it can be assembled using 2 screws as per the schematic and as seen in Figure 6. The square lens can be inserted into the test stand then the next 5-mm LED into the upper hole in the test stand. The last LED can be inserted into the lower hole after installing a bezel. This bezel can be printed from the download files, or it can be a commercial bezel.

Figure 6 The 3D printed test stand to test the effectiveness and esthetics of the adapters. The RGB settings or HSV settings can be adjusted with the control knobs using specific programs.

Using various demonstration programs supplied in the download, you can test the effectiveness and esthetics of the adapters. There is a program to allow adjustment of colors and brightness, using the control knobs to adjust RGB settings. With another program, you can adjust HSV settings. As you adjust the knobs, the digital values are displayed on the Arduino serial output so you can find a color and brightness you want to use and record its values.

I think you’ll find that these adapters will come in handy for many of your projects requiring LEDs. You can not only get a huge selection of colors but you can control/adjust all your LEDs from one control pin. Also, you can have an adjustable brightness without using PWM. As for cost, when you buy an LED strip, you’ll find the individual LEDs work out to be only about 10 cents each.

All files for printing the parts (stl, step, 3mf) are provided in the download location, as are extra pictures, the BOM, and more information. The download can be found at:

• https://makerworld.com/en/models/531239#profileId-448069
• https://www.thingiverse.com/thing:6614089

Damian Bonicatto is a consulting engineer with decades of experience in embedded hardware, firmware, and system design. He holds over 30 patents.

Phoenix Bonicatto is a freelance writer.

 Related Content

• LED status indication battery charger
• Simple battery-status indicator uses two LEDs
• Redirecting dynamic indication segment to a separate LED
• An LED display adapted for DIY projects
• DIY LED display provides extra functions and PWM
• Exploring software-defined radio (without the annoying RF)—Part 2

The post A simple, full color upgrade for your LED indicators appeared first on EDN.

EMITE and Rohde & Schwarz continue their collaboration to enhance EMITE’s Over-the-Air (OTA) measurement solutions by fully integrating the latest test capabilities of the R&S CMX500 multi-technology, multi-channel one-box signaling tester. The integration enables besides support of LTE, FR1 and FR2 also full compliance with the cutting-edge WLAN standard IEEE 802.11be as well as 5G RedCap.

EMITE’s state-of-the-art over-the-air chambers can now be combined with the latest sophisticated testing features of the R&S CMX500 one-box signaling tester from Rohde & Schwarz. The radio communication tester offers a wide range of device testing capabilities, supporting cellular technologies such as LTE, 5G NR FR1 frequency range up to 8 GHz and FR2 millimeter wave frequency range up to 50 GHz, including the latest 5G RedCap technology. It also supports non-cellular technologies, including the latest Wi-Fi 7, all in a single instrument. As a consequence of this collaboration, EMITE’s customers obtain a comprehensive environment for accurately assessing the performance of Wi-Fi 7 as well as 5G Red Cap devices.

EMITE’s enhanced OTA chambers are fully equipped to handle the rigorous testing requirements of current and future wireless technologies. The next step of the collaboration is looking at integrating test capabilities for NB-IoT NTN and NR NTN, which are already covered by the R&S CMW500 and R&S CMX500.

The IEEE 802.11be standard, Wi-Fi 7, is the next generation of Wi-Fi technology, designed for extremely high data throughput that far surpass its predecessor, the current IEEE 802.11ax (Wi-Fi 6/6E). With tens of gigabits of data per second and low latency, it meets the growing demand for ultra-high-definition video streaming, as well as immersive virtual reality and augmented reality applications.

RedCap is a 5G technology defined in 3GPP Release 17. As a reduced-functionality version of 5G, it has significantly lower cost compared to 5G eMBB. It is characterized by mid-range data throughput, low power consumption, low complexity and the ability to support a large number of devices. This makes it particularly attractive for IoT applications.

David A. Sánchez-Hernández, CEO at EMITE, said: “EMITE is committed to quality and customer satisfaction. Therefore, we are excited to upgrade our testing chambers with the R&S CMX500 enabling our customers to extend capabilities to include the IEEE 802.11be standard and Red Cap devices. This partnership underscores our dedication to delivering superior testing solutions that meet the evolving demands of the telecommunications sector.”

Christoph Pointner, Senior Vice President of Mobile Radio Testers at Rohde & Schwarz, said: “We are happy to bring our collaboration with EMITE to the next level. EMITE’s customers can confidently deploy their devices for the latest technologies, knowing their products have been rigorously tested to meet the highest standards of reliability and efficiency, made possible through the integration of our tried-and-tested R&S CMX500 one-box signaling tester into the EMITE OTA chambers portfolio.”

For more information on the R&S CMX500, visit: www.rohde-schwarz.com/product/cmx500 . For more information on EMITE, visit: www.emite-ing.com

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Efficient Power Conversion Corp (EPC) of El Segundo, CA, USA — which makes enhancement-mode gallium nitride on silicon (eGaN) power field-effect transistors (FETs) and integrated circuits for power management applications — says that its GaN intellectual property rights have been upheld for the third time in three months...

The MAXER-2100 illustrates AAEON’s commitment to innovation across client bases.

Leading provider of advanced AI solutions AAEON (Stock Code: 6579), has released the inaugural offering of its AI Inference Server product line, the MAXER-2100. The MAXER-2100 is a 2U Rackmount AI inference server powered by the Intel Core i9-13900 Processor, designed to meet high-performance computing needs.

The MAXER-2100 is also able to support both 12th and 13th Generation Intel Core LGA 1700 socket-type CPUs, up to 125W, and features an integrated NVIDIA GeForce RTX 4080 SUPER GPU. While the product’s default comes with the NVIDIA GeForce RTX 4080 SUPER, it is also compatible with and an NVIDIA-Certified Edge System for both the NVIDIA L4 Tensor Core and NVIDIA RTX 6000 Ada GPUs.

Given the MAXER-2100 is equipped with both a high-performance CPU and industry-leading GPU, a key feature highlighted by AAEON upon the product’s launch is its capacity to execute complex AI algorithms and datasets, process multiple high-definition video streams simultaneously, and utilize machine learning to refine large language models (LLMs) and inferencing models.

Given the need for latency-free operation in such areas, the MAXER-2100 offers up to 128GB of DDR5 system memory through dual-channel SODIMM slots. For storage, it includes an M.2 2280 M-Key for NVMe and two hot-swappable 2.5” SATA SSD bays with RAID support. The system also provides extensive functional expansion options, including one PCIe [x16] slot, an M.2 2230 E-Key for Wi-Fi, and an M.2 3042/3052 B-Key with a micro SIM slot.

MAXER-2100_3DFront_02

For peripheral connectivity, the server boasts a total of four RJ-45 ports, two running at 2.5GbE and two at 1GbE speed, along with four USB 3.2 Gen 2 ports running at 10Gbps. In terms of industrial communication options, the MAXER-2100 grants users RS-232/422/485 via a DB-9 port. Multiple display interfaces are available, thanks to HDMI 2.0, DP 1.4, and VGA ports, which leverage the exceptional graphic capability of the server’s NVIDIA GeForce RTX 4080 SUPER GPU.

Given the combined thermal output of its 1000W power supply, 125W CPU, integrated NVIDIA GeForce RTX 4080 SUPER GPU, and potential additional add-on cards, the MAXER-2100 is remarkably compact at just 17″ x 3.46″ x 17.6″ (431.8mm x 88mm x 448mm). This is made possible by a novel cooling architecture utilizing three fans, prioritizing airflow around the CPU and key chassis components. Fan placement within the MAXER-2100 chassis also serves to reduce system noise.

AAEON has indicated that the system caters to three primary user bases – edge computing clients, central management clients, and enterprise AI clients.

The first of these refers to organizations and businesses that require scalable, server-grade edge inferencing for applications such as automated optical inspection (AOI) and smart city solutions.

“The MAXER-2100 can be used to run multiple AI models across multiple high-definition video streams simultaneously, via either its onboard peripheral interfaces or scaled up via network port integration.” Associate Vice President of AAEON’s Smart Platform Division Alex Hsueh said. “Its high-performance CPU, powerful GPU, large memory capacity, and high-speed network interfaces make it well-equipped to handle the acquisition and processing of 50-100+ high definition video streams, making it an ideal solution for applications requiring real-time video analysis.” Hsueh added.

AAEON’s second target market is those seeking remote multi-device management functions, such as running diagnostics, deploying or refining AI models, or storing local data on edge devices. On the topic of the product’s suitability for such clients, Mr. Hsueh remarked, “With the MAXER-2100, our customers can utilize K8S, over-the-air, and out-of-band management to update and scale edge device operations across smart city, transportation, and enterprise AI applications, addressing key challenges faced by our customers when managing multiple AI workloads at the edge.”

For enterprise AI clients, AAEON indicates that by leveraging the MAXER-2100, companies can effectively harness their data to build and deploy advanced AI solutions powered by LLMs. This includes applications in natural language processing, content generation, and customer interaction automation. The key benefits that the MAXER-2100 brings to such setups are the security provided by data being stored and processed at the edge and the system’s ability to train and refine inference models during operations.

For more information and detailed specifications, please visit the MAXER-2100 product page, or contact your AAEON representative via the contact form on the AAEON website.

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Accenture has acquired Excelmax Technologies, a Bangalore, India-based semiconductor design services provider. The acquisition further enhances Accenture’s growing silicon design and engineering capabilities. Terms of the transaction were not disclosed.

Excelmax provides custom silicon solutions used in consumer devices, data centers, artificial intelligence (AI) and computational platforms that enable edge AI deployments, to clients in the automotive, telecommunications and high-tech industries.

The semiconductor market is experiencing a surge in demand for silicon design engineering, driven by the proliferation of data centers and the increasing use of AI and edge computing. This is further propelled by the growing consumer appetite for electronics, which is driving new investments in the chip design space.

“With the rapid evolution of new technologies like generative AI and the growth of connected products, more intricate, specialized chips with enhanced performance and efficiency are required,” said Karthik Narain, group chief executive—Technology at Accenture. “Our acquisition of Excelmax enhances our expertise across every aspect of silicon design and development—from concept to production—so we can help our clients fuel innovation and drive growth.”

Mahesh Zurale, global lead – Advanced Technology Centers Global Network, Accenture said, “Accenture’s acquisition of Excelmax Technologies brings approximately 450 highly skilled silicon professionals to our Advanced Technology Centers in India. With the global demand for silicon solutions on the rise, India is becoming a hotbed for chip design. Growing our skilled talent in the country across physical and RTL design, verification, emulation, and firmware engineering will help us expand our capabilities in the silicon design space and accelerate innovation for our world-wide clients.”

Founded in 2019, Excelmax brings comprehensive semiconductor solutions from high level design to detailed physical layout ready for manufacturing, and full turnkey execution. The company adds approximately 450 professionals to Accenture in key areas such as emulation, automotive, physical design, analog, logic design and verification, expanding Accenture’s ability to help global clients accelerate edge computing innovation.

“Our focus has always been on developing the best talent to deliver tailor-made solutions for our global clients that help them build and maintain competitive advantage,” said Shekhar Patil, founder & CEO, Excelmax Technologies. “Joining Accenture enables us to remain at the forefront of innovation, providing new and exciting opportunities for both our clients and our people.”

This acquisition follows the addition of XtremeEDA, an Ottawa, Canada-based silicon design services company, in 2022.

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