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Karnataka Forest Department, WRRC, and Bosch Global Software Technologies collaborate to open the first Elephant Care Facility in the state

ELE Times - Wed, 12/06/2023 - 09:19

Set up a safe and healthy environment for elephants at Lakshmisagara, Kolar District

  • The facility is overseen by the Wildlife Rescue and Rehabilitation Centre (WRRC), a non-profit organization providing a dedicated team of seasoned veterinarians and mahouts, committed to delivering optimal care to elephants
  • BGSW is an instrumental partner, enriching the facility’s essential infrastructure such as a CCTV surveillance network, fencing enclosures, and an off-grid solar-powered system among others
  • The The Elephant Care Ecosystem project is a testament to what can be achieved when the government, non-profits, and the corporate sector come together with a shared vision (The Elephant Care Ecosystem project)

Bangalore, TBD – The Karnataka Forest Department, in partnership with the Wildlife Rescue and Rehabilitation Centre (WRRC) and Bosch Global Software Technologies (BGSW), has opened the first Elephant Care Facility in the state. The facility is located in Lakshmisagara, Kolar District and is surrounded by over 100 acres of reserve forest. It has been established in response to the growing number of elephants in private ownership, which are being exploited in captivity.

There are over 180 captive elephants in Karnataka alone, many of whom are subjected to abuse and neglect in private custody. The new facility will provide the rescued elephants with a safe and healthy environment. They will have access to nutritious food, adequate water, as well as a space to walk and socialize. Trained professionals will also provide regular medical care to the elephants.

V Yedukondalu, Deputy Conservator of Forests, Kolar, Karnataka Forest Department, said, “The Elephant Care Facility is a historic moment for Karnataka, highlighting the need to address the challenges faced by captive elephants, many of whom have endured hardship and neglect. Our cultural and natural heritage includes these majestic beings, who deserve care, respect, and freedom. This facility is not just a refuge but a commitment to ensuring that every rescued and needy elephant in our state has a chance to thrive in an environment that mirrors their natural habitat as much as possible, providing them with a healthy and natural diet, socialising opportunities, and the chance to indulge in other natural behaviours which aren’t possible in captivity. We are proud to collaborate with WRRC and BGSW in setting a benchmark for ethical wildlife conservation.”

The facility is managed by the Wildlife Rescue and Rehabilitation Centre (WRRC), a Bengaluru-based non-profit organization. WRRC has a team of experienced veterinarians and mahouts who are dedicated to providing the elephants with the best possible care.

Elephant Care Facility 2

Suparna Baksi Ganguly, Honorable President and Co-founder, WRRC, “Elephants, as majestic and gentle creatures, deserve the utmost dignity and respect. This facility is a testament to our unwavering commitment to their welfare. We are deeply grateful to our partners, Bosch Global Software Technologies and the Karnataka Forest Department, for their dedicated support in making this safe haven a reality. Together, our efforts have set a new precedent for ethical wildlife conservation across the nation.”

Bosch Global Software Technologies is an instrumental partner, enriching the essential foundation by securing the facility through setting up a CCTV surveillance network (2 areas under CCTV surveillance) and fencing enclosures (3000 square ft), an elephant weigh bridge with 10-tonne capacity to understand progress on health parameters, an off-grid solar-powered system to ensure energy self-sufficiency (Hybrid solar Inverter 5KW, 500L capacity solar water heater and 36W solar lights), two container cabins converted into a research and welfare hub to enable wildlife observation and studies, with residential capability, and a training and sensitization hub to promote awareness and capacity building of relevant stakeholders.

 “Bosch has been committed to sustainable development of the environment including animal conservation efforts since 2016. Our Corporate Social Responsibility project has helped the Kolar elephant camp to take significant strides towards establishing a safe space for rehabilitation of elephants in need. In this enriched ecosystem elephants can finally be free from pain, suffering and can exercise a greater degree of autonomy in choosing their companions and activities, than they would otherwise. “

Jacob Peter, Executive Board, Senior VP, Mobility R&D, BGSW.

The Elephant Care Ecosystem project is a testament to what can be achieved when the government, non-profits, and the corporate sector come together with a shared vision. It is not just a sanctuary for elephants but also a precedent for wildlife conservation and ethical treatment across the nation.

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Rohde & Schwarz is first to deliver a 5G FR1 A-GNSS OTA test solution approved by CTIA Certification

ELE Times - Wed, 12/06/2023 - 08:44

The R&S TS8991 over-the-air (OTA) test system from Rohde & Schwarz is the first to be approved by CTIA Certification for testing 5G A-GNSS antenna performance. This solution measures the performance of the global navigation satellite system (GNSS) receiver in a wireless device. This is critical because Assisted-GNSS is used for E911 emergency calls over 5G.

The R&S TS8991 from Rohde & Schwarz has been approved by CTIA Certification for testing 5G A-GNSS antenna performance. This marks a significant milestone that establishes the R&S TS8991 as the first 5G FR1 A-GNSS OTA test solution to be approved by CTIA Certification.

The latest Test Plan for Wireless Device Over-the-Air (OTA) Performance Version 4.0.x from CTIA Certification added 5G FR1 EN-DC to the existing A-GPS L1 OTA specification. The previously published Version 6.0.x added 5G FR1 SA, A-GPS L5 and A-Galileo E1, which are soon to start the CTIA Certification validation process.

The R&S TS8991 test system from Rohde & Schwarz is a turnkey solution for meeting CTIA Certification OTA test requirements for 2G/3G A-GPS, 4G LTE A-GNSS and now also 5G A-GNSS. This system consists of the R&S CMX500 5G one-box signaling tester, the R&S SMBV100B satellite simulator and an anechoic wireless performance test chamber (WPTC). It features a high degree of system integration and is easily upgradeable. Every component is controlled using the R&S CONTEST software, allowing for fully automated OTA measurements in compliance with CTIA Certification Test Plans.

The R&S CMX500 is a one-box solution for all mobile device testing applications. It supports transmitter and receiver RF parametric measurements as well as testing for data throughput, audio quality and battery life. This solution is integrated into the R&S TS8991 antenna performance test system to provide signaling capabilities to a device under test (DUT) as well as measure the receive sensitivity and transmit power. The R&S CMX500 covers the most advanced requirements for wireless communications testing and supports the latest 3GPP and IEEE technologies.

The R&S SMBV100B is a satellite simulator that supports all major satellite navigation technologies and satellite constellations. With the CMX500 location-based services, it supports all 3GPP-based Assisted GNSS technologies.

The R&S WPTC OTA Test Chamber is a high-performance OTA anechoic test chamber available in a range of chamber sizes for different testing needs.

Christoph Pointner, Senior Vice President of Radio Mobile Testers and Test Systems at Rohde & Schwarz says: “We are committed to providing customers with reliable, high-performance OTA test systems that meet a wide range of different testing needs. This is why we are thrilled that the R&S TS8991 is the first 5G FR1 A GNSS OTA test solution approved by CTIA Certification. The TS8991 OTA test systems are equipped with market-leading Rohde & Schwarz instrumentation and software – ensuring optimal performance and seamless system integration.”

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Infineon introduces new CoolMOS S7T with integrated temperature sensor

ELE Times - Wed, 12/06/2023 - 08:30

Infineon Technologies launches its new CoolMOS S7T product family with an integrated temperature sensor to improve the accuracy of junction temperature sensing. The integration of these products has a positive impact on the durability, safety, and efficiency of many electronic applications. The CoolMOS S7T is best suited for solid-state relay (SSR) applications for enhanced performance and reliability due to its superior RDS(on) and the highly accurate, embedded sensor.

Since SSRs are fundamental components in various electronic devices, customers can benefit in many ways from a superjunction MOSFET with an integrated sensor in the same package. Infineon’s innovative approach improves the relay’s performance and ensures reliable operation even under overload conditions. The integrated temperature sensor provides up to 40 percent greater accuracy and ten times faster response time than a standard independent on-board sensor located at the drain. Additionally, the monitoring process can be performed individually within a multi-device system for improved reliability.

The CoolMOS S7T enables optimal utilization of the power transistor, resulting in enhanced performance and precise control of the output stage. Compared to electromechanical relays, the total power dissipation can be improved up to two times, while current solid state triac solutions are more than 5 times less efficient. Improved efficiency and the ability to handle higher loads help in reducing power consumption and energy costs.

Unique output stage performance, coupled with a significant overcurrent threshold, bolster relay reliability and minimizes the risk of failure and downtime. The rugged switching solution also ensures safer operation. As a result of the MOSFETs increased robustness, the life of the relay is improved, leading to less frequent replacement. Ultimately, all of these benefits translate into lower maintenance costs.

Availability

Engineering samples of the CoolMOS S7T in TOLL and starter kits will be available in February 2024. More information is available at www.infineon.com/s7.

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ROHM Offers the Industry’s Largest Library of LTspice Models at Over 3,500 by Adding SiC and IGBTs

ELE Times - Wed, 12/06/2023 - 07:37

Improves design convenience by allowing designers to incorporate power devices in circuit simulations

ROHM has expanded the library of the SPICE model lineup for the LTspice of its circuit simulator. LTspice is also equipped with circuit diagram capture and waveform viewer functions that make it possible for designers to check and verify in advance whether the circuit operation has been achieved as designed. In addition to the existing lineup of bipolar transistors, diodes, and MOSFETs, ROHM has added SiC power devices and IGBTs that increases its number of LTspice models to more than 3,500 for discretes (which can be downloaded from product pages). This brings the amount of coverage of LTspice models on ROHM’s website to over 80% of all products – providing greater convenience to designers when using circuit simulators that incorporate discrete products, now including power devices.

In recent years, the increasing use of circuit simulation for circuit design has expanded the number of tools being utilized. Among these, LTspice is an attractive option for a range of users, from students to even seasoned engineers at well-known companies. To support these and other users, ROHM has expanded its library of LTspice models for discrete products.

Besides product pages, ROHM has added a Design Models page in October that allows simulation models to be downloaded directly. Documentation on how to add libraries and create symbols (schematic symbols) is also available to facilitate circuit design and simulation execution.

Going forward, ROHM will continue to contribute to solving circuit design issues by expanding the number of models compatible with various simulators while providing web tools such as ROHM Solution Simulator to meet growing customer needs.

 

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First Year Engineering Student - Just Built My First Significant Circuit

Reddit:Electronics - Wed, 12/06/2023 - 05:18
First Year Engineering Student - Just Built My First Significant Circuit

The circuit displays a continuous irregular repeating countdown; 4, 7, 2, 1, 4, 7, 2, 1, etc. It uses 3 J-K flip-flops, a decoder, a 7-segment LED display, and a few resistors. It is hooked up to a function generator that generates a 1 Hz pulse wave and a DC voltage source. I determined the proper J-K connections with Karnaugh mapping. 3 more years to go.

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Single supply function generator outputs buffered squares, triangles, and sines

EDN Network - Tue, 12/05/2023 - 17:00

The traditional analog function generator with its customary triple-threat ensemble of square, triangle, and sine waveform outputs is a familiar tool on electronics lab benches. It’s also a classical design exercise. Generally, the square and triangle are easy, so the problem is how to generate an acceptably accurate sine wave.  This usually involves some method of conversion of the triangle. Figure 1’s generator circuit employs the popular integrator solution, but with a useful twist.

Figure 1 Quad highspeed RRIO TLV9064 op-amp performs as comparator, integrator, and clipper while sipping single-digit milliwatts from a single, flexible, power source.

A1 and A2 combine to form a conventional multivibrator generating symmetrical (around Vdd/2) squares and triangles. The peak-to-peak amplitude of the latter is fixed by R5 and R6 at 0.909Vdd, and the frequency of both is settable over two decades (and perhaps a bit more) by R1C1.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Conversion of A2’s triangles into a (more or less) serviceable approximation of a sine wave could now be, and popularly would be, accomplished by simple integration of A2’s output. But the downside of unadorned integration is found in that ominous phrase “more or less”. Unfortunately, the resulting approximation, while definitely looking a lot like a sinusoid, would quantitatively differ from a true sine function by the +/-3% of full-scale, mainly third harmonic, error shown in Figure 2.

Figure 2 Simple integration of triangle would result in +/-3%, 3rd harmonic sine error.

 But maybe we can do better.

A little experimentation and simulation revealed that simple truncation of the triangle at +/- 2/3rds of full-scale (Vpp = 0.67Vdd) prior to integration yields a surprising 3x improvement in sinewave accuracy, shown in

Figure 3’s plot of the residue error function.

Figure 3 Imposing trapezoidal truncation of triangle at +/- 67% prior to integration reduces peak sine error to less than +/-1% of mainly 5th harmonic.

I say “simple” because we already have an extra amplifier (A3) available. So, it only costs two extra resistors (R7 and R8) to generate the clipped at 67% trapezoidal waveform. This does a better job of approximating the dV/dT of a true sine, reducing error to the +/- 1% 5th harmonic squiggle shown in Figure 3.It’s interesting to note that 1% sine accuracy is similar to the performance of the famous Intersil ICL8038 function generator chip. But that was achieved only after in-circuit trimming. The circuit in Figure 1 needs none. Not to brag.

Integration now occurs in A4, with the DC restoration R9C3 network providing zero stability, and R2 controlling sine amplitude. 

This last is an important feature because the fact that the sine waveshape results from an integration makes its amplitude inherently inversely proportional to frequency. Therefore, because frequency is unaffected by the sine amplitude adjustment but not vice-versa, the most efficient way to set these two parameters is to adjust frequency first, then set sine amplitude as required. This avoids a potentially time wasting (and frustrating) iteration.

A final comment on Figure 1’s circuit: The TLV9064 is particularly suited for the A1 comparator and the A3 clipper because of its remarkably fast 200 ns overload recovery time. This is unusual performance for an op-amp, particularly such a low power one as the 9064.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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LPDDR flash: A memory optimized for automotive systems

EDN Network - Tue, 12/05/2023 - 14:07

Next-generation automotive systems are advancing beyond the limits of currently available technologies. The addition of advanced driver assistance systems (ADAS) and other advanced features requires greater processing power and increased connectivity throughout the vehicle. On top of this, automotive OEMs are expanding the user experience (UX) to introduce innovations that improve convenience, efficiency, and safety for drivers and passengers.

This combination of new and advanced features is straining the capacity of traditional automotive E/E architectures (see Figure 1). To address this need, OEMs are consolidating more functions into fewer systems by taking a domain/zonal architectural approach. And these systems often need substantially more non-volatile memory for code storage than is available as embedded flash integrated into processors.

Figure 1 A domain/zonal architecture approach consolidates many safety-critical functions and must be able to process huge amounts of data in real-time as well as store a significantly larger code image. Source: Infineon

Furthermore, many of these consolidated systems are safety critical, and must eliminate both performance and memory access bottlenecks to meet real-time performance deadlines. Finally, automotive systems need to be able to operate in a wide range of harsh environments, including extreme temperatures.

More code storage for software-defined vehicles

The evolution and consolidation in automotive architectures is driving the industry toward software-defined vehicles. The central car computer will connect to the cloud but also needs to have enough centralized processing to be completely autonomous from the cloud for critical driving operations. From a functional standpoint, car functionality will shift to be more service-oriented and maintain a higher level of safety and security.

Part of the challenge OEMs face is the need for more code storage because all this added functionality and connectivity in turn require more complex software. Software is stored in non-volatile memory so it can be updated in the field. Ideally, when there is enough embedded flash on a processor to hold all the software, the processor executes code directly from this on-chip flash in a process known as execute-in-place (XiP). This provides the best execution performance while maintaining system flexibility.

However, when there is not enough embedded on-chip flash, software must be stored in an external flash. But flash bus latency and limited throughput prevent external flash from accessing the system-on-chip (SoC) to XiP at speed. For this reason, the software is copied from flash to faster DRAM to achieve the necessary performance, an approach known as ‘shadow code’.

But a shadow code approach comes at the cost of additional DRAM memory—plus associated board space—to store the copy of the software. In addition, system start takes longer, which negatively impacts user experience, or worse, operational safety.

For next-generation automotive systems, neither approach is sufficient. Specifically, to meet the real-time requirements of a consolidated domain or zone, a higher performance, highly integrated SoC processor is required. To achieve such a level of integration, these SoCs must utilize smaller manufacturing process nodes.

This enables SoCs to provide all the integrated capabilities with a single chip in a cost-effective manner. However, as manufacturing process nodes shrink to 22 nm and below, it becomes expensive to integrate embedded flash in the densities required. Thus, an alternative to embedded flash for XiP is needed.

Overcoming external memory bottlenecks

To be able to take full advantage of high-performance SoCs built using smaller process nodes, engineers need to once again turn to external NOR flash. Figure 2a shows one approach to using external flash where the SoC can XiP from an embedded flash while an external NOR flash is used as a memory extension.

Figure 2 A traditional execute from embedded flash architecture uses an external NOR flash as a memory expansion to hold software that is loaded into embedded flash for XiP. This approach is limited by embedded flash capacity as well as xSPI throughput (left). A next-generation execute from external flash architecture combines the flexibility of an embedded flash approach with the performance of DRAM (right). Source: Infineon

The problem with the former approach is the limited bandwidth of the xSPI bus used to interface between the embedded flash and external NOR flash. Standard xSPI throughput is 400 MB/s, and even at 16-bits, xSPI at 200 MHz can only achieve 800 MB/s maximum throughput. This falls substantially short of what is required to support real-time code execution.

In addition, xSPI uses a multiplexed command/address/data bus that negatively impacts effective throughput because code reads cannot be pipelined efficiently. Furthermore, LVCMOS leaves little room for advancement beyond 200 MHz.

Figure 2b shows an alternative approach that directly executes code from external flash. This approach eliminates the need for embedded flash by utilizing a high-performance low power double data rate (LPDDR) interface that enables XiP from external flash.

LPDDR: Proven interface finds a new use case

LPDDR is a memory interface commonly used with DRAM for high-performance data access. The LPDDR interface has been adapted to work with NOR flash and optimized for efficient XiP from external NOR flash. With a throughput potential of many gigabytes per second, LPDDR flash provides the performance of DRAM with the non-volatile reliability and flexibility of embedded NOR flash. It’s the best of both worlds.

One of the factors that makes the LPDDR NOR flash interface a compelling technology is that its physical layer is completely compatible with the LPDDR standard interface. This compatibility reduces the risk associated with adopting a new interface as the signal integrity of LPDDR has already been proven in the market in myriad real-world applications and operating environments.

At a high level, the LPDDR NOR flash interface is focused on code storage and real-time XiP for applications where code is written once and read many, many times. Thus, the interface is optimized to increase read performance overwrite efficiency. Again, the physical layer is untouched, so optimizations have been implemented in the controller protocol. These optimizations are tailored to meet the requirements of high-performance applications like autonomous vehicles.

The LPDDR advantage

The benefits of LPDDR NOR flash over SDRAM and xSPI-based NOR flash architectures are substantial. Take the example of the LPDDR4-based SEMPER X1 NOR flash, which is specifically optimized for operation in automotive applications. In comparison to standard NOR flash, it provides the throughput of LPDDR to support XiP using an external NOR flash (Figure 3).

Figure 3 SEMPER X1 has been optimized for operation in automotive applications and to support XiP using an external NOR flash. Source: Infineon

The entire memory architecture has been designed for functional safety and reliability to ensure uninterrupted operation in applications where failure is not an option.

To understand the advantages of LPDDR flash over both xSPI NOR flash and DRAM, consider how the SEMPER X1 utilizes the LPDDR4 interface to improve real-time performance (see Figure 4).

Figure 4 The LPDDR4 interface optimized for data read access provides superior performance compared to LPDDR4 SDRAM and xSPI NOR flash, as illustrated by these performance comparison figures. Source: Infineon

XiP from external memory becomes possible through several different optimizations as shown in Figure 4:

  1. Separating read from write

SEMPER X1 NOR flash has multiple ports: a quad SPI for write/read and an LPDDR4 dedicated for read only. Eliminating write operations from the LPDDR4 port enables the interface to be further optimized than if it also supported write operations.

  1. Faster training

Eliminating the write path in LPDDR eliminates the need for write DQ training. This results in 100x faster training compared to LPDDR4 SDRAM.

  1. Faster read commands

When accessing DRAM, it takes four commands to retrieve data. The LPDDR4 interface of SEMPER X1 uses a simpler format, requiring just two commands (Figure 5). Combined with no banking restrictions, row activation, or refresh compared to LPDDR4 DRAM, SEMPER X1 delivers 5x faster random read transactions. It’s also 5x faster than xSPI NOR flash for a 32-byte single read operation from command request to read data.

Figure 5 LPDDR flash requires just two commands—NVR-1 and NVR-2—to complete each read operation. Source: Infineon

  1. Separate command from data

A typical xSPI interface is 8 pins, and both commands and data must share that bus. LPDDR, in contrast, has separate pins for commands and data, enabling the efficiency of command pipelining. The result is 20x better performance for pipelined random read transactions compared to xSPI NOR flash.

  1. Data bus efficiency

The underlying embedded charge trap (eCT) technology in this memory ensures that there is no need for periodic refresh to interrupt throughput. That enables it to achieve up to 99% bus efficiency at 125° C, a 14% improvement compared to LPDDR4 DRAM.

  1. Better determinism

Determinism is a measure of the consistency of performance. Zone controllers often have many cores operating in parallel to provide the necessary processing capacity required for consolidated automotive systems. When multiple cores share memory, accesses by one core can create delays in accesses by all the other cores. Such delays can impact real-time reliability. A memory with multiple banks allows each core to have its own bank. This minimizes memory access interference and interdependence between cores, thus improving overall determinism and reliability.

  1. Zero downtime updates

With multiple banks, firmware-over-the-air (FOTA) updates can be loaded into an alternate memory bank. Once the update is complete and has been authenticated, the system can switch over to the alternate bank, allowing for a seamless transition to the update with zero system downtime.

  1. Better power efficiency

LPDDR optimizations impact more than just performance and reliability. Compared to xSPI NOR flash, SEMPER X1 consumes 8x lower read energy per MB while providing 8x higher throughput performance. For high-performance applications, these savings add up fast.

  1. Outperforms shadow code

The ability of LPDDR flash to provide throughput of 3.2 GB/s puts its XiP performance on par with SDRAM using a shadow code approach. In addition, the LPDDR approach requires fewer memory ICs, has faster setup time, and consumes less energy, making it a compelling alternative to SDRAM.

Scalability for the future

A key advantage of LPDDR is that it is a scalable interface that can support the increasing complexity of automotive applications in the future. xSPI is limited in its ability to scale as LVCMOS has little room for advancement past 200 MHz, capping bandwidth at 400 MB/s (x8) and 800 MB/s (x16). In short, xSPI can no longer keep up.

LPDDR4, on the other hand, allows for frequencies up to 1,600 MHz and can scale throughput from 1,600 MB/s to 12,800 MB/s (Figure 6). With this wide range of capacity, LPDDR4 offers the scalability and performance required for XiP in increasingly advanced systems, with newer LPDDR generations providing even more headroom.

Figure 6 xSPI is limited in its ability to scale, capping performance at 800 MB/s (x16). In contrast, LPDDR4 allows for frequencies up to 1,600 MHz and can scale from 1,600 MB/s to 12,800 MB/s, providing the scalability and performance required for XiP in today’s and tomorrow’s increasingly complex automotive applications. Source: Infineon

As the computational load and software complexity of vehicles increase with more automation, greater convenience and advanced user experience, greater code storage is required. Many of these software-defined functions are mission-critical and need real-time code execution to maintain reliability and safety.

To maintain performance and efficiency, today’s automotive applications need a fast underlying memory array to leverage all possible efficiencies. However, at advanced manufacturing process nodes, automotive-qualified embedded non-volatile memory technology faces high cost (die area) and lack of scalability. An external memory approach is required but the needs of the increasingly software-defined architecture of vehicles exceed the capabilities of today’s most advanced xSPI NOR flash, which simply cannot provide real-time XiP performance.

LPDDR is a key technology for next-generation automotive systems, providing an interface to external flash memory with enough performance to enable real-time computing and XiP capabilities for domain and zone controllers. With efficiencies such as 20x faster random read transactions and 8x lower read energy consumption per megabyte, LPDDR enables next-generation vehicles to provide advanced capabilities with enhanced safety and architectural flexibility.

Sandeep Krishnegowda is VP of marketing and applications for flash solutions at Infineon Technologies.

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I think i did something wrong

Reddit:Electronics - Tue, 12/05/2023 - 13:14
I think i did something wrong

Was trying to make a voltage regulator and accidentally hooked up an 80v psu to it (the schematic said it was rated up to 30v)

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How V2G benefits drivers and electricity suppliers

ELE Times - Tue, 12/05/2023 - 12:12

Vehicle-to-grid (V2G) has been a well-known concept since the 1990s when electric vehicles (EVs) seemed poised to become mainstream. However, the electric car revolution was delayed, and V2G’s progress stalled before it even began. There simply weren’t enough EVs on the road.

It was only in the 2010s and 2020s that higher sales of EVs put V2G back in the game as a viable technology. With a growing proportion of our electricity being generated by renewables, the storage and grid-balancing capabilities offered by V2G are coming at just the right time to help utilities manage their increasingly complex systems.

Renewables are unpredictable, so we need a way to store excess energy generated when the wind blows and the sun shines. This enables the grid to have spare energy available to handle short-term peak demands without having to keep costly gas and coal power plants available for occasional use.

However, storing electricity is surprisingly difficult and expensive. Home storage batteries, such as Tesla’s Powerwall, would do the job, but they are a costly solution.

Instead, how about utilizing all the batteries already sitting in our driveways?

Vehicles as energy stores

Using an EV battery to provide electricity to the grid may seem obvious, but it requires the right technology–specifically, the provision of bi-directional charging capability in both the charger and the car.

To ensure interoperability across multiple vendors, the ISO 15118 standard for communication between EVs and charging stations includes specifications for bi-directional charging. Currently, only EVs built to the CHAdeMO charging standard (developed by Japanese carmakers) can handle bi-directional charging, although efforts are underway to add this capability to other standards such as Combined Charging System (CCS).

While Avnet’s primary focus in this article is on V2G, there is also ongoing interest in vehicle-to-home (V2H) and vehicle-to-load (V2L), often collectively referred to as V2X.

V2L enables a vehicle’s battery to power electric devices, such as power tools or lights. V2H allows an EV battery to be used to power the home, ensuring the lights stay on during a power outage or storing power from home solar cells for later household use.

The benefits of V2G Charging your car or charging your home? an-ev-charging-at-home-on-a-drivewayV2G could help you power your home at the end of the day, before recharging the vehicle during the hours of lower grid demand.

Electricity at night is typically much cheaper than during the day due to considerably lower demand. Charging EVs overnight can save car owners a significant amount of money.

Moreover, the reduced demand at night means that a larger proportion of the electricity used for charging comes from renewable sources, as opposed to fossil fuel power plants that may only be activated during peak times. This contributes to utilities’ efforts to lower carbon emissions.

In addition to assisting electricity suppliers in managing peak demands, the energy stored in EV batteries can also help them handle voltage and frequency fluctuations on the grid.

Given the unpredictable nature of renewables, instances of cheap electricity may arise with little notice, such as unexpected windy weather. The V2G system, including any consumer-facing applications, must be flexible enough to respond promptly. EV batteries are well-suited to serve as a nearly instant source of power, available more quickly than activating other power generators.

Commercial issues

While the technology challenges of V2G are well on the way to being solved, the barriers to its adoption are now primarily commercial. Adding bidirectional capabilities to an EV increases cost, and it remains to be seen if enough consumers can be persuaded that it’s worthwhile.

There is also an unresolved issue regarding who bears the cost for the new infrastructure needed for V2G, particularly the systems required to convert between the alternating current (AC) used in the grid and the direct current (DC) used to charge and discharge the EV battery at roadside fast chargers.

Power companies prefer using AC bidirectionally to facilitate the seamless addition of stored energy into their grids. However, automakers are concerned about the costs of adapting vehicle electronics to meet the demanding technical and safety standards of the grid.

Some consumers have expressed concerns that the additional charge/discharge cycles from V2G may accelerate the wear and tear on their EV’s battery, leading to additional costs. Additionally, there are concerns about the round-trip efficiency as AC electricity from the grid is rectified to DC, stored in the car’s battery, discharged from the battery, inverted back to AC again, and delivered back to the grid–with each step resulting in power losses. Charging stations for EVs typically use AC for residential and home chargers, while DC designs are increasingly common for fast chargers at roadside locations.

Governments may intervene to make bidirectional charging compulsory, as demonstrated by California’s proposed Senate Bill 233, which sets a deadline of 2027 for most new EVs and chargers sold in the state to support bidirectional charging. However, such a process may be slow and cumbersome.

System demands for V2G

EV charging presents a complex technical challenge that encompasses various aspects, including communications, security, user interface functions and power conversion. It requires the use of one or more microcontrollers (MCUs) that run physical layer (PHY) and application software. Communication standards utilized may include Wi-Fi, Bluetooth or cellular, with devices like NXP’s IW620 dual-band solution or its OL2385 RF transceiver for sub-GHz protocols.

Ensuring bidirectional charging necessitates robust security systems in both chargers and vehicles, encompassing confidentiality and authenticity. Hardware-based security solutions, such as NXP EdgeLock SE05x/A5000 secure element, offer easily integrated options for system designers. To handle the complexity of keys and certificates, NXP provides EdgeLock 2GO, a fully managed cloud platform.

To expedite development, NXP provides an EV charging station development platform that enables rapid prototyping and system design. This platform allows customers to swiftly load Azure RTOS-based application software onto NXP’s i.MX RT1064 crossover MCU and securely connect the simulated EV charging station to the cloud.

In EV chargers, wide bandgap (WBG) semiconductors like gallium nitride (GaN) and silicon carbide (SiC) offer superior efficiency compared to silicon alternatives. This is particularly crucial in EV chargers. For instance, Renault and the French Alternative Energies and Atomic Energy Commission (CEA) recently introduced a new bidirectional charger supporting V2G, claiming a 30% reduction in energy losses during conversion thanks to the implementation of WBG materials.

Conclusions Your car will have a closer relationship with the grid ev-charger-cable-in-a-car-with-graphic-overlayVehicles will negotiate with the grid to share energy, making sure there is enough energy available during peak periods of demand.

The journey to reach the current state of V2G has been long and challenging. However, the adoption of V2G technology remains slow. While cars like the Nissan Leaf and Ford F-150 Lightning support bidirectional charging, they still constitute a minority. Notably, Tesla has shown reluctance to support bidirectional charging.

However, the future looks more promising. With the rapid increase in the number of EVs on our roads, the time is ripe for V2G technology. The necessary technical solutions are already available, the standards are well-defined, and the demand is growing. Therefore, we should anticipate a significant rise in the prevalence of V2G in the coming years.

HARVEY WILSON
Systems Engineer Professional
(Smart Industry)
Avnet Silica

The post How V2G benefits drivers and electricity suppliers appeared first on ELE Times.

2D Materials in Piezoelectric Nanogenerators (PENGs)

ELE Times - Tue, 12/05/2023 - 09:24

Courtesy: Mouser Electronics

As technology advances, so does the technology that is powering it. Over the years, a number of energy creation, energy storage, and energy harvesting devices have been developed to provide power to large electronic systems and individual electronic devices in a range of ways. As society moves towards Industry 4.0 and the Internet of Things (IoT), there’s an opportunity to create many types of ultra-small devices that can be used for automation and remote monitoring, and telemedicine applications.

Powering small-scale devices—especially in remote applications—requires unconventional self-powering mechanisms to be self-sufficient. In recent years, a number of different small-scale energy harvesters, known as nanogenerators, have gathered interest for powering small-scale devices in medical, remote monitoring, and IoT applications. The small size of these devices means they are not too bulky for the small devices they are powering. Despite their small size, they can still provide enough electricity for many devices to self-charge using their natural operating environment. In some cases, it might also be possible to use nanogenerators for large-scale harvesting—if many individual devices are integrated into a single harvesting system—however, this is something that has not been looked at yet from a widespread research perspective.

While there are a number of different nanogenerators, they are all used in different operating environments because the generation of an electrical charge is often governed by the stimuli in the surrounding environment. One of the more promising, widely talked about, and widely researched nanogenerators is the piezoelectric nanogenerator—often referred to in shorthand as a PENG.

Using the Piezoelectric Effect

PENGs use the piezoelectric effect to generate an electric charge. The piezoelectric effect is when an electrical charge is generated under an applied stress/load on a material. The piezoelectric effect is a reversible effect, so once the stress has been removed, the electrical charge stops. This also means that the piezoelectric effect can work in the other direction where an electrical voltage can be applied to the material, causing the atomic structure of the material to deform and become stress-induced.

In terms of the specific mechanisms, it is the rearrangement of ions at the atomic level—within the solid-state lattice—that generates the piezoelectricity. Most piezoelectric materials are inorganic in nature, and when they aren’t, they have some form of crystal structure (inorganic materials have this also). This means that (mostly) the piezoelectric has a regular and repeating array of well-ordered cations and anions within its atomic lattice. It is the deformation of the ions within this regularly patterned lattice that generates an electrical charge. While the material retains an overall neutral charge—the overall charge of the material doesn’t change, only the localized distribution of charges at the atomic level changes.

So, when the stress/load is applied to the piezoelectric material, the oppositely charged ions move from their original positions within the lattice to a point where they lie closer to each other. This rearrangement alters the charge balance within the lattice and induces an external electric field. The effects of the charge imbalance also permeate throughout the material. The result is the appearance of a net charge—either positive or negative—on one of the outer faces of the crystal. This subsequently creates a voltage across the oppositely charged crystal face. The piezoelectric charge can be harnessed, but when the stress stimulus is removed, the crystal lattice returns to its natural state and the voltage ceases.

In certain scenarios—such as the movement of a limb in wearable electronics, the movement of internal organs in implantable electronics, or the movement of the local surrounding environment in remote sensing/monitoring applications, to name a few—movements can create stresses across the piezoelectric material at the atomic scale that can then be harnessed.

In many cases where the PENG is used, the harnessing of the induced stress and the resulting electrical charge can then be used to power a small device that it is attached to. However, in certain situations—mainly sensing—the nanogenerator can act as both the powering device and the sensing device, as the generation of an electrical charge can act as a usable and detectable output for the sensor in load-bearing/stress-sensing situations.

Why 2D Materials Are Showing Promise for PENG Energy Harvesters

2D materials show promise for PENG Energy Harvesters for a number of reasons. First, the inherent thinness and small size of 2D materials enable the creation of ultra-small harvesting devices that are small enough to power the very small nodes in IoT systems, power very small sensors in remote monitoring applications, and charge small-scale implantable or wearable medical devices. By contrast, bulkier materials would create harvesting/power systems that are too large and unfeasible for these types of applications. This is why you often see nanomaterials touted for wearable/implantable electronics, IoT, and remote sensing applications.

Another aspect is the mechanical strength and flexibility of many 2D materials. Because the piezoelectric effect is induced by some level of mechanical deformation, the materials generating the electric current need to be robust and be able to withstand many bending cycles. The inherent thinness of 2D materials means that they have a very high degree of flexibility. While graphene has the highest flexibility, inorganic materials have relatively high flexibility compared to their bulkier counterparts, and other inorganic materials in general. When this flexibility is coupled with high mechanical strength, it means that the 2D materials can withstand a great deal of mechanical stress, leading to PENGs that can withstand many bending cycles, and in turn, be able to produce an electrical charge for longer time periods than when using other materials.

Then, there’s also the ability to exhibit piezoelectric properties. Traditionally, piezoelectric properties are seen in a range of inorganic materials, including natural and synthetic crystal materials, synthetic ceramics, group III-V and II-VI semiconductors, and various metal oxide complexes. Many different 2D materials are also known to exhibit piezoelectric properties, some of which are semiconducting materials. In terms of the materials of interest for PENGs, currently, hexagonal boron nitride (h-BN), various semiconducting transition metal dichalcogenides, group III and IV monochalcogenides, and chemically modified graphene—so that it is more semiconducting in nature rather than fully conducting as it naturally has no electronic bandgap—are the go-to choices.

Factors to Be Aware of with 2D Material PENGs

While the potential for creating PENGs using 2D materials exists, they, like any material, need to be used in the right way. In many cases, the piezoelectricity is only seen in single and few layered 2D materials. Once you get beyond this, the level of piezoelectricity generated is insufficient to power devices. As more 2D layers are added, this diminishing effect has been attributed to the lattice distortion caused by strain and the consequent charge polarization in the crystal. The more layers, the less flexible the 2D material is, so the lower the induced amount of strain, and therefore, the lower the degree of crystal polarization and generated electrical charge.

There have also been some other interesting phenomenon discovered with some 2D materials known as the layer dependence effect. While it’s not applicable to all 2D materials, it’s not only the number of layers that can influence the piezoelectric properties of the 2D material, but also whether there is an odd or even number of layers. This is because, in some cases, an odd number of layers has piezoelectric properties, but once the number of layers becomes even, the other layer becomes counterbalanced leading to piezoresistive properties. This then reverts to piezoelectric properties once another layer is added, and so forth until the layers become too great to exhibit piezoelectric properties anyway

Nevertheless, despite needing to ensure that the 2D materials are used in the correct manner, there are several 2D materials that can be harnessed, including a few materials where their bulkier 3D inorganic counterparts show no piezoelectric properties. There are now also many ways to create single and few layered 2D materials on a commercial level, so these kinds of challenges are not as significant as they would have been even just a few years ago. So, there’s a chance to break away from the traditional piezoelectric materials when it comes to creating these small-scale nanogenerators.

Conclusion

The piezoelectric effect is a common phenomenon in a range of bulk inorganic materials, but it is also observed in a range of 2D materials. 2D materials that can generate a piezoelectric charge that can be used in a range of PENGs for powering small-scale devices. There are a lot of benefits of using 2D materials in PENGs, including high flexibility and mechanical strength, as well as an inherent thinness, and PENGs offer a lot of potential for small-scale energy harvesting in remote applications—be it IoT, monitoring, or medical applications.

 

The post 2D Materials in Piezoelectric Nanogenerators (PENGs) appeared first on ELE Times.

Javelin Missile guidance computer teardown

Reddit:Electronics - Tue, 12/05/2023 - 04:40

https://www.youtube.com/watch?v=11_5TB0-lNw

A French engineer posted his teardown video of the FGM-148 Javelin missile guidance computer.

Absolutely amazing - the cables, the mainboard etc.

Old tech by today's standards. Just curious: As of 2023-2024, would a simple SBC like Raspberry 5 with GPIO do the same work?

submitted by /u/GenericName9173
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Syn470r & SJK 6.758

Reddit:Electronics - Tue, 12/05/2023 - 02:38
Syn470r & SJK 6.758

AliExpress delivered a thousand of those to me by mistake. What's this used for? How to recycle ♻️ it now?

submitted by /u/Vikt724
[link] [comments]

Google’s Chromecast with Google TV: Dissecting the HD edition

EDN Network - Mon, 12/04/2023 - 21:10

At the end of a few-months-ago writeup, wherein I successfully reassembled a 4K-version Google Chromecast with Google TV:

that I’d taken apart earlier in the year, I wrote:

In closing, a foreshadowing. As I mentioned in my earlier teardown, written and submitted for publication in mid-March:

 “Mine’s one of the original 4K resolution-capable units introduced in September 2020, not the newer (September 2022) and less expensive ($29.99 vs $49.99) albeit “only” 1080p-max “HD” model.”

 Well, I subsequently also picked up one of those newer Google Chromecast with Google TV HD (wow, that’s a mouthful!) devices, in late April when Walmart had them on sale for $19.98:

 It looks just like its “4K” big brother, doesn’t it? Makes you wonder if the hardware is identical, and Google just differentiates the two devices solely via software, doesn’t it? There’s only one way to find out; it’s in my teardown pile, and I’ve promised Aalyia it’s near the top of the stack. Stay tuned for the “full monty” coming soon; until then, share your thoughts in the comments.

That time is now! Some upfront if-necessary clarification: while the earlier 4K “CGTV” (for short) supported output video resolutions of, per the published tech specs “Up to 4K HDR, 60 FPS”, this version conversely is “only” capable of “Up to 1080p HDR, 60 FPS”. Strictly speaking, leveraging the terminology commonly found with computer monitors, Google maybe should have called it the “FHD” edition, for 1080p (1920×1080 progressive-scan) “full HD”, since 720p (1080×720 pixel progressive-scan) support is all that’s necessary to claim conventional “HD” capabilities. Further to this point, I should also point out that “FHD” (or “4K”, for that matter) doesn’t also require HDR (high dynamic range) or 60 frame-per-second display output capabilities, both of which both of these device variants also support as feature supersets.

The differentiation continues with the devices’ supported audio and video formats. First, here’s the 4K CGTV:

  • Audio: Dolby Digital, Dolby Digital Plus, and Dolby Atmos via HDMI passthrough
  • Video: Dolby Vision, HDR10, HDR10+, HLG (Hybrid Log-Gamma)

Now for the “HD” version:

  • Audio: Dolby Digital, Dolby Digital Plus, and Dolby Atmos via HDMI passthrough
  • Video: HDR10, HDR10+, HLG (note: no Dolby Vision support in this case)

While the various “4K” version’s A/V enhancements could come solely from different software builds installed on a common hardware foundation, I’ve always suspected that the two versions have unique hardware designs. For one thing, the FCC IDs are different, suggestive of two different hardware platform certifications: A4RGZRNL for the 4K version and A4RG454V for the newer HD version (that said, any Bluetooth, Wi-Fi or other RF broadcast differences between the two products might also result solely from different software builds that selectively enable and tweak various wireless subsystems).

The HD version is also nearly half the price of its 4K sibling; any resultant higher sales volumes might not be enough to counterbalance lower unit profit margin on a common hardware foundation, making a bill-of-materials cost reduction potentially also necessary to hit revenue and profit targets. That all said, why might Google consider basing both product proliferations off a common hardware foundation at all? The advantages here would involve manufacturing line and inventory simplification. Obviously, the end retail packaging for the two versions would need to differ, but they’d be identical right up to the point where final firmware is programmed into a particular device (via the USB-C port, for example) and it’s packaged and shipped either to a retail partner or directly to the customer (for products sold from the online Google Store).

So, which is it in reality: one hardware foundation, or two? Let’s find out. I’m not going to repeat the entire suite of images shown for the 4K device back in May, except selectively to reinforce commonality (or not), so I encourage you to back-reference my earlier writeup for the “full picture” (bad pun intended). But I will as-usual start with some packaging shots post-clear plastic shrink-wrap removal (to preclude annoying camera reflections in the shots). Front (note the “HD” mark in the lower left corner this time):

Left side:

Back:

Right side:

Top:

And bottom, again with varying markings from last time reflective of HD-vs-4K differentiation:

Same contents as last time:

The USB-to-USB C power adapters are the same. 4K version:

And HD version:

As are the remote controls. 4K version:

And HD version:

Now we get to the deviations, specifically the players themselves:

although truth be told, everything looks the same as before (including the ever-present accompanying 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes)…

until you flip the HD unit over and peer closely at the markings stamped on its backside:

Time to dive inside:

Things still look pretty much the same at this point, save for an altered number and pattern of thermal paste imprints. 4K version:

and HD version:

Remove four screws:

and pop off the topside heat sink/Faraday cage, however, and the uniqueness of the PCB this around this time is unmistakable. 4K version:

and HD version:

The pattern of the inner Faraday Cage rim is different in the upper left corner this time, for one thing. Also look at the four quadrants inside the outer Faraday cage. Last time there were notable ICs in the upper and lower right quadrants; that extra blob of thermal paste on the left side was, as I mentioned at the time, to dissipate heat from an IC on the other side of the PCB. This time, three of the four quadrants (also including the upper left) are large-IC-populated.

Clearly, I’m going to need to remove the entire PCB again to get a full comparative picture. Let’s first clean the paste off the ICs and PCB itself:

Now remove the two additional screws holding the HDMI cable in place and attached to the enclosure shell lower half (although I didn’t bother disconnecting the cable itself from the PCB):

And the PCB-plus-cable combo then pops right out of the remainder of the case:

One more heat sink/Faraday cage to go; no screw removals needed this time:

And after some more thermal paste cleanup courtesy of isopropyl alcohol and elbow grease, here’s how the two versions compare from a PCB backside perspective. 4K version:

and HD version:

The types of ICs—system processor and DRAM—are the same. The specifics are where the variance lies. Last time, the system SoC was Amlogic’s S905 and the DRAM was a Hynix H9HCNNNBKUMLHR-NME 16 Gbit LPDDR4-3733 SDRAM. This time, the system SoC is Amlogic’s newer, lower-end S805X2. And the DRAM? Smaller capacity, slightly slower, and from a different supplier: Nanya Technology’s NT5AD256M16E4-HR 4 Gbit standard DDR4-2666 SDRAM.

Back to the PCB front side for one more comparison. 4K version:

and HD version:

As mentioned earlier, the 4K product design includes only two sizeable ICs on this side of the PCB: a Samsung KLM8G1GETF-B041 8 GByte eMMC flash memory and a Broadcom-then-Cypress Semiconductor-now-Infineon Technologies BCM43598 “single-chip IEEE 802.11 b/g/n MAC/baseband/radio with integrated Bluetooth 5.1 compliance”. The nonvolatile storage chip in the upper right quadrant is unchanged for the HD generation, albeit rotated, but the wireless connectivity is now supplied by a NXP Semiconductors 88W8987 in the bottom right, originally intended by its supplier (per Google’s cache) for automotive applications, interestingly. And that “new” IC in the upper left? It’s another SDRAM, this one from Micron Technology, the MT40A512M16TB-062E (identified by a D8BPK code stamped atop it) 8 Gbit DDR-3200 device.

One DRAM for code execution, and the other for a video-decode buffer? That’s my guess. Let me know your thoughts on this or anything else in the comments! ICs aside, the hardware designs are otherwise largely identical, including (beyond already-mentioned bits) their reset switches, status LEDs and various PCB-embedded antennae. I’ll eventually tackle reassembling this HD device to fully functional “new” condition, as with its 4K sibling, but for now I’ll keep it in pieces so I can answer any other questions you all might have about its insides.

Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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The post Google’s Chromecast with Google TV: Dissecting the HD edition appeared first on EDN.

Development board

Reddit:Electronics - Mon, 12/04/2023 - 19:31
Development board

This development board was provided to me in my college during the labs for trying out various circuits. It had so many options available but I never really got to know about a few except the basic breadboard part, power supply, input/output ports and the seven segment display. The first time I saw this, I was really excited about working on it and it was a very good experience.

submitted by /u/shirosaki42
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Renesas Electronics Unveils RISC-V Based 32-bit CPU Core with Impressive Performance Metrics

ELE Times - Mon, 12/04/2023 - 13:32

In a significant development, Renesas Electronics Corporation, a prominent semiconductor company, has officially introduced a cutting-edge 32-bit CPU core built upon the open-standard RISC-V instruction set architecture (ISA). This latest addition to Renesas’ microcontroller portfolio, known for its RX Family and RA Family based on the Arm Cortex-M architecture, expands the company’s offerings in the rapidly evolving landscape of embedded systems.

The newly developed RISC-V CPU core is versatile, serving as a primary application controller, a secondary core in system-on-chips (SoCs), on-chip subsystems, or within deeply embedded Application-specific Standard Products (ASSPs). Renesas boasts a remarkable performance metric of 3.27 CoreMark/MHz, surpassing comparable architectures. Furthermore, its silicon area implementation enhances cost-effectiveness by minimizing both operating and standby leakage currents.

This CPU core provides customization options through the RV32 ‘I’ or ‘E’ option, allowing optimization based on specific application requirements. Renesas has integrated several RISC-V ISA extensions, including the M extension for optimized multiplication and division operations, the A extension for atomic access instructions, the C extension for compressed instructions to conserve memory space, and the B extension for bit manipulation.

The RISC-V ISA’s flexibility empowers designers to tailor elements according to their unique use cases, optimizing power consumption, performance, and silicon footprint. Notable features include a stack monitor register to detect and prevent stack memory overflows, enhancing the robustness of application software.

In terms of architecture, the CPU includes a dynamic branch prediction unit for efficient code execution, supporting compact Jtag debug interfaces suitable for microcontrollers with limited pins. Additionally, a register bank save function improves response latency and enables real-time behaviour in embedded devices. For enhanced system insights, an instruction tracing unit is available.

Building on its history of innovation, Renesas has previously introduced 32-bit voice-control and motor-control ASSP devices, along with the RZ/Five 64-bit general-purpose microprocessors (MPUs) based on CPU cores developed by Andes Technology Corp. The company is currently in the sampling phase, providing devices based on the new core to select customers. Renesas anticipates launching its inaugural RISC-V-based MCU and accompanying development tools in the first quarter of 2024.

The post Renesas Electronics Unveils RISC-V Based 32-bit CPU Core with Impressive Performance Metrics appeared first on ELE Times.

Renesas Unveils the First Generation of Own 32-bit RISC-V CPU Core Ahead of Competition

ELE Times - Mon, 12/04/2023 - 13:26

New RISC-V Core Extends Renesas’ Industry-Leading Embedded Processing Portfolio

Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, announced today that it has designed and tested a 32-bit CPU core based on the open-standard RISC-V instruction set architecture (ISA). Renesas is among the first in the industry to independently develop a CPU core for the 32-bit general-purpose RISC-V market, providing an open and flexible platform for IoT, consumer electronics, healthcare and industrial systems. The new RISC-V CPU core will complement Renesas’ existing IP portfolio of 32-bit microcontrollers (MCUs), including the proprietary RX Family and the RA Family based on the Arm Cortex-M architecture.

RISC-V is an open ISA which is quickly gaining popularity in the semiconductor industry, due to its flexibility, scalability, power efficiency and open ecosystem. While many MCU providers have recently created joint investment alliances to accelerate their development of RISC-V products, Renesas has already developed a new RISC-V core on its own. This versatile CPU can serve as a main application controller, a complementary secondary core in SoCs, on-chip subsystems, or even in deeply embedded ASSPs. This positions Renesas as a leader in the emerging RISC-V market, following previous introductions of its 32-bit voice-control and motor-control ASSP devices, as well as the RZ/Five 64-bit general purpose microprocessors (MPUs), which were built on CPU cores developed by Andes Technology Corp.

“Renesas takes pride in offering embedded processing solutions for the broadest range of customers and applications,” said Daryl Khoo, Vice President of the IoT Platform Division at Renesas. “This new core extends our leadership in the RISC-V market and uniquely positions us to deliver more solutions that accommodate a diverse range of requirements.”

“We congratulate Renesas on achieving its recent milestone in 32-bit RISC-V MCU architecture development,” said Calista Redmond, CEO at RISC-V International. “This achievement exemplifies how RISC-V ecosystem partners, such as Renesas, are rapidly advancing RISC-V innovation. Our RISC-V community now spans 70 countries with more than 4,000 members, and we eagerly anticipate further innovations emerging from this dynamic, expanding market.”

The Renesas RISC-V CPU achieves an impressive 3.27 CoreMark/MHz performance, outperforming similar architectures on the market. It includes extensions to improve performance, while reducing code size.

Renesas is sampling devices based on the new core to select customers, with plans to launch its first RISC-V-based MCU and associated development tools in Q1 2024. Details of the new MCU will be published at that time. More information about RISC-V solutions is available at: renesas.com/risc-v. A blog article about the new RISC-V CPU is available here.

The post Renesas Unveils the First Generation of Own 32-bit RISC-V CPU Core Ahead of Competition appeared first on ELE Times.

Nuvoton Technology Ushers in a New Era of Edge Computing with the Introduction of the Innovative eBMC Chip

ELE Times - Mon, 12/04/2023 - 12:25

Nuvoton Technology, a leading global semiconductor technology provider, proudly announces its latest groundbreaking product – the eBMC chip. This innovative product, specially designed for edge computing platforms, promises to deliver enhanced efficiency, security, and management capabilities to the edge computing environment.

The eBMC (Edge Computing Base Management Controller) chip is a novel creation based on Nuvoton’s own BMC (Base Management Controller) and TPM (Trusted Platform Module) technologies. It seamlessly integrates Root of Trust (RoT), network security, and platform management. In addition to bringing full security and privacy protection for AI of edge computing, it also brings a perfect balance of design convenience and usability for edge computing platform manufacturers.

The eBMC chip boasts several crucial features, including:

  1. Root of Trust (RoT): The eBMC chip establishes a Root of Trust, ensuring the highest level of security for all data during processing and transmission. This is crucial for safeguarding sensitive data and mitigating data risks.
  2. Security and Privacy: The eBMC chip emphasizes security by incorporating multiple layers of security measures to guarantee data integrity and confidentiality. It integrates TPM technology, supporting data encryption, authentication, and risk management, shielding users from potential threats.
  3. Remote OOB (Out-of-Band) Management: AI models need to be deployed and regularly updated on edge devices, and these devices are often deployed in hard-to-reach locations. Therefore, eBMC chip provides remote management and troubleshooting, ensuring these devices maintain optimal operation in various environments.

In addition, the eBMC chip provides various interfaces and traditional I/O functions, including USB, eSPI, CAN Bus, UART, and more, making it compatible with various platforms, including x86 and ARM, while offering greater flexibility.

Nuvoton also proudly announces the selection of the eBMC chip as the Advantech EdgeBMC Out-of-Band management solution for IoT devices by Advantech in 2023. This collaboration ensures a higher level of security and management for IoT devices. “We are proud that the eBMC chip has been adopted by Advantech. This is a testament to our commitment to edge computing, data security, and smart technology. We believe this innovative product will bring greater value to Advantech and drive IoT future technological developments.” Nuvoton remarks.

Nuvoton has always been committed to driving progress worldwide through innovative technology. Nuvoton eBMC chip will continue to bring more innovation and development to the field of edge computing.

The post Nuvoton Technology Ushers in a New Era of Edge Computing with the Introduction of the Innovative eBMC Chip appeared first on ELE Times.

6ch multi-controlled relay board

Reddit:Electronics - Mon, 12/04/2023 - 12:21
6ch multi-controlled relay board

I built a multi-controlled relay board for my electronics workbench.

It can be controlled by web interface, HTTP GET, websocket, MQTT, UART (4pin JST header on top) and USB/serial. It also send changes to all these connections.

On the web interface you can define 25 groups of on/off states of the relays. Each group can be recalled by any of the interface methods, and you can also set a group to one of the two buttons for quick manual recalls.

The board works on the 24V supply I have all over my workbench, that's what the two 2pin JST headers are for (2nd one for daisychaining). All relay contacts are on the bottom side, there are two male and two female headers for every COM, NC and NO.

I wrote a little piece of code for my Stream Deck, so I can see and switch states of every relay and also recall every group from it.

I ise this thing to control and especially automate workflows on my electronics workbench. It's great for long run test series of things.

submitted by /u/analogMensch
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TI expands low-power GaN portfolio, enabling AC/DC power adapters to shrink 50%

ELE Times - Mon, 12/04/2023 - 11:20
  • Engineers can develop AC/DC solutions that are half the size and achieve >95% system efficiency, simplifying thermal design.
  • New GaN devices are compatible with the most common topologies in AC/DC power conversion.

Texas Instruments today announced the expansion of its low-power gallium nitride (GaN) portfolio, designed to help improve power density, maximize system efficiency, and shrink the size of AC/DC consumer power electronics and industrial systems. TI’s overall portfolio of GaN field-effect transistors (FETs) with integrated gate drivers addresses common thermal design challenges, keeping adapters cooler while pushing more power in a smaller footprint.

“Today’s consumers want smaller, lighter and more portable power adapters that also provide fast, energy-efficient charging,” said Kannan Soundarapandian, general manager of High Voltage Power at TI. “With the expansion of our portfolio, designers can bring the power-density benefits of low-power GaN technology to more applications that consumers use every day, such as mobile phone and laptop adapters, TV power-supply units, and USB wall outlets. Additionally, TI’s portfolio also addresses the growing demand for high efficiency and compact designs in industrial systems such as power tools and server auxiliary power supplies.”

The new portfolio of GaN FETs with integrated gate drivers, which includes the LMG3622, LMG3624 and LMG3626, offers the industry’s most accurate integrated current sensing. This functionality helps designers achieve maximum efficiency by eliminating the need for an external shunt resistor and reducing associated power losses by as much as 94% when compared to traditional current-sensing circuits used with discrete GaN and silicon FETs.

Maximize energy efficiency and simplify thermal design

TI’s GaN FETs with integrated gate drivers enable faster switching speeds, which helps keep adapters from overheating. Designers can reach up to 94% system efficiency for <75-W AC/DC applications or above 95% system efficiency for >75-W AC/DC applications. The new devices help designers reduce the solution size of a typical 67-W power adapter by as much as 50% compared to silicon-based solutions.

The portfolio is also optimized for the most common topologies in AC/DC power conversion, such as quasi-resonant flyback, asymmetrical half bridge flyback, inductor-inductor-converter, totem-pole power factor correction and active clamp flyback.

To learn more about the benefits of TI GaN for the most common AC/DC topologies, read the technical article, “The benefits of low-power GaN in common AC/DC power topologies.”

Long-term investment in GaN manufacturing

TI has a long history of globally owned, regionally diverse internal manufacturing operations, including wafer fabs, assembly and test factories, and bump and probe facilities across 15 worldwide sites. TI has been investing in manufacturing GaN technology for more than 10 years.

With plans to manufacture more than 90% of its products internally by 2030, TI has the ability to provide customers with dependable capacity for decades to come.

Package, availability and pricing

Production quantities of the LMG3622 and LMG3626 and pre-production quantities of the LMG3624 are available for purchase now on TI.com/GaN.

  • Pricing starts at US$3.18 in 1,000-unit quantities.
  • Available in an 8-mm-by-5.3-mm, 38-pin quad flat no-lead package.
  • Evaluation modules, including the LMG3624EVM-081, start at US$250.
  • Multiple payment and shipping options are available.
  • Pin-to-pin devices without integrated current sensing, LMG3612 and LMG3616, are also available.
About Texas Instruments

Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures, tests and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. Our passion to create a better world by making electronics more affordable through semiconductors is alive today, as each generation of innovation builds upon the last to make our technology smaller, more efficient, more reliable and more affordable – making it possible for semiconductors to go into electronics everywhere. We think of this as Engineering Progress. It’s what we do and have been doing for decades. Learn more at TI.com.

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