Feed aggregator

Kyocera has developed an innovative mmWave phased array antenna module (PAAM) that simultaneously creates multiple beams in different directions at different frequencies. These PAAMs will be used in 5G FR2 infrastructure installations, enabling for example site co-location of different operators running networks on different frequency bands. To ensure optimal beam steering and beam directivity of their groundbreaking product, Kyocera relies on CATR-based multi-reflector OTA testing technology from Rohde & Schwarz.

Kyocera and Rohde & Schwarz will showcase at MWC 2025 in Barcelona the characterization of a novel mmWave PAAM design for FR2 applications. Crucial to the demonstration at the Kyocera booth (5E12) is the R&S ATS1800M 5G NR multi-directional mmWave test chamber from Rohde & Schwarz, designed for over-the-air (OTA) testing with an exceptionally small footprint.

Mobile communications that operate in the FR2 frequency range experience a high path loss, something that can be solved by using beamforming antenna arrays. In contrast to traditional antennas, FR2 antennas typically use phased arrays with a high number of individual antenna elements. Kyocera has developed a novel phased array antenna module (PAAM) featuring 384 dual polarization elements which is able to create up to 8 simultaneous beams in different directions at different frequencies. With this design, the PAAM can be used in site installations allowing multiple operators to run networks on different frequency bands.

However, all these antenna elements need to work perfectly together to form an RF beam with the desired characteristics. Rohde & Schwarz offers a patented approach for testing such a complex antenna array over- the-air (OTA) in a fully shielded environment, which helps engineers verify the correct beam pattern and supports the process of minimizing sidelobes.

The R&S ATS1800M is a unique solution that features four feed antennas and CATR reflectors, each with a 30 cm quiet zone (QZ). In the demonstration at MWC 2025, the Kyocera PAAM device under test (DUT) is placed on a rugged 3D positioner in the center, where all four QZs overlap, coming from multiple directions. This allows Kyocera’s engineers to address a variety of different tests, including the simultaneous reception of RF beams from four different directions, as will be shown at MWC 2025. Thanks to the vertical CATR design patented by Rohde & Schwarz, this setup takes up a fairly small footprint in the lab compared to other OTA-solutions.

The full test setup contains multiple test instruments from Rohde & Schwarz in addition to the mmWave test chamber, which work seamlessly together: four 5G NR-capable R&S SMW200A vector signal generators, a 5G NR-capable R&S FSW signal and spectrum analyzer, and an R&S NGP800 power supply. Each generator simulates a 5G NR FR2 signal which will be fed through one of the R&S ATS1800M feed antennas. The DUT receives the signal via one of the CATR reflectors. With the combination of all signal

sources, feed antennas and reflectors, Kyocera’s engineers can simulate complex reception scenarios of four frequency independent signals from four different locations. The received signal quality can be observed using the signal analyzer connected to the Kyocera PAAM.

Visitors to MWC 2025 can experience this milestone demonstration live at the Kyocera booth 5E12 in hall 5 of the Fira Gran Via in Barcelona from March 3 to 6, 2025.

For further information on antenna testing solutions from Rohde & Schwarz, visit: https://www.rohde-schwarz.com/_231852.html

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AI-powered tool streamlines software development for greater efficiency and accuracy

Microchip Technology is leveraging the power of Artificial Intelligence (AI) to assist software developers and embedded engineers in writing and debugging code with the launch of its MPLAB AI Coding Assistant. A Microsoft Visual Studio Code (VS Code) extension, the free tool is based on Continue—the market’s leading open-source AI code assistant—and comes preconfigured with Microchip’s AI chatbot for real-time support.

The Microchip chatbot enables a chat functionality which allows developers to evaluate and iterate on code directly from the sidebar. This interactive support enhances the coding experience by providing highly customized, relevant real-time assistance and insights on Microchip-specific products. Additional features include advanced autocomplete for easier coding, an edit feature and error detection for efficient code modifications within the current file and integrated access to searchable Microchip documentation within the IDE.

“The MPLAB AI Coding Assistant represents a significant leap forward in software development and will transform how engineers work with Microchip products,” said Rodger Richey, vice president of development systems and academic programs at Microchip. “We’re harnessing the power of AI to provide interactive, real-time support that helps developers create better software, more quickly and with less hassle.”

Unlike most other code assistants on the market, MPLAB AI Coding Assistant’s sidebar chat feature can deliver block diagrams directly within the VS Code interface rather than just text responses. This capability, combined with easy access to a library of documentation on Microchip microcontrollers and microprocessors, streamlines the coding process and helps enhance accuracy.

Visit the website to learn more about Microchip’s wide range of development tools.

Pricing and Availability

The MPLAB AI Coding Assistant is available for free; some advanced features may require a subscription license. For additional information contact a Microchip sales representative, authorized worldwide distributor or visit Microchip’s Purchasing and Client Services website, www.microchipdirect.com.

The post Artificial Intelligence Meets Embedded Development with Microchip’s MPLAB AI Coding Assistant appeared first on ELE Times.

Rheostats are simple and ubiquitous circuit elements, usually comprising a potentiometer connected as an adjustable two terminal resistor. The availability of manual pots with resistances spanning ohms to megohms makes the optimum choice of nominal resistance easy. But when an application calls for a digital potentiometer (Dpot), the problem can be challenging.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Dpots are only available in a resistance range that’s narrow compared to manual pots. They also typically suffer from problematically high wiper resistance and resistance tolerance. These limitations conspire to make Dpots a difficult medium for implementing precision rheostats. Recent EDN design idea (DI) articles have addressed these issues with a variety of strategies and topologies:

• Op-amp wipes out DPOT wiper resistance
• Synthesize precision Dpot resistances that aren’t in the catalog
• Synthesize precision bipolar Dpot rheostats
• A class of programmable rheostats

While each of these designs corrects one or more complaints on the lengthy list of digital rheostat shortcomings, none fixes them all and some introduce complications of their own. Examples include crossover distortion, unreduced sensitivity to resistance tolerances, resolution-reducing nonlinearity of the programmed resistance, and just plain old complexity.

Figure 1’s circuit isn’t a perfect solution either. But it does synthesize an accurate programmed resistance equal to reference resistor R1 linearly multiplied by U1’s Rbw/Rab digital setting (the ratio between the terminal B to wiper resistance and total element resistance).

Figure 1 A precision digital rheostat that synthesizes an accurate programmed resistance equal to reference resistor R1 linearly multiplied by U1’s Rbw/Rab.

Here’s how it works.

 R = (Va – Vb)/Ia
R = R1/(Raw/Rbw + 1) = R1 Rbw/Rab
Rab = Raw + Rbw = typically 5k to 10k

Where R is the programmed synthetic resistance, R1 is the reference resistor, Raw is the resistance between terminal A and wiper terminal, Rbw is the resistance between B and wiper terminal, and Rab is the total element resistance.

U1 works in “voltage divider” (pot) mode to set the gain of inverting amplifier A2. Pot mode makes gain insensitive to both U1’s wiper resistance (Rw) and Rab. They really don’t matter much—see Figure 4-4 in the Microchip MCP41XXX/42XXX datasheet.

Turning the crank on Figure 1’s design equation math, we get:

Ga2 = Raw/Rbw

Where Ga2 is A2’s gain. Further,

Voltage across R1 = (Va – Vb) + Ga2(Va – Vb) = (Raw/Rbw + 1)(Va – Vb) =  Rab/Rbw(Va – Vb)
Current through R1 = Ia = Rab/Rbw(Va – Vb)/R1

Then, since R = (Va – Vb)/Ia:

R = R1*Rbw/Rab

Va is lightly loaded by A1’s ~10 picoamp (pA) input bias, so R1 can range from hundreds of ohms up to multiple megohms as the application may dictate. It should be precision, certainly 1% or better; then, programming and the math above takes over.

Figure 2 plots the linear relationship between R and Rbw.

Figure 2 Linear relationship between R and Rbw showing the circuit synthesizes an accurate programmed resistance equal to reference resistor R1 linearly multiplied by U1’s Rbw/Rab.

A compensation capacitor (C1) probably isn’t necessary for the parts selection shown in Figure 1 for A2 and U1. But if a faster amplifier or a higher resistance Dpot is chosen, then 10 pF to 20 pF would probably be prudent.

Meanwhile, I think it would be fair to say this design looks competitive with its peers. But earlier I described it as imperfect. Besides being a single-terminal topology (like two others on the list), where else does it fall short of being a complete solution to the ideal digital rheostat (Digistat) problem?

Here’s where: As Figure 3 shows, when the programmed value for R goes down, A2’s gain (Ga2) must go up. Reading the graph from right to left, we see gain rising moderately as R declines by 75% from R1 to R1/4 where, Rbw/Rab = 64/256 and gain = 3, but then it takes off. This tends to exaggerate errors like input offset, finite GBW and other op-amp nonidealities while creating the possibility of early A2 saturation at relatively low signal levels.

Figure 3 Graphs for Ga2 (red) and R/R1 (black) versus Rbw/Rab on the x-axis. When the programmed value for R goes down, Ga2 must go up.

The severity of the impact of these effects on utility of the design, whether mild, serious, or fatal, will depend on how low you need go in R/R1 and other specifics of the application. So, it’s certainly not perfect, but maybe it’s still useful somewhere.

And about that single terminal problem. If you have an application that absolutely requires a two-terminal programmable resistance, you might consider Figure 4. Depending on the external circuitry, it might not oscillate.

Figure 4 Duplicate and cross-connect Figure 1’s circuitry to get a two-terminal programmable resistance.

In closing…

Thanks to frequent contributor Christopher R. Paul for his clever innovations and stimulating discussions on this topic, I would likely never have come up with this design without his help. More thanks go to editor Aalyia Shaukat for her clever creation of this DI section that makes fun teamwork like this possible in the first place. This article would definitely never have happened without her help.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Op-amp wipes out DPOT wiper resistance
• Synthesize precision Dpot resistances that aren’t in the catalog
• Synthesize precision bipolar Dpot rheostats
• A class of programmable rheostats

The post A precision digital rheostat appeared first on EDN.

A new network-on-chip (NoC) IP aims to dramatically accelerate chip development by introducing artificial intelligence (AI)-driven automation and reducing wire length to lower power use in system-on-chip (SoC) interconnect design. Arteris, which calls its newly introduced FlexGen interconnect IP a smart NoC, claims to deliver a 10x productivity boost, shortening design iterations from weeks to days.

Modern chips—connected by billions of wires—are ever-expanding with growing complexity. Modern SoCs have 5 to 20+ unique NoC instances, and each instance can require 5-10 iterations. As a result, SoC design complexity has surpassed manual human capabilities, which calls for smarter NoC automation.

“In SoC interconnect, while technology has advanced to new levels, a lot of work is still done in manual mode,” said Michal Siwinski, CMO of Arteris. FlexGen accelerates chip design by shortening and reducing iterations from weeks to days for greater efficiency.

“While FlexGen is still using the tried-and-tested NoC IP technology as basic building blocks, it automates the existing infrastructure by employing AI technology,” said Andy Nightingale, VP of product management and marketing at Arteris. “With FlexGen, we automate the NoC IP generation to reduce the manual work while opening high-quality configurations that rival or surpass the manual designs.”

Figure 1 A FlexNoC manual interconnect (above) is shown for an ADAS chip, while an automated FlexGen interconnect (blow) accelerates this chip design by up to 10x. Source: Arteris

According to Nightingale, it enhances engineering efficiency by 3x while delivering expert-quality results with optimized routing and reduced congestion. Dream Chip Technologies, a supplier of advanced driver assistance systems (ADAS) silicon solutions, acknowledges reducing design iterations from weeks to days while using FlexGen in its Zukimo 1.1 automotive ADAS chip design.

“FlexGen’s automated NoC IP generation allows us to create floorplan adaptive topologies with complex automotive traffic requirements within minutes,” said Jens Benndorf, GM at Dream Chip Technologies. “That enabled rapid experimentation to find design sweet spots and to respond quickly to floorplan changes with almost push-button timing closure.”

Shorter wire length

With AI comes a compute performance explosion, and as a result, the complexity of interconnects is going to exponential levels in SoC designs, leading to a huge explosion in the number of wires. FlexGen claims to reduce wire length by up to 30% to improve chip or chiplet power efficiency.

“We are also tackling the big problem of wire length in modern SoC designs,” said Nightingale. “As the gate count size reduces, it inevitably leads to dynamic power issues due to massive data traffic across wires.” By reducing wire length, FlexGen interconnect IP can reduce overall system power and thus help heating problems caused by the energy density of moving massive amounts of data across SoC interconnects.

Figure 2 FlexNoC manual interconnect (above) is shown with the best performance, while automated FlexGen (below) significantly reduces the interconnect wire length. Source: Arteris

Siwinski added that the number of gates doesn’t matter at smaller nodes. “Power from wire length kills you, so we reduce wire length to reduce overall power, performance, and area (PPA) in SoC designs.” That’s crucial as SoCs scale and become more powerful to meet the demands of applications like AI, autonomous driving, and cloud computing.

FlexGen is processor agnostic and supports Arm, RISC-V, and x86 processors. Moreover, its IP generation is highly repeatable to facilitate incremental design.

Related Content

• SoC Interconnect: Don’t DIY!
• What is the future for Network-on-Chip?
• Why verification matters in network-on-chip (NoC) design
• SoC design: When is a network-on-chip (NoC) not enough
• Network-on-chip (NoC) interconnect topologies explained

The post SoC interconnect automates processes, reduces wire length appeared first on EDN.

electronica China 2025 will take place from April 15 to 17, 2025 at the Shanghai New International Expo Centre (SNIEC), in halls W3-W5 and N1-N5. It is expected to attract a total of 1,700 high-quality exhibitors from Chinese and international markets covering 100,000 square meters. The visitor registration is going on heatedly, register now and check out the highlights of the important trade fair for the electronics industry in Asia!

The venue will feature sections for semiconductors, sensors, power supplies, testing and measurement, passive components, displays, connectors, switches, wiring harnesses and cables, distributors, printed circuit boards, electronic manufacturing services, semiconductor intelligent manufacturing, etc. 1,700 premium enterprises from both Chinese and international markets will join in succession, showcasing their cutting – edge scientific research achievements and industry solutions.

This year’s exhibition will continue to host multiple themed forums, focusing on popular application markets and rapidly evolving industries such as electric vehicles, automotive electronics, humanoid robot, third-generation semiconductor, embedded system, AI, IoT, energy storage, smart manufacturing, connector, motor drive. Industry leaders, technical experts, and academic researchers from the electronic sector, application domains, and research institutes will be invited to address audience queries, share case studies, and provide cutting-edge technological solutions.

Click to register now: https://ec.global-eservice.com/?lang=en&channel=ele

For more information: https://www.electronicachina.com.cn/en

The post electronica China 2025 is Coming: Embarking on a journey of in-depth exploration of the electronic industry chain! appeared first on ELE Times.

The latest radio resource management (RRM) conformance work item from the Global Certification Forum (GCF) has reached “Active” status following the approval of the Rohde & Schwarz R&S TS8980FTA-M1 5G conformance test system as the first to meet test platform approval criteria (TPAC). This includes the validation of RRM FR2 test cases in standalone mode (SA) for both one and two angles of arrival (1x AoA and 2xAoA) within 5G mmWave band combinations.

Rohde & Schwarz is the first company to obtain Global Certification Forum (GCF) test approval for validating the radio resource management (RRM) performance of advanced 5G New Radio (NR) devices. This approval specifically applies to devices operating in 5G NR standalone (SA) mode within FR2 and capable of managing multiple angles of arrival. It enables device manufacturers to certify their products for global compatibility with mobile networks that utilize mmWave frequencies and operate in 5G SA with a real 5G core network (5GC).

Verifying compliance with critical RRM test cases is increasingly important as wireless 5G routers and customer premises equipment (CPE) gain prominence for fixed wireless access (FWA) applications. These test cases are essential for ensuring a reliable end user experience, especially in challenging network conditions, such as blockages, or at the cell edge.

After the Conformance Agreement Group (CAG) #81 meeting held by GCF in Bangkok January 21 to 23, 2025, it was confirmed that Rohde & Schwarz is currently the only provider offering certification solutions that meet all mandatory test requirements for 5G FR2 RRM, while also supporting the largest number of validated test cases for both RF and RRM in this frequency range. The Rohde & Schwarz 5G mmWave test platform offers a wide range of advanced 5G FR2 non-standalone (NSA) and SA test cases. The platform is built on the CMX500 5G network emulator and includes the R&S ATS1800M anechoic chamber series as well as a powerful device under test (DUT) positioner.

Thomas Eyring, Senior Director of Device Certification at Rohde & Schwarz, commented on the milestone, saying: “We are proud to take a significant step toward enhanced conformance testing as a pioneer in mobile device testing. Our technology will help ensure the quality and reliability of 5G devices while addressing the

challenges in the FR2 frequency range. We are also working on test cases for the upcoming FR3 frequency range, which is expected to play a key role in 6G networks.”

The post Rohde & Schwarz first to achieve GCF approval for 5G FR2 RRM standalone mode conformance test cases appeared first on ELE Times.

Altium joins AWS Skills to Jobs Tech Alliance in India; Aims to Bridge Skills Gaps and Enhance Employability for Indian Students

• AWS Cloud Practitioner Essentials – Covering cloud technology basics
• AWS Technical Essentials – Introducing core cloud concepts like networking, databases, and storage
• Amazon AppStream 2.0 Primer – AWS’s application streaming solution
• IoT Fundamentals – Training in IoT and smart technology

• On Campus Applied Learning: Co-hosted events, workshops and challenges will give students hands-on experience in solving industry challenges.
• Pathways to Employment: Students who complete the joint curriculum will connect with industry partners for career opportunities.

The post Altium and AWS Collaborate to Equip India’s Next Generation of Engineers with Industry-Ready Skills in Electronics Design and Cloud Technology appeared first on ELE Times.

The global semiconductor manufacturing industry closed 2024 with strong fourth quarter results and solid year-on-year (YoY) growth across most of the key industry segments, SEMI announced today in its Q4 2024 publication of the Semiconductor Manufacturing Monitor (SMM) Report, prepared in partnership with TechInsights. The industry outlook is cautiously optimistic at the start of 2025 as seasonality and macroeconomic uncertainty may impede near-term growth despite momentum from strong investments related to AI applications.

After declining in the first half of 2024, electronics sales bounced back later in the year resulting in a 2% annual increase. Electronics sales grew 4% YoY in Q4 2024 and are expected to see a 1% YoY increase in Q1 2025 impacted by seasonality. Integrated circuit (IC) sales rose by 29% YoY in Q4 2024 and continued growth is expected in Q1 2025 with a 23% increase YoY as AI-fueled demand continues boosting shipments of high-performance computing (HPC) and datacenter memory chips.

Similar to electronics sales, semiconductor capital expenditures (CapEx) decreased in the first half of 2024 but saw a strong rebound, particularly in the fourth quarter, resulting in 3% annual growth by the end of 2024. Memory-related CapEx continued to lead the growth surging 53% quarter-on-quarter (QoQ) and 56% YoY in Q4 2024. Non-memory CapEx also edged up in Q4 2024 showing 19% QoQ and 17% YoY improvement. Total CapEx is expected to remain strong in Q1 2025, growing 16% relative to the same period of the previous year on the strength of investments to support high bandwidth memory (HBM) capacity additions for AI deployment.

The semiconductor capital equipment segment remained resilient primarily due to increased investments into expanding leading-edge logic, advanced packaging and HBM capacity. Wafer fab equipment (WFE) spending increased 14% YoY and 8% QoQ in Q4 2024. Quarterly WFE billings are expected to be around $26 billion in Q1 2025. China’s investment continues to play a significant role in the WFE market but started to subside by end of the year. Additionally, back-end equipment showed strong increases in Q4 2024 with the Test segment logging 5% QoQ growth and an impressive 55% YoY increase for the quarter, while the Assembly and Packaging segment experienced a YoY increase of 15%. Both segments are expected to show similar QoQ growth between 6-8% in Q1 2025.

In Q4 2024, installed wafer fab capacity surpassed a record 42 million wafers per quarter worldwide (in 300mm wafer equivalent), and capacity is projected to reach nearly 42.7 million in Q1 2025. Foundry and Logic-related capacity continues to show stronger increases, growing 2.3% QoQ in Q4 2024, and the segment is projected to rise 2.1% in Q1 2025 driven by capacity expansion for advanced nodes. Memory capacity increased 1.1% in Q4 2024 and is forecasted to remain at the same level in Q1 2025 driven by strong demand for HBM.

“Despite seasonality and the challenges of macroeconomic uncertainty, momentum in AI-driven investments continues to fuel expansion across key segments, including memory, capital expenditures, and wafer fab equipment,” said Clark Tseng, Senior Director of Market Intelligence at SEMI. “Looking forward for 2025, the industry remains cautiously optimistic, with robust growth prospects driven by ongoing demand for high-performance computing and data center buildout.”

“As we begin the year, our expectation is for stronger performance in the second half, with semiconductor sales anticipated to remain flat sequentially in the first half, followed by a notable double-digit increase in the latter half,” said Boris Metodiev, Director of Market Analysis at TechInsights. “Inventory challenges persist for discrete, analog, and optoelectronic manufacturers, which will need to be addressed before we can expect widespread growth to resume.”

The Semiconductor Manufacturing Monitor (SMM) report provides end-to-end data on the worldwide semiconductor manufacturing industry. The report highlights key trends based on industry indicators including capital equipment, fab capacity, and semiconductor and electronics sales, along with a capital equipment market forecast. The SMM report also contains two years of quarterly data and a one-quarter outlook for the semiconductor manufacturing supply chain including leading IDM, fabless, foundry, and OSAT companies. An SMM subscription includes quarterly reports.

The post Global Semiconductor Manufacturing Industry Reports Solid Q4 2024 Results, SEMI Reports appeared first on ELE Times.

In my recent 2nd generation Google Chromecast teardown, “The Google Chromecast Gen 2 (2015): A Form Factor Redesign with Beefier Wi-Fi, Too,” I noted that I subsequently planned on tearing down the Chromecast Ultra, followed by the 3rd generation Chromecast, chronologically ordered per their respective introduction dates (2016 and 2018).

I’ve subsequently decided to flip-flop that ordering, tackling the 3rd generation Chromecast first, in the interest of grouping together devices with output resolution commonality. All three Chromecast generations, also including 2013’s original version, peak-output 1080p video, although the 3rd generation model also bumped up the frame rate from 30 fps to 60 fps; the Ultra variant you’ll see in the near future conversely did 4K. If you’re wondering why I’m referring to them all in the past tense, by the way, it’s because none of them are in production any longer, although everything but the first-generation Chromecast still gets software updates.

Google also claimed at intro that the Chromecast 3 not only came in new color options:

but was also 15% faster than its predecessor (along with adding support for Dolby Digital Plus and fully integrated Chromecast with Nest smart speakers), although the company was never specific about what “15% faster” meant. Was it only in reference to the already mentioned 1080p60 smoother video-playback option? One might deduce that it also referred to more general UI responsiveness, but if true was this due to faster innate processing—which all users would conceivably experience—or higher wireless network performance, only for those with advanced LANs? Or both? I hope this teardown will help answer these and other questions (like why does Wikipedia list no CPU or memory details for this generation?) to at least a degree.

Generally speaking, I try whenever possible to avoid teardowns of perfectly good hardware that end up being destructive, i.e., leaving the hardware in degraded condition that precludes me from putting it back together afterwards and donating it to someone else. In such cases, I instead strive to focus my attention on already nonfunctional “for parts only” devices sourced from eBay and elsewhere. This time, however, all I could find were still-working eBay options:

although the one I picked was not only inexpensive ($10 plus shipping and sales tax, $16.63 total) but was absent its original packaging:

Here’s a closeup of the micro-USB connector—a legacy approach that’s rapidly being obsoleted by the USB-C successor—at the other end of the USB-A power cable:

And here’s a top view of our patient, as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes:

Followed by a closeup of the top of the main body:

Same goes for the underside:

That printing on the bottom is quite scuffed at this seeming long-time use point, although I suspect it was already faint from the get-go. In the center are “UL Listed” and HDMI logos, with the phrase “ITE E258392” in-between them. And here’s what it says around the circumference:

Google Model NC2-685
1600 Amphitheater Parkway
Mountain View, CA 94043
CAN ICES-3
(B)NMB-3(B)
IC 10395A-NC26A5
FCC ID A4RNC2-6A5B
Made in Thailand
06041HFADVM445

…whatever (some of, I already get the rest of) that means. And phew!

Here’s the HDMI connector on one end of the cable:

And jumping ahead in time a bit, the other end, entering the partially disassembled body:

Back to where we were before in time, the opposite side of the body showcases, left to right, a hardware reset button (you can also reset via software, if the Chromecast is already activated and mobile device-connected), the aforementioned micro-USB power input and a status LED:

Speaking of sides, you probably already noticed the seam around the circumference of the main body. Also speaking of sides, let’s see if it gets us inside. First off, I used the warmed-up iOpener introduced previously in the Chromecast 2 teardown to heat up the presumed glue holding the two halves together at the seam:

Then I set to work with its iFixit-companion Jimmy:

which got me partly, albeit not completely, to my desired end result, complete with collateral damage in the process:

I suspected that the diminutive dallop of under-case thermal paste I’d encountered with the 2nd-generation Chromecast was more substantially applied this time, to counteract the higher heat output associated with the 3rd-generation unit’s “15% faster” boast. So, I reheated the iOpener, reoriented it on the device, waited some more:

and tried, tried again. Yep, there’s paste inside:

Veni, vidi, vici (albeit, in this case, not particularly swiftly):

My, that’s a lot of (sloppily applied, to boot) glue:

The corresponding paste repository on the inside of the upper-case half is an odd spongy donut-shaped thing. I’ve also scraped away some of the obscuring black paint to reveal the metallic layer beneath it, which presumably acts as a secondary heat sink:

Some rubbing alcohol and a tissue cleaned the blue-green goop off the Faraday cage:

Although subsequently removing the retaining screws on either side of the HDMI cable did nothing to get the cage itself off:

Resigning me to just ripping it off (behavior that, as you’ll soon see, wasn’t a one-time event):

Followed by (most of) the black tape underneath it:

I never actually ever got the HDMI cable detached from the lower-case half, but with the screws removed, I was at least able to disconnect it from the PCB:

enabling me to remove the PCB from the remainder of the case…at least theoretically:

This Chromecast-generation time around, there’s an abundance of thermal paste on both sides:

Even after jamming the Jimmy in the gap in attempting to cut the offending paste in half, I still wasn’t able to separate the PCB from the case, specifically down at the bottom where the micro-USB connector was. The ambient light in the room was starting to get dim and I needed to leave for Mass soon, so I—umm—just gave the PCB a yank, ripping it out of the case:

and quickly snapped the remainder of the photos you’ll see, including the first glimpse of the bottom of the PCB:

When I got back home and reviewed the shots, I was first flummoxed, then horrified, and finally (to this very day, in fact) mortified and embarrassed. And I bet that at least a few of you eagle-eyed readers already know where I’m going with this. What’s that in the bottom left-ish edge of the inside of the back half of the case (with the reset button rubber “spring” to its left and the light guide for the activity LED to its right)? Is that…a still-attached screw? Surrounded by a chunk of PCB?

Yes…yes it is. This dissected device is destined solely for the landfill, “thanks” to my rushed ham-handedness. Sigh:

Guess I might as well get this Faraday cage off too:

And clean off the additional inside paste:

The IC in the upper left is Marvell’s Avastar 88W8887 quad wireless transceiver, supporting 1×1 802.11ac, Bluetooth 4.1, NFC and FM, only some of these functions actually implemented in this design. It’s the same chip used in the 2nd generation Chromecast, so the basis for the “15% faster” claim seemingly doesn’t seemingly source here. Next to it on the right is a SK Hynix H5TC4G63EFR-RDA 4 Gbit LPDDR3-1866 SDRAM. Note too the LED in the lower left corner, and the PCB-embedded antennae on both sides. And, since this PCB is “toast” anyway (yes, note the chunk out of it in the lower right, too), I went ahead and lifted the upper right corner of the cage frame to assure myself (and you) that nothing meaningful was hiding underneath:

Back to the previously seen front side of the PCB:

At far left (with the hardware reset switch below it in the lower left corner…and did I mention yet the missing chunk of PCB to the right of it?), peeking out from the cage frame, is a small, obviously Marvell-sourced, IC labeled as follows (ID, anyone?):

MRVL
G868
952GAX

which I suspect has the same (unknown) function(s) as a similarly (but not identically) labeled chip I’d found in the 2nd-generation Chromecast:

MRVL
G868
524GBD

To its left is the much larger Synaptics MM3006, formerly known as the Marvell 88DE3006 (Synaptics having acquired Marvell’s Multimedia Solutions Business in mid-2017). Again, it’s the same IC as in the 2nd generation Chromecast. And finally, at far right is a Toshiba TC58NVG2S0 4 Gbit NAND flash memory. Same flash memory supplier as before. Same flash memory technology as before. But hey, twice the capacity as before (presumably to provide headroom for the added firmware “support for Dolby Digital Plus and fully integrated Chromecast with Nest smart speakers” mentioned earlier)! So, there’s that…

Aside from a bigger flash memory chip (and, ok, getting rid of the magnet integrated into the Chromecast 2’s HDMI connector), what’s different between the 2nd and 3rd generation Chromecasts, and where does Google’s “15% faster” claim come from? The difference, I suspect, originates with the DRAM. I hadn’t specifically mentioned this in the previous teardown, but the Samsung DRAM found there, while also LPDDR3 in technology and 4 Gbit in capacity, was a “K0” variant reflective of a 1600 MHz speed bin. This time, conversely and as already noted, the DRAM runs at 1866 MHz. My guess is that this uptick also corresponds to a slightly faster speed bin for the Marvell-now-Synaptics application processor. And therein lies, between the two, the modest overall system performance boost.

Agree or disagree, readers? Any other thoughts? Let me know in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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