Feed aggregator

Благодійний чемпіонат з футболу в КПІ ім. Ігоря Сікорського kpi вт, 10/08/2024 - 15:12

Recently I published a simple platinum resistance temperature detector (PRTD) design idea that was largely inspired by a deviously clever earlier DI by Nick Cornford.

Remarkable and consistently constructive critical commentary of my design immediately followed.

Reader Konstantin Kim suggested that an AP4310A dual op-amp + voltage reference might be a superior substitute for the single amplifier and separate reference I was using. It had the double advantages of lowering both parts count and cost.

Meanwhile VCF pointed out that >0.1oC self-heating error is likely to result from the multi-milliamp excitation necessary for 1 mV/oC PRTD output from a passive bridge design. He suggested active output amplification because of the lower excitation it would make possible. This would make for better accuracy, particularly when measuring temperatures of still air.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1 shows the outcome of some serious consideration and quiet contemplation of those, as they turned out to be, terrific ideas.

Figure 1 Nonlinearity is cancelled by positive feedback to PRTD constant excitation current feedback loop via R8. A2’s 10x gain allows reduced excitation that cuts self-heating error by 100x.

 A1’s built-in 2.5-V precision reference combines with the attached amplifier to form a constant-current excitation feedback loop (more on this to follow). Follow-on amplification allows a tenfold excitation reduction from ~2.5 mA to 250 µA with an associated hundredfold reduction in self-heating from ~1 mW to ~10 µW and a proportionate reduction in the associated measurement error.

The sixfold improvement in expected battery life from the reduced current consumption is nice, too.

The resulting 100 µV/oC PRTD signal is boosted by A2 to the original multimeter-readout compatible 1 mV/oC. R1 provides a 0oC bridge null adjustment, while R2 calibrates gain at 100oC. Nick’s DI includes a nifty calibration writeup that should work as well here as in his original.

Admittedly the 4310’s general-purpose-grade specifications like its 500-µV typical input offset (equivalent if uncompensated to a 5oC error) might seem to disqualify it for a precision application like this. But when you adjust R1 to null the bridge, you’re simultaneously nulling A2. So, it’s good enough after all.

An unexpected bonus benefit of the dual-amplifier topology was the easy implementation of a second-order Callendar-Van Dusen nonlinearity correction. Positive feedback via R8 to the excitation loop increases bias by 150 ppm/oC. That’s all that’s needed to linearize the 0 oC to 100oC response to better than +/-0.1oC.

So, cheaper, simpler, superior power efficiency, and more accurate. Cool! Thanks for the suggestions, guys!

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• DIY RTD for a DMM
• The power of practical positive feedback to perfect PRTDs
• Minimize measurement errors in RTD circuits
• Designing with temperature sensors, part three: RTDs
• RTDs provide differential temperature measurement 

The post Improved PRTD circuit is product of EDN DI teamwork appeared first on EDN.

What:      At India Mobile Congress 2024, Keysight Technologies will showcase a range of solutions designed to accelerate network validation, performance optimization, and innovation in wireless technology. The solutions on display help innovators to quickly solve design, emulation, and test challenges in order to optimize 5G experiences.

When:     October 15-18, 2024

Where:    Keysight booth: Hall 3, Stall No. 3.10

Bharat Mandapam, Pragati Maidan, New Delhi, India

Keysight demonstrations include:

• 6G Test Bed: Keysight will present its 6G Test Bed demo, offering a platform to test and validate emerging 6G technologies. The demo will focus on advanced features ultra-low latency, and the path to AI integration, providing insights into the future of communications. Keysight’s 6G Test Bed aims to accelerate research and development, enabling efficient network design and performance optimization for next-gen wireless networks, driving innovation in 6G.
• ORAN Design Validation: In this demo, Keysight will emphasize the validation of Open RAN components for compatibility, performance, and efficiency. Learn how Keysight’s solutions ensure seamless interoperability across ORAN networks, helping operators and vendors test, optimize, and validate open network elements, contributing to the development of reliable, flexible, and high-performance ORAN infrastructures.

• AI RAN, NTN, FWA, and Wi-Fi 7 testing: Keysight will demonstrate AI RAN and RICtest, focusing on optimizing radio access networks with AI technologies. The demo will also cover Non-Terrestrial Networks, showcasing innovative connectivity solutions, as well as Wi-Fi 7 scalability, and the newly introduced Fixed Wireless Access (FWA) test capability, highlighting advancements in next-gen wireless networking.

• Quantum Computing and FPGA-based architecture: This demo will highlight intuitive visualization techniques for complex quantum systems and showcase runtime error suppression methods to enhance the reliability and performance of quantum computing applications, demonstrating innovative solutions for next-gen computing challenges.

• AI-Augmented Testing: Keysight will showcase how advanced technologies, including AI-augmented testing capabilities featuring generative AI modeling, visual verification, and predictive analytics, enhance software testing. The demonstration will highlight how automating testing workflows is more efficient and accurate, as real-time insights into potential issues help improve the quality of digital solutions.

The post Keysight to Showcase Next Generation Solutions at India Mobile Congress 2024 appeared first on ELE Times.

Autonomous and automated driving is a megatrend in the automotive industry, along with electrification. AI plays a critical role in this trend, enabling vehicles to detect pedestrians, analyze driver behavior, recognize traffic signs, and control trajectories, among many other use cases. A key enabler of this is Edge AI, as autonomous and automated driving is highly dependent on the need for AI systems with machine learning capabilities and processors that can handle large amounts of data in parallel, safely, secured, and in real time. To address this challenge, Imagimob, an Infineon Technologies AG company, has enhanced its automotive machine learning portfolio by integrating machine learning capabilities into Infineon’s Automotive ASIL-D complaint MCUs like AURIX TC3x and AURIX TC4x.

“The integration of secured and dependable AI capabilities into microcontroller families is crucial for advancing autonomous driving applications in the automotive industry,” said Thomas Boehm, Senior Vice President Microcontroller at Infineon. “We are proud that our AURIX microcontrollers are now supported by Imagimob Studio, making them accessible to developers worldwide. This highlights our role as a leading innovator in the industry.”

“With the integration of AURIX into our Imagimob Studio, we are bringing full machine learning (ML) compatibility and capabilities to the automotive sector,” said Alexander Samuelsson, CTO of Imagimob. “This means that all the use cases we support with our platform are now also available for Infineon’s AURIX microcontrollers.”

With Imagimob Studio, developers can now create robust ML models for the Edge and deploy them onto Infineon’s proven AURIX MCUs. The process starts with creating machine learning models in Imagimob Studio. Once the AI model is complete, users can select to deploy on the MCUs directly within the platform. They are then guided through steps on how to deploy the code seamlessly, simplifying the implementation of machine learning on MCUs and enabling the creation of sophisticated ML models. In addition, Imagimob Studio offers a sample project for siren detection, demonstrating model creation and deployment. By using the code example, users can also learn how to create acoustic models with AURIX MCUs and a microphone shield. Furthermore, Imagimob has developed new regression models that can be used to calculate remaining battery power, health status, and usage time.

Advanced AI use cases with AURIX TC4x

The AURIX TC4x scalable MCU family offers a seamless upgrade path from the AURIX TC3x family of ASIL-D compliant automotive MCUs. This enhanced performance is powered by the next-generation TriCore 1.8. In addition, the AURIX TC4x features a scalable accelerator suite that includes a parallel processing unit (PPU) and multiple intelligent accelerators to support cost-effective AI integration. For the AURIX TC4x family, these advancements translate into enhanced machine learning capabilities, enabling developers to deploy multiple models simultaneously or more complex ones. For instance, while the AURIX TC3x can handle basic siren detection, the AURIX TC4x enables both siren detection and voice interaction simultaneously.

The post Imagimob’s Edge AI solutions are now available for the AURIX product family appeared first on ELE Times.

🎥 КПІ ім. Ігоря Сікорського активізує співпрацю щодо громадянської освіти з Фондом Ганса Зайделя kpi пн, 10/07/2024 - 19:40

Київські політехніки тримають марку найкращих баскетболістів Києва kpi пн, 10/07/2024 - 18:29

Back in October 2015, when I was evaluating alternatives to Microsoft’s Window Media Center for receiving, recording, and streaming cable television service around my house, I picked up a factory-refurbished Western Digital My Cloud 2 TByte (single-HDD) network-attached storage (NAS) (later rebranded as the My Cloud Home) for $99:

Introduced in late October 2013 (here’s an initial review from a few months later), the 2 TByte variant originally sold for $150. Roughly two years later came a notably feature-enhanced proprietary O/S update to My Cloud OS 3, along with additional single- and multi-HDD hardware models. I’d bought mine because it was one of the stored-recordings options then supported by SiliconDust’s HDHomeRun PVR software; I was already using the company’s HDHomeRun PRIME CableCard-supportive three-tuner networked receiver. I planned to run HDHomeRun PVR’s server software on a networked PC, with per-TV playback supported via Google Nexus Players, each paired to a micro-USB-to-Ethernet adapter and running the company’s Android client app.

Unfortunately, shortly thereafter came several successive WD Cloud OS remote device hijacks with a common attack vector—the NAS’s connectivity to WD’s “cloud” file sync and backup service—along with a common unfortunate company response—extended delay, in sloth-like reaction to both private alerts sent to the company by security vulnerability firms and public disclosures. One such patch suite belatedly arrived in March 2017; read it and weep.

In December 2021, WD “threw in the towel” on My Cloud OS 3, telling customers to upgrade applicable devices to My Cloud OS 5, as support for My Cloud OS 3 would be ending a few months later. Alas, my particular device wasn’t My Cloud OS 5-compatible; to WD’s credit, “devices that had auto-update enabled received a final firmware update that disabled remote access and outbound traffic to cloud services”, effectively transforming them into local-only NAS devices from that point forward. And the company also sent folks like me a 20%-off coupon for hardware-upgrade purposes; mine arrived on January 17, 2022.

Just in time, it turns out…two days later came the news of patches for yet another set of My Cloud OS 3 vulnerabilities. And, as it also turns out, My Cloud OS 5 users’ troubles alas weren’t over, either. In March of last year, WD’s cloud services were circumvented by a network breach that “locked them out of their data for more than 24 hours and has put company-handled information into the hands of currently unknown hackers.” I’m admittedly glad I didn’t take WD up on its discounted hardware upgrade offer, not that QNAP’s been notably better…

Truth be told, I never got around to actualizing my HDHomeRun PVR aspiration; I’m still running Windows Media Center on an out-of-support Windows 7-based networked computer along with several equally geriatric per-TV-located Xbox 360s (although the expiration clock on this particular setup is growing louder by the passing day, for reasons I’ll explain in greater detail in another upcoming planned post). I’ve still got my device, which I’ll never donate to charity due to its now-neutered functionality which’d only bewilder a recipient. Worst case, I’ve got a 2 TByte WD Red HDD that I can repurpose in some other system. And, to satisfy my own curiosity, among other reasons, I’ve also decided to crack open the NAS and see what’s inside.

Here’s an initial suite of overview shots, after I’d first removed the reflection- and glare-enhancing protective clear plastic sheet from the front and sides, and as usual accompanied by a 0.75″ (19.1 mm) diameter U.S. penny for size comparison purposes (the WD My Cloud Home 2 TByte has dimensions of 7.5 in x 1.9 in x 6.7 in/193.3 mm x 49 mm x 170.6 mm and weighs 2.12 lb./0.92 kg):

Right and left sides:

Top: no integrated fan on this NAS, but plenty of heat-dissipating passive airflow vents:

More on the raised bottom, this time presumably for air inflow (heat rises, don’cha know):

Here’s a closeup of the bottom-end label:

And finally, the much more interesting backside, once again vent-abundant:

Here’s a closeup of its sticker:

And another up-close perspective, this time with more intriguing elements for us techie folks:

The wired Ethernet connectivity is Gbit-capable, thereby rationalizing why I’ve held onto the NAS for this long in spite of its dearth of RAID 1 multi-HDD mirroring redundancy. Conversely, the USB connector is useful solely for expanding the internal capacity via a tethered DAS; the WD My Cloud Home cannot itself be used as a DAS to a USB-connected computer, alas.

Before diving in, here’s a look at the included accessories—a length of Ethernet cable and the external power supply—along with a closeup of the latter’s specs:

Initial path-inside suspicion focused on the backside label, but removal was unfruitful; no screw heads were behind it:

Focusing instead on the seams between the sides and the inner frame was more productive, with thanks to the publisher of this particular YouTube video for his calm-demeanor guidance:

Only a bit of collateral damage:

Here’s the first-time exposed inner frame frontside:

Along with the also now-exposed right- and left-side “guts”:

The HDD and its paired PCB assembly surprisingly (at least to me) “floats” on one end:

The other end’s two mounting points are more sturdily secure, but only somewhat (left side views first, then right):

Releasing one end of each clip:

affords liftoff of the insides:

Here’s the aforementioned assembly from multiple perspectives:

Three screws hold the PCB in place:

And I bet you know what comes next:

Slide off the SATA power and data connectors:

and, along with three spacers falling away, the separation between the PCB and HDD is complete:

including the now revealed, and much more interesting, PCB inside:

Additional closeups of the latter expose, I suspect, why this particular model never got the My Cloud OS 5 update:

The system SoC, also found in other WD My Book models, is Mindspeed Technologies’ (now NXP Semiconductor’s) M86261G-12 Comcerto 2000 communication processor, based on a dual-core Arm Cortex-A9 running at 650 MHz. Visit NXP’s product page and you’ll see that this particular chip is end-of-life (and likely has been for some time); alongside the IC’s demise, further software development support likely also ceased. For posterity, a photo of this exact SoC is even coincidentally showcased on Wikipedia’s company page:

Controller of a Western Digital My Cloud 4 TB – ARM Cortex-A9

To the system processor’s right is a Samsung K4B2G1646E 2-Gbit DDR3 SDRAM. To its left is Broadcom’s BCM54612E GbE transceiver, with an associated Delta Ethernet transformer beyond it. And in the M86261G-12’s lower right corner is a Winbond W25X40CL 4-Gbit serial flash memory, presumably housing the aforementioned OS.

In closing, here are some views of the HDD, which as previously mentioned is a conventional WD “Red” (the company’s Red series is NAS usage-tailored from access profile optimization, power consumption and other aspects) 2 TByte model.

The shielding between the HDD and the PCB lifts away easily:

And with that, I’ll close and hand the keyboard over to you for your thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

 Related Content

• Farewell, Windows Media Center
• Teardown: Disposable 1-Tbyte NAS drives: How’d that happen?
• Peeking inside an HDD
• NAS successors add notable features
• NAS failure launches a data recovery mission
• Beating the heat: A NAS’s CPU requires a critical mass of software in order to compete

The post Disassembling a Cloud-compromised NAS appeared first on EDN.

Analog and mixed-signal chipmakers are increasingly aiming to integrate analog signal chain with embedded processing platforms to build vertical solutions, and today’s announcement from Analog Devices Inc. reinforces this design trend.

ADI is creating what it calls a software-defined version of itself by providing a base software enablement platform that offers drivers, operating systems, middleware, and libraries built on a robust and secure software supply chain. The Wilmington, Massachusetts-based company calls it CodeFusion Studio.

Figure 1 The embedded software development platform encompasses core technologies like amplifiers, RF, and sensors as well as embedded digital software for processing, algorithms and security along with solution stacks on top. Source: Analog Devices Inc.

“ADI is expanding its digital portfolio, from lower-cost MCUs for precision applications to more advanced heterogeneous compute devices to analog chips with a digital interface,” said Rob Oshana, senior VP of Software and Security Group at ADI. “CodeFusion Studio provides a single, unified development environment for our digital portfolio.”

CodeFusion Studio

CodeFusion Studio—a software development environment tailored for ADI’s analog and digital technologies—is based on Microsoft’s Visual Studio Code. It comprises three core components. First, software development kit (SDK), which includes drivers, OSes, middleware, libraries and domain-specific reference applications.

Second, an integrated development environment (IDE) facilitates heterogeneous application development, debugging, and optimization. Third, configuration and productivity tools assist in system and core configuration, end-to-end security implementation, technical discovery, and efficient data flow through the system.

Figure 2 Essential features include breakpoints, disassembly, heterogeneous debugging, and RTOS thread awareness. Source: Analog Devices Inc.

Oshana notes that everything in CodeFusion Studio—from SDK to IDE and configuration tools—is open-source, offering design engineers greater control over their software development pipeline. “Open-source tooling provides developers full ownership of their software development pipeline.”

CodeFusion Studio leverages a modern IDE and command-line interface, encompassing open-source configuration and profiling tools to simplify development on heterogeneous processors. It also makes SDKs easily accessible by including Zephyr(r) and other communities with a broad ecosystem of technology plug-ins and providers.

Next, the new software platform supports the Assure Trusted Edge Security Architecture, ADI’s hardware and software security foundation that aims to facilitate a simple and flexible way to natively implement security inside semiconductor devices. It includes hardware security capabilities within select ADI hardware products and software layers with application programming interfaces (APIs) available within Code Fusion Studio.

Developer Portal

Besides CodeFusion Studio, an embedded software development environment, ADI has also unveiled a Developer Portal, which centralizes code samples, product documentation, and other resources to efficiently work with ADI’s technology and alleviate complexity. The Developer Portal brings together resources including tools, drivers, SDKs, sample code, tutorials, documentation, community news, and updates on design events.

ADI wants developer.analog.com to become the  primary place for developers to find the tools and resources they need to create new products and solutions and to stay current with the company’s hardware and software offerings.

Figure 3 The new embedded software development offers features like quick project setup as well as clock and configuration tools. Source: Analog Devices Inc.

At a time when embedded software engineering is becoming an increasingly complex challenge, development environments such as CodeFusion Studio built from the ground up can help simplify the embedded development experience. Especially, when it comes from an analog and mixed-signal design house like ADI, already engaged in algorithm development for signal processing applications.

“We looked for new ways for ease of use by reducing complexity and we didn’t have to worry about old, legacy software offerings,” Oshana said. He added that legacy platforms are often proprietary and fail to provide open, extensible interfaces essential for modern heterogeneous systems.

“Silicon vendors rarely think about consumers and debug. Fantastic that ADI is addressing this,” noted a user after reviewing this new development platform. “I needed this 20 years ago.”

Related Content

• Embedded Basics
• All Things Embedded
• 8 pillars of embedded software
• Mixed-Signal = Analog + Digital, or is there more to it?
• 5 Steps To Designing An Embedded Software Architecture

The post A new embedded software platform meshes analog and digital appeared first on EDN.

The US National Science Foundation (NSF) has awarded a three-year, $2m Future of Semiconductors (FuSe2) grant to researchers at Penn State University and the University of California, Santa Barbara (UCSB) to develop wireless communications and sensing platforms through advanced chips and packaging...

Did not have brass so had to make it out of steel wire submitted by /u/Spirited-Comfort521 [link] [comments]

submitted by /u/AutoModerator
[link] [comments]

Київська політехніка розширює співпрацю з Ajax Systems kpi сб, 10/05/2024 - 17:31

🎲 Тематичний міні-тренінг «Конфлікт інтересів» kpi пт, 10/04/2024 - 23:51

The circuit in Figure 1 seems utterly simple but demonstrates unusual behavior. It produces an almost square wave of odd-integer quartz harmonics, including its main frequency.

You can determine the output frequency of the circuit (Fo) simply by varying a resistor’s value.

Figure 1 A simple circuit that produces an almost square wave odd-integer of quartz harmonics.

The circuit uses shock excitation for the resonance oscillation of the quartz. In contrast to well-known oscillators, the circuit explores feedback from its highly nonlinear output providing the shock excitation of the quartz resonator which synchronizes the circuit oscillation.

Wow the engineering world with your unique design: Design Ideas Submission Guide

One potentially strange choice was to use a Schmitt trigger as an active element, albeit this trigger is far more helpful than an ordinary inverter; in this case it also ensures the unusual abilities of the circuit.

The output square wave of Schmitt trigger contains only components of odd-integer harmonic frequencies (of the form 2*π*(2*k−1)*f).

Hence, filtering out the undesirables with the help of LPF RC (look at the equivalent circuit on Figure 2) can provide a quite good excitation for the quartz. (Here C is the common capacitance associated with the quartz node: a parasitic capacitance plus capacitances of the trigger input and the quartz itself.)

Figure 2 A LPF RC equivalent circuit that provides excitation for quartz oscillator.

Assuming the rising threshold Vt1 and the falling threshold Vt0 are symmetrical (the case of 54HC14), the frequency of a free-running Schmitt trigger RC oscillator can be found by the approximately by equation:

Fofr = 1/(2*R*C*ln2) = 0.72/ (R*C)

To make the synchronization possible, this free-run frequency must be slightly less than the target frequency.

Note: if this condition is not held, the circuit can oscillate on a stray combination of sub-harmonics of the quartz, or any unrelated frequency determined mainly by RC. The question of the phase noise of such an oscillator is also open.

The circuit may be less useful for higher frequencies since a higher frequency means lower value of R and therefore more heavy shunting of the resonator by this resistor. The lower values of R also distort our simple model of a square wave oscillator.

But it is well suited for rather low quartz frequencies, it was used for frequencies in the range from 32 kHz to 1 or 2 MHz.

For instance, with Fq = 100 kHz the values of R in range 150k to 250k correspond to the main frequency (100 kHz), R from the range 85k to 40k gives the 3rd harmonic (300 kHz), values from the range 65k to 75k will give 5th harmonic (500 kHz) and so on. Surely, all these values are given as a guide for the case of 54HC14 and Edd = 5 V.

—Peter Demchenko studied math at the University of Vilnius and has worked in software development.

 Related Content

• Crystal-oscillator circuit is ultralow power
• Crystal Oscillator Fundamentals and Operation—Part II
• Crystal Oscillator Fundamentals and Operation—Part III
• Making oscillator selection crystal clear
• Oscillators: How to generate a precise clock source

The post Quartz oscillator with shock excitation appeared first on EDN.

Two analog signal generators from Keysight enable component and device characterization at frequencies up to 26 GHz. The AP5001A RF signal generator covers 9 kHz to 6.1 GHz, while the AP5002A microwave signal generator spans 9 kHz to 26 GHz. Their compact, lightweight design allows easy transport and efficient use of lab space.

Both generators deliver accurately leveled output power at 1 GHz, ranging from -120 dBm to +17 dBm for the AP5001A and up to +23 dBm for the AP5002A. Each instrument provides an OCXO-stabilized signal with -130 dBc/Hz phase noise at 1 GHz and a 20 kHz offset, ensuring mHz resolution for precise measurements. The fast switching speed of the AP5001A, as low as 20 µs, accelerates testing and increases throughput.

Keysight’s analog signal generators offer modulation capabilities, including AM, FM, PM, pulse, pulse train, and frequency chirps. They come equipped with an LCD touch screen, remote desktop software, and a carrying handle. The company states that the generators are future-ready, with all frequencies and options available for license upgrades.

Prices for the AP5001A and AP5002A signal generators start at $7357 and $17,850, respectively.

AP5001A product page

AP5002A product page

Keysight Technologies

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Portable signal generators reach 26 GHz appeared first on EDN.

Offering Limited Power Source (LPS) functionality, the AOZ1390DI ideal diode protection switch from AOS improves the efficiency and safety of USB Type-C applications. LPS limits the current and voltage supplied to the load, protecting sensitive components from conditions such as overcurrent and overvoltage.

In multiport ORing or parallel power applications, the LPS(B) pin of the AOZ1390DI can be connected to the Disable(B) pin of one or more AOZ1390DI devices across different ports. The LPS feature acts as a watchdog, disabling the port if another port in the same system is faulty or damaged. The ability to prevent excessive power flow from malfunctioning ports makes the AOZ1390D1 well-suited for multiport USB-C Power Deliver (PD).

The AOZ1390DI features Ideal Diode True Reverse Current Blocking (IDTRCB), effectively preventing undesired reverse current from VOUT to VIN. An integrated back-to-back MOSFET provides a typical on-resistance of 18 mΩ and a high Safe Operating Area (SOA).  Input operating voltage ranges from 3.3 V to 23 V, with both VIN and VOUT terminals rated for an absolute maximum of 30 V. 

The AOZ1390DI ideal diode protection switch is available in two variants. The -01 variant automatically restarts after fault conditions are cleared, while the -02 version latches the power switch off.

Both the AOZ1390DI-01 and AOZ1390DI-02 cost $1.40 each in lots of 1000 units. They are available in production quantities with a standard lead time of 12 weeks.

AOZ1390DI-01 product page

AOZ1390DI-02 product page

Alpha & Omega Semiconductor 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Ideal diode switch elevates UCB-C safety appeared first on EDN.

The Achronix Speedster AC7t800 FPGA delivers 12 Tbps of fabric bandwidth, making it well-suited for AI/ML, 5G/6G, and data center applications. Manufactured on TSMC’s 7-nm FinFET process, this midrange FPGA features a 2D network-on-chip (2D NoC) for 12 Tbps bandwidth, 864 machine learning processors, and six GDDR6 subsystems (including controller and PHY) that provide 1.5 Tbps of external memory bandwidth. It also supports double-bit error detection and single-bit error correction.

The AC7t800 supplies 711,000 logic elements (LEs), the equivalent of 730,000 system logic cells (LCs). Along with GDDR6 interfaces, the FPGA provides two 400-Gbps Ethernet channels, 16 PCIe Gen5 lanes, and 24 12-Gbps serializer/deserializer channels. The device’s 2D NoC facilitates connections among all interconnects, I/O, memory, internal functional blocks, and the FPGA fabric. According to Achronix, the 2D NoC reduces routing congestion by as much as 40% compared to conventional FPGAs.

Samples of the AC7t800 FPGA are available now.

AC7t800 product page

Achronix Semiconductor 

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post FPGA is optimized for high-bandwidth workloads appeared first on EDN.

ST has launched a page EEPROM that provides the speed and density typical of serial flash, combined with the byte-level flexibility of EEPROM. The SPI page EEPROM family offers densities of 8 Mbits, 16 Mbits, and 32 Mbits, significantly increasing storage compared to standard EEPROMs. These devices can be used in wearables, healthcare devices, asset trackers, e-bikes, and other industrial and consumer products.

Embedded smart page management allows byte-level write operations for processes like data logging, while also supporting page/sector/block erase and page programming up to 512 bytes for handling firmware OTA updates. The devices also offer buffer loading, which can program several pages simultaneously. The data-read speed of 320 Mbps is about 16 times faster than standard EEPROM, while write-cycle endurance of 500,000 cycles is several times higher than conventional serial flash.

With peak current control, page EEPROM minimizes power supply noise and prolongs the runtime of battery-operated equipment. According to ST, the write current is below that of many conventional EEPROMs, and there is a deep power-down mode with fast wakeup that reduces the current to below 1 µA.

The M95P08, M95P16, and M95P32 page EEPROMs are in production now, with prices starting at $0.50 for the 8-Mbit MP95P08.

STMicroelectronics

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Page EEPROM boasts flash-like speed appeared first on EDN.

Semtech’s single-channel LoRaWAN hub evaluation kit supports smaller-scale network deployments, such as SMB and smart home applications. Designed for low-density networks of up to 50 end devices, the kit is compatible with the LoRaWAN standard and LoRaWAN 1.0.x devices. It uses Wi-Fi for backhaul and can be configured via an embedded webpage.

This turnkey solution provides basic LoRaWAN connectivity and supports several Semtech LoRa sub-GHz transceivers, including the SX1261, SX1262, SX1268, LR1121, and LLCC68. The LRWHUB1EVK1A evaluation kit features a shield adapter board with an Espressif ESP32-S3, a low-power MCU-based SoC with integrated 2.4-GHz Wi-Fi and Bluetooth LE. Additionally, the kit comes with a separate OLED display adapter board. It requires a LoRa radio shield, sold separately.

Global analyst Omdia predicts LoRaWAN to have the greatest annual growth, at 30% over the 2023-2030 forecast period. “It is a comparatively recent technology finding a niche in longer-distance, lower-power applications like irrigation systems and security sensors for property perimeters,” noted Omdia senior research director, Edward Wilford. “The cost effectiveness of Semtech’s one-channel hub aligns well with such smaller-scale applications.”

For more information about Semtech’s LRWHUB1EVK1A single-channel LoRaWAN hub evaluation kit and reference designs, click here.

Semtech

Find more datasheets on products like this one at Datasheets.com, searchable by category, part #, description, manufacturer, and more.

The post Eval kit promotes LoRaWAN for smart home appeared first on EDN.