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Low-Power, Streamlined Devices Target Energy Management, Home Appliances, Building Automation and Medical Applications

• Core: 48MHz Arm Cortex-M23
• Memory: 512KB integrated, dual-bank Flash memory and 48KB SRAM
• Analog Peripherals: 24-bit Sigma Delta ADC with digital filter, 12-bit ADC, and temperature sensor.
• Packages: 100-, 80- and 64-pin LFQFP

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Cadence Reality Digital Twin Platform integrated with NVIDIA Omniverse and Orion molecular design platform accelerated with NVIDIA BioNeMo will transform the future of design

Cadence Design Systems, Inc. today announced an expansion of its multi-year collaboration with NVIDIA across EDA, system design and analysis, digital biology and AI with the unveiling of two transformative solutions to reinvent design using accelerated computing and generative AI.

First, the new Cadence Reality Digital Twin Platform is the industry’s pioneering comprehensive digital twin solution to facilitate speed-of-light acceleration of the design, simulation and optimization of data centers across multiple industries. The platform virtualizes the entire data center and uses AI, high-performance computing (HPC) and physics-based simulation to significantly improve data center energy efficiency by up to 30%.

The Cadence Reality platform’s integration with NVIDIA Omniverse brings OpenUSD data interoperability and physically based rendering to the digital twin solution—helping accelerate data center design and simulation workflows by 30X.

Second, the companies are collaborating on generative AI to dramatically accelerate approaches to drug discovery. Cadence’s cloud-native molecular design platform Orion® will now be supercharged with NVIDIA’s generative AI tool, NVIDIA BioNeMo , and NVIDIA microservices for drug discovery to broaden therapeutic design capabilities and shorten time to trusted results. The collaboration brings together decades of expertise in scientific software and accelerated computing from the two companies to deliver transformative approaches to drug discovery. Accelerated by on-demand GPU access at an unprecedented scale, pharmaceutical companies can quickly and reliably generate and assess design hypotheses across a range of therapeutic modalities, including biologics, peptides and small molecules.

“The broadening collaboration between NVIDIA and Cadence is having a transformative impact on everything from data center design to drug discovery,” said Dr. Anirudh Devgan, president and CEO, Cadence. “As AI rapidly becomes a keystone technology driving data center and data center workload expansion, the Cadence Reality Digital Twin Platform integration with NVIDIA Omniverse will optimize every aspect of data center design and operations, use energy more efficiently, and pave the way for a more efficient, resilient, and environmentally friendly future. Our groundbreaking efforts with NVIDIA to integrate BioNeMo with our industry-leading Orion molecular design tools hold great promise for unlocking new ideas and transforming the future of therapeutics and drug discovery. Together, NVIDIA and Cadence are leading the AI revolution.”

“Digital twins will transform manufacturing, drug discovery and countless other industries,” said Jensen Huang, founder and CEO of NVIDIA. “Using NVIDIA Omniverse and generative AI technologies, Cadence can deliver simulation and digitalization technologies to benefit individuals, companie and societies in ways we have yet to imagine.”

Digital twin technology is increasingly becoming critical to designers and operators of complex data center systems in the AI era as through creating a virtual replica of a physical system, it can use real-time data to simulate its behavior, performance and interactions in various conditions. The Cadence Reality platform provides visibility across the entire value chain, enabling data center designers and operators to simulate the performance of integrated liquid and air-cooling systems, visualize the performance of data centers and plan for what-if scenarios.

The company’s collaboration with NVIDIA also expands the capabilities of the Orion drug discovery platform by providing key capabilities, including access to BioNeMo models for structure prediction, small molecule generation and molecular property prediction. Molecules generated with BioNeMo may then be profiled and iteratively enhanced and designed with Orion tools.

Today’s announcements build upon Cadence and NVIDIA’s long-standing collaboration in areas such as:

• AI-driven digital and custom IC design, including PPA, schedule and cost reduction of NVIDIA GPUs with Cadence Innovus and Cadence Cerebrus solutions
• Over 20 years of partnership in hardware and software verification, including Palladium, Protium, and now Cadence Verisium technologies
• System design and analysis, including GPU-optimized Cadence Fidelity CFD Software and the revolutionary Cadence Millennium Enterprise Multiphysics Platform

These announcements also open a new chapter of Cadence’s Intelligent System Design strategy to help customers develop differentiated products across a wide range of industries and market verticals.

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STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, announced the resolutions to be submitted for adoption at the Annual General Meeting of Shareholders (AGM) which will be held in Amsterdam, the Netherlands, on May 22, 2024.

The resolutions, proposed by the Supervisory Board, are:

• The adoption of the Remuneration Policy for the Supervisory Board;

• The adoption of the Company’s statutory annual accounts for the year ended December 31, 2023, prepared in accordance with International Financial Reporting Standards (IFRS). The 2023 statutory annual accounts were filed with the Netherlands authority for the Financial Markets (AFM) on March 21, 2024 and are posted on the Company’s website (www.st.com) and the AFM’s website (www.afm.nl);

• The distribution of a cash dividend of US$ 0.36 per outstanding share of the Company’s common stock, to be distributed in quarterly installments of US$ 0.09 in each of the second, third and fourth quarters of 2024 and first quarter of 2025 to shareholders of record in the month of each quarterly payment as per the table below;

• The amendment to the Company’s Articles of Association;

• The adoption of the Remuneration Policy for the Managing Board;

• The reappointment of Mr. Jean-Marc Chery as member and Chairman of the Managing Board for a three-year term to expire at the end of the 2027 AGM;

• The approval of the stock-based portion of the compensation of the President and CEO;

• The appointment of Mr. Lorenzo Grandi as member of the Managing Board for a three-year term to expire at the end of the 2027 AGM;

• The approval of the stock-based portion of the compensation of the Chief Financial Officer;

• The approval of a new 3-year Unvested Stock Award Plan for Management and Key Employees;

• The reappointment of EY as external auditor for the 2024 and 2025 financial years;

• The reappointment of Mr. Nicolas Dufourcq, as member of the Supervisory Board, for a three-year term to expire at the end of the 2027 AGM;

• The reappointment of Ms. Janet Davidson, as member of the Supervisory Board, for a one-year term to expire at the end of the 2025 AGM;

• The appointment of Mr. Pascal Daloz, as member of the Supervisory Board, for a three-year term expiring at the 2027 AGM, in replacement of Mr. Yann Delabrière whose mandate will expire at the end of the 2024 AGM;

• The authorization to the Managing Board, until the conclusion of the 2025 AGM, to repurchase shares, subject to the approval of the Supervisory Board;

• The delegation to the Supervisory Board of the authority to issue new common shares, to grant rights to subscribe for such shares, and to limit and/or exclude existing shareholders’ pre-emptive rights on common shares, until the end of the 2025 AGM;

• The discharge of the member of the Managing Board; and

• The discharge of the members of the Supervisory Board.

The record date for all shareholders to participate at the Annual General Meeting of Shareholders will be April 24, 2024. The complete agenda and all relevant detailed information concerning the 2024 AGM, as well as all related AGM materials, are available on the Company’s website (www.st.com) and made available to shareholders in compliance with legal requirements as of March 21, 2024.

As for rule amendments from the Securities and Exchange Commission (SEC) and conforming FINRA rule changes, beginning on May 28, 2024, on US market the new standard for settlement will become the next business day after a trade or t+1. European settlement rule will remain at t+2.

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Introduction

Modern electronic systems need small, lightweight, high-efficiency power supplies. These supplies require cost-effective methods to take power from the AC power distribution grid and convert it to a form that can run the necessary electronics.

High switching frequencies are among the biggest enablers for small size. To that end, gallium nitride (GaN) switches provide an effective way to achieve these high frequencies given their low parasitic output capacitance (COSS) and rapid turn-on and turn-off times. It is possible, however, to amplify the high-power densities enabled by GaN switches through the use of advanced control techniques.

In this article, I will examine an advanced control method used inside a 5-kW power factor corrector (PFC) for a server. The design uses high-performance GaN FETs to operate the power supplies at the highest practical frequency. The power supply also uses a novel control technology that extracts more performance out of the GaN FETs. The end result is a high-efficiency, small-form-factor design with higher power density.

System overview

It’s well known that the totem-pole PFC is the workhorse of a high-power, high-efficiency PFC. Figure 1 illustrates the topology.

Figure 1 Basic totem-pole PFC topology where S1 and S2 are high-frequency GaN switches and S3 and S4 are low-frequency-switching Si MOSFETs. Source: Texas Instruments

S1 and S2 are high-frequency GaN switches operating with a variable frequency between 70 kHz and 1.2 MHz. S3 and S4 are low-frequency-switching silicon MOSFETs operating at the line frequency (50 to 60 Hz).

During the positive half cycle of the AC line, S2 operates as the control FET and S1 is the synchronous rectifier. S4 is always on and S3 is always off. Figure 2 shows the interval when the inductor current is increasing because control FET S2 is on. Figure 3 shows the interval when the inductor current is discharging through synchronous rectifier S1.

Figure 2 Positive one-half cycle inductor current charge interval. Source: Texas Instruments

Figure 3 Positive one-half cycle inductor discharge interval. Source: Texas Instruments

Figure 4 and Figure 5 illustrate the same behaviors for the negative one-half cycle.

Figure 4 Negative one-half cycle inductor current charge interval. Source: Texas Instruments

Figure 5 Negative one-half cycle inductor discharge interval. Source: Texas Instruments

ZVS

The use of GaN switches for S1 and S2 enables the converter to run at higher switching frequencies given the lower turn-on and turn-off losses of the switch. It is possible to achieve even higher frequencies, however, if the GaN switches can turn on with zero voltage switching (ZVS). The objective for this design is to achieve ZVS on every switching cycle for all line and load conditions. In order to do this, you will need two things:

• Feedback to tell the controller if ZVS has been achieved
• An algorithm that a microcontroller can execute in real time to achieve low total harmonic distortion (THD)

You can accomplish the first item through an integrated zero voltage detection (ZVD) sensor inside the GaN switches [1]. The ZVD flag works by asserting a high signal if the switch turns on with ZVS; if it does not achieve ZVS at turn-on, the ZVD signal stays low. Figure 6 and Figure 7 illustrate this behavior.

Figure 6 ZVD feedback block diagram with the LMG3425R030 GaN FET with an integrated driver, protection and temperature reporting as well as the TMS320F280049C MCU. Source: Texas Instruments

Figure 7 ZVD signal with ZVS (left) and ZVD signal without ZVS (right). The integrated ZVD sensor enables a ZVD flag that can be seen if the switch turns on with ZVS. Source: Texas Instruments

Integrating this function inside the GaN switch provides a number of advantages: minimal component count, low latency and reliable detection of ZVS events.

In addition to the ZVD signal, you also need an algorithm capable of calculating the switch timing parameters such that you can achieve ZVS and low THD simultaneously. Figure 8 is a block diagram of the hardware needed to implement the algorithm.

Figure 8 Hardware needed for the ZVD-based control method that enables an algorithm capable of calculating the switch timing parameters to achieve ZVS and a low THD simultaneously. Source: Texas Instruments

Solving the state plane for ZVS of the resonant transitions of the GaN FET’s drain-to-source voltage (VDS) will give you the algorithm for this design. Figure 9 illustrates the GaN FET VDS, inductor current, and control signals, along with both the time-domain and state-plane plots.

Figure 9 Resonant transition state-plane solution with the GaN FET VDS, inductor current, and control signals, along with both the time-domain and state-plane plots. Source: Texas Instruments

In Figure 9’s state-plane plot:

• “j” is the normalized current at the beginning and end of each dead-time interval
• “m” is the normalized voltage
• “θ” is used for the normalized timing parameters

The figure also shows the normalization relationships. The microcontroller in Figure 8 solves the state-plane system equations shown in Figure 9 such that the system achieves both ZVS and an ideal power factor. The ZVD signal provides feedback to instruct the microcontroller on how to adjust the switching frequency to meet ZVS.

Figure 10 shows the operating waveforms when the applied frequency is too low (left), ideal (center) and too high (right). You can see that both ZVD signals are present only when the applied frequency is at the ideal value; thus, varying the frequency until both FETs achieve ZVD will reveal the ideal operating point.

Figure 10 ZVD control waveforms when the applied frequency is too low (left), ideal (center) and too high (right). Source: Texas Instruments

Hardware performance

Figure 11 is a photo of a two-phase 5-kW design example using GaN and the previously described algorithm.

Figure 11 Two-phase 5 kW GaN-based PFC with the hardware required to apply algorithms to achieve even higher frequencies and enhance the efficiency of the overall solution. Source: Texas Instruments

Table 1 lists the specifications for the design example.

 Table 1 Design specifications for hardware example used in Figure 11.

Figure 12 shows the inductor current waveforms (ILA and ILB) and GaN FET VDS waveforms for both phases (VA and VB). The plots are at full power and illustrate three different operating conditions. In each case, you can see ZVS and a sinusoidal current envelope. The conditions for all three plots are VIN = 230VRMS, VOUT = 400V, P = 5kW, and 200V/div, 20A/div and 2µs/div.

Figure 12 The inductor current waveforms (ILA and ILB) and GaN FET VDS waveforms taken at full power for: (a) VIN≪VOUT/2, (b) VIN=VOUT/2, and (c) VIN≫VOUT/2. Source: Texas Instruments

Figure 13 shows the measured efficiency and THD for a system operating with a 230VAC input across the load range.

Figure 13 Efficiency and THD of a two-phase PFC operating with a 230VAC input across the load range. Source: Texas Instruments

 Reducing the footprint of a GaN power supply

GaN switches can increase the power density of a wide variety of applications by enabling faster switching frequencies. However, the addition of technologies such as advanced control algorithms can significantly reduce the footprint of a power supply even further. For more information about the reference design example discussed in this article, see reference [2].

Brent McDonald works as a system engineer for the Texas Instruments Power Supply Design Services team, where he creates reference designs for a variety of high-power applications. Brent received a bachelor’s degree in electrical engineering from the University of Wisconsin-Milwaukee, and a master’s degree, also in electrical engineering, from the University of Colorado Boulder.

Related Content

• Power Tips #124: How to improve the power factor of a PFC
• Power Tips #115: How GaN switch integration enables low THD and high efficiency in PFC
• Power Tips #116: How to reduce THD of a PFC
• PFC totem pole architecture and GaN combine for high power and efficiency

 References

1. Texas Instruments. n.d. LMG3526R030 650-V 30-mΩ GaN FET with Integrated Driver, Protection and Zero-Voltage Detection. Accessed Jan. 22, 2024.
2. Texas Instruments. n.d. “Variable-Frequency, ZVS, 5-kW, GaN-Based, Two-Phase Totem-Pole PFC Reference Design.” Texas Instruments reference design No. PMP40988. Accessed Jan. 22, 2024.

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Design options allow system designers to configure their system with the right performance, reliability, and safety considerations while meeting design cost and efficiency targets. The right design options can be even more important in high-voltage and/or high-current applications. In these high-power designs, an isolation technique with several integrated features can mean the difference between a product that meets and even exceeds customer expectations and one that generates numerous customer complaints.

For example, an integrated solid-state isolator (SSI) based on coreless transformer (CT) provides galvanic isolation with several design benefits. With integrated features such as a dynamic Miller clamp (DMC), overcurrent and overtemperature protection (OTP), under-voltage lockout protection, fast turn-on, and more, an integrated SSI driver can provide essential protection and ensure proper operation and extended life for high-power systems. These integrated protection features are not available in optical-based solid-state relays (SSRs).

Combined with the appropriate power switches, the highly integrated solid-state isolators allow designers to create custom solid-state relays capable of controlling loads in excess of 1,000 V and 100 A. The CT-based isolators enable energy transfer across the isolation barrier capable of driving large MOSFET or IGBT without the added circuitry of a power supply on the isolated side. SSRs designed with these innovative protection features can be highly reliable and extremely robust.

These coreless transformer-based isolators enable ON and OFF control, acting like a relay switch without requiring a secondary side, isolated power supply. Combined with MOSFETs and IGBTs, SSIs enable cost effective, reliable, and low power solid-state relays for a variety of applications. This includes battery management systems, power supplies, power transmission and distribution, programmable logic controllers (PLCs), industrial automation, and robotics as well as smart building applications such as heating, ventilation, and air conditioning (HVAC) controllers and smart thermostats.

Energy transfer through coreless transformer

The main design feature of an SSI device is a coreless transformer which enables power transfer across a galvanic isolation barrier of up to 10 mW. This eliminates the need for an isolated power supply for the switch reducing the bill of material (BOM) volume, count, and cost as well as providing a fast turn ON/OFF feature (≤ 1 µs) to ensure that the safe operating area (SOA) of the switch is adhered to.

Figure 1 Highly integrated solid-state isolators easily drive MOSFETs or IGBTs and do not require an isolated bias supply. Source: Infineon

Integrated protection

The integrated protection features of the CT-based isolators deserve further explanation. These include overcurrent and overtemperature protection (OTP), a dynamic Miller clamp, and under-voltage lockout (latch-off) protection as well as satisfying essential industry standards.

System and switch protection

Depending on the application’s need and product variant selected, SSIs offers overcurrent protection (OCP) as well as OTP either via an external positive temperature coefficient (PTC) thermistor/resistor or a MOSFET’s integrated direct temperature sensor.

In case of a failure event (overcurrent or overtemperature), SSI triggers a latch-off. Once triggered, the protection reacts quickly, turning off in less than 1 μs. Furthermore, it can support the AC-15 system tests, required for electromechanical relays according to the IEC 60947-5-1 under appropriate operating conditions.

Overcurrent protection

When operating solid-state relays, a common problem is the handling of fast overcurrent or short circuit events in the range of 20 A/μs up to 100 A/μs. Isolation issues often result in a short circuit with an extremely high current level that is defined by the power source’s impedance and cabling resistance.

Figure 2 shows a circuit for implementing the overcurrent protection. The shunt resistor (RSh) and its inherent stray inductance (LSh) generate a voltage drop that is monitored by the current sense comparator. Noise on the grid needs to be filtered out from the shunt signal, so an external filter (CF and RF) complements the integrated filter. When the comparator triggers, it activates the fast turn-off and latches the fault leaving the system in a safe state.

Figure 2 The above circuitry implements overcurrent protection using an isolator driver. Source: Infineon

Overtemperature protection

Another major known issue when operating solid-sate relays is the slow overload events that heat up the switches and the current sensor (shunt). Increased load current and insufficient thermal management can additionally shift the overall temperature above the thermal power transistor limits.

Figure 3 shows an example measurement of the overtemperature protection using an isolated driver. The SSI turns off two MOSFETs with integrated temperature sensors configured in a common-source mode. The sensing MOSFET heats up from the load current until the sensor voltage decreases below the comparator trigger threshold. As a result, the SSI’s output is turned off.

Figure 3 Isolated driver’s overtemperature protection triggers within 500 ns. Source: Infineon

The lower part of Figure 3 depicts a detailed zoom into the turn-off in this measurement with a time resolution of 500 ns per division. This reduced timeframe shows that the gate is turned off in much less than 500 ns. This means that the switched transistors do not violate their safe operating area.

Dynamic Miller clamping protection

Some SSIs also have an integrated dynamic Miller clamp to protect against spurious switching due to surge voltages and fast electric transients as well as the dv/dt of the line voltage. The dv/dt applied by the connected AC voltage creates capacitive displacement currents through the parasitic capacitances of a power transistor.

This can lead to parasitic turn-on of the power switch by increasing the voltage at its gate node during its “off” state. The dynamic Miller clamping feature ensures that the power switch remains safe in the “off” state.

When failure is not an option

When matched with the appropriate power switch, the isolator drivers enable switching designs with a much lower resistance compared to optically driven/isolated solid-state solutions. This translates to longer lifespans and lower cost of ownership in system designs. As with all solid-state isolators, the devices also offer superior performance compared to electromagnetic relays, including 40% lower turn-on power loss and increased reliability due to the elimination of moving or degrading parts.

When failure is not an option, the right choice of isolation can mean the difference between design success and failure.

Dan Callen Jr. is a senior manager at Power IC Group of Infineon Technologies.

Davide Giacomini is director of marketing at Power IC Group of Infineon Technologies.

Sameh Snene is a product applications engineer at Infineon Technologies.

Related Content

• Isolated Gate Drivers for GaN MOSFETs
• Gate Driver Solutions Proliferate for Motor Control
• Improving Energy Efficiency with a SiC Isolated Gate Driver
• Galvanic Isolation in Electric and Hybrid Vehicle Applications
• Isolation is good when it’s digital: Protect your people and devices

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