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The new Snapdragon 7+ Gen 3 processor comes with CPU and memory performance increases, Wi-Fi 7, and enhanced edge AI capabilities for mobile devices.

The UK Government has announced a £16.6m investment to give semiconductor researchers and businesses access to new equipment helping them to test and make chips for use in high-energy machines such as electric vehicles and manufacturing equipment. Of the funding, £14m is targeted particularly at semiconductors used in power electronics...

In a ceremony attended by HRH The Princess Royal as well as key customers, ecosystem partners, investors and government officials, Pragmatic Semiconductor of Cambridge, UK has officially opened what is the UK’s first 300mm wafer fabrication line. The manufacturing facility at the 60,000m2 Pragmatic Park brownfield site near Durham in North-East England produces chips based on the firm’s unique flexible integrated circuit (FlexIC) technology...

In electrical heating applications, resistive heaters are powered through phase angle-controlled SCR/triac circuits to vary the applied voltage/power to maintain the required temperature.

Phase angle control produces a lot of harmonics leading to power line disturbances.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Figure 1’s circuit gives a simple and cost-effective solution without introducing harmonics. This controller skips a certain number of power cycles in between, to vary power to the heaters.

Figure 1 Circuit schematic of mains cycle skipping controller, this controller skips a certain number of power cycles in between, to vary power to the heaters.

In this typical design, 10 full cycles are taken as base. Timer U3 (555) through R2, R4, and C1 decides this by giving output pulses with an interval of  200 ms, which is the width of 10 full AC cycles of a 50 Hz AC mains (for a 60 Hz mains, this will be 166.6 ms). These pulses trigger U4 (555) monostable to produce pulses with an adjustable width within 200 ms, by adjusting potentiometer RV1. This pulse train controls an optotriac with zero cross detector U2 (MOC3033) to trigger triac U1 (BTA25-600BW). The triac conducts for the duration of “off pulse widths” produced by U4. Thus, these conduction periods allow the selected number of voltage cycles to pass through and impress on load. During “on pulse widths”, the triac does not conduct and skips the voltage cycles. Simulated waveforms can be seen in Figure 2 with two full cycles being skipped and Figure 3 with five full cycles being skipped.

Figure 2 Simulated waveforms with the U3 timer output (yellow), U4 timer output (blue), and heater voltage (pink). Eight full cycles are impressed on load, skipping two full cycles as decided by the RV1 potentiometer position.

Figure 3 Simulated waveforms with the U3 timer output (yellow), U4 timer output (blue), and heater voltage (pink). Five full cycles are impressed on load, skipping five full cycles as decided by another RV1 potentiometer position.

As an example, if a 40 ms width is chosen by RV1, which corresponds to 2 full cycles of a 50 Hz mains, the triac will not conduct for 2 voltage cycles and will conduct for 8 full cycles and pass to the load. Thus, two cycles are skipped. This operation repeats. Thus, load power is controlled by skipping a selected number of voltage cycles. As AC cycles passed to load are full cycles, unwanted harmonics are eliminated.

Normally such controllers are realized with an MCU and software, the novelty of this circuit realizing the  same function without using the MCU, thus making it simple with low cost components.

Jayapal Ramalingam has over three decades of experience in designing electronics systems for power & process industries and is presently a freelance automation consultant.

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• How to make LED bulbs dimmable

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Diamfab has raised €8.7m in a first round of funding from Asterion Ventures, as well as from the French Tech Seed fund (managed on behalf of the French government by Bpifrance as part of France 2030), Kreaxi with the Avenir Industrie Auvergne–Rhône–Alpes regional fund, Better Angle, Hello Tomorrow and Grenoble Alpes Métropole...

Rohde & Schwarz will present the first real-time measurements on the planned new Bluetooth signals to support Channel Sounding. The demonstration at the embedded world Exhibition & Conference in Nuremberg, Germany, will be run on an R&S CMW500 wideband radio communication tester. The Bluetooth Channel Sounding feature will enable unprecedented positioning accuracy for consumer and commercial applications. The signal measurement capabilities to support chip and device development are eagerly awaited by the industry.

For consumer and commercial devices, Bluetooth is the most widely installed technology with location-determining capabilities. Channel Sounding, soon to be introduced, will significantly improve the accuracy of real-time location services for determining position using Bluetooth to an accuracy of 50 cm or better. In addition to improved location accuracy, Channel Sounding is expected to consume less power than existing Bluetooth location services and provide increased security. The improved accuracy will be a major step forward in particular for indoor applications such as asset tracking on the factory floor or in the warehouse, as well as for secure access to buildings or vehicles.

Hardware changes for Bluetooth devices introduced on a new physical layer are required to support the improved location functions. Engineers who want to start developing the necessary chips and devices, including support for Channel Sounding urgently require reliable and accurate measurements on the signals that enable the new functions. Rohde & Schwarz has already prepared options for its R&S CMW platform to support the corresponding RF physical layer measurements.

The current draft of the next version of the Bluetooth Core Specification defines support for phase-based ranging (PBR) tone exchange and round-trip time (RTT). To give hardware and software engineers involved in Bluetooth chipset and device development an early preview of the PBR measurement techniques, Rohde & Schwarz will be presenting a session at the embedded world Conference called “Redefining Bluetooth Low Energy Testing to Cover Latest Bluetooth Innovations” at 1:45 p.m. on April 10. A live demonstration of the measurements will take place at the Rohde & Schwarz booth 4-218 in hall 4 at the embedded world Exhibition in Nuremberg, Germany, April 9 to 11, 2024.

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Featuring a Common Cathode Configuration, Devices Can Withstand IOL Cycles Up to 5x That of the Previous TO-244 Generation for Improved Life Expectancy While
Reducing Losses

Vishay Intertechnology, Inc. has introduced two new FRED Pt 500 A Ultrafast soft recovery diode modules in the new TO-244 Gen III package. Offering higher reliability than previous-generation solutions, the Vishay Semiconductors VS-VSUD505CW60 and VS-VSUD510CW60 are designed to reduce losses and EMI / RFI in high-frequency power conditioning systems.

The rugged TO-244 package of the diode modules released today withstands 46 000 IOL cycles at given conditions, offering an improved life expectancy over previous-generation devices. In addition, the industry-standard package is footprint-compatible with competing solutions in the TO-244 to provide a drop-in replacement for existing designs.

The VS-VSUD505CW60 and VS-VSUD510CW60 are ideally suited for high-frequency welding; high current converters and ballast water management systems (BWMS) in railway equipment, cranes, and ships; UPS; and other applications where switching losses comprise a significant portion of the total losses. In these applications, the softness of their recovery eliminates the need for a snubber, reducing component counts and lowering costs.

Offered in a common cathode configuration, the diode modules provide low forward voltage drop down to 0.82 V, thermal resistance — junction to case — of 0.16 °C/W, and an operating temperature range up to +175 °C.

Device Specification Table:

Part number	VS-VSUD505CW60	VS-VSUD510CW60
VR (V)	600
IF(AV)(A)	500
Qrr typical (nC)	460	1770
trr (ns)	178	270
VFM @ 250 A, +175 °C (V)	0.95	0.82
RthJC per diode (°C/W)	0.160
Package	TO-244

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Infineon Technologies AG has introduced the first product in its new advanced power MOSFET technology OptiMOS 7 80 V: The IAUCN08S7N013 features a significantly increased power density and is available in the versatile, robust, and high-current SSO8 5 x 6 mm² SMD package. The OptiMOS 7 80 V offering is a perfect match for the upcoming 48 V board net applications. It is designed specifically for the high performance, high quality and robustness needed for demanding automotive applications like automotive DC-DC converters in EVs, 48 V motor control, for instance, electric power steering (EPS), 48 V battery switches and electric two- and three-wheelers.

Compared to the previous generation, the RDS(on) of the Infineon IAUCN08S7N013 has been reduced by more than 50 per cent and is now the best RDS(on) in the industry with a maximum of 1.3 mΩ. Users benefit from minimized conduction losses, superior switching performance and the highest power density in a 5 x 6 mm² package. In addition, the IAUCN08S7N013 also features low package resistance and inductance, as well as a high avalanche current capability. For automotive applications, it has an extended qualification that goes beyond AEC-Q101.

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Anritsu Corporation in collaboration with the University of Texas at Dallas showcased its orchestration system for overall control and monitoring of combined OpenROADM[*1] and IPoDWDM[*2] networks at the Optical Fiber Communication Conference and Exhibition 2024 (OFC2024) on March 26-28, 2024, in San Diego, USA.

These networks are controlled by the YANG model devised by OpenROADM and IETF[*3] as a vendor-independent network control method with an orchestration system managed by the University of Texas at Dallas. In the demonstration, Anritsu’s compact, high-performance MT1040A 400G Tester is connected via an open interface to the Add/Drop line to monitor quality in a live traffic environment.

Today’s network functions are becoming more sophisticated and virtualized for diversifying all-photonics networks and Beyond 5G/6G use cases. Operators expect optimized QoS and reduced maintenance and management costs with automated network settings as well as autonomous operation. Achieving these goals demands integrated transmission and IP network management as well as network quality monitoring.

In this exhibit, two 400G ports on Anritsu MT1040A with built-in 400G OpenZR+ transceivers connected via the Add/Drop line are positioned at each end of an Open ROADM system. In addition to making the channel settings from the orchestration system, the system also monitors line quality data from the MT1040A, providing a unified single system for monitoring communication channel changes based on quality data and for evaluating ROADM path changes.

OpenLab @ UT Dallas contributes to verifying hardware and software interoperability specified by OpenROADM MSA. The lab issues test labels certifying devices that pass interoperability verification and feeds back these test results to OpenROADM MSA.

As a result of this collaboration with the orchestration system for managing OpenROADM and IPoDWDM, Anritsu is contributing to the development of systems for configuring future automated and autonomous networks.

Product Details Network Master Pro (400G Tester) MT1040A

MT1040A is a B5 size 400G handheld tester with excellent expandability and operability. It is a touch panel-operated field measurement instrument equipped with a 9-inch screen that is small enough to carry with a single hand. It supports a range of interfaces from 10M up to 400G.

MU104014B is the test module and has the following futures to test 400ZR/ZR+.

• Powerful hardware with cooling for easy handling 400ZR/ZR+ transceivers
• Flexible Settings for All Network Environments
  • Grid, Wavelength, Tx Power setting
  • Coherent monitoring (OSNR, SOP, CD, etc.) via OIF CMIS
  • Media-side FEC monitoring (PreFEC BER) via OIF CMIS
  • 1x 400G, 4x 100G, 2x 100G, 1x 100G client signal
  • Flexible Layer-2 to Layer-4 configuration
• History Function Monitoring Live Network
  • Auto-save all of results at a minimum of 1 second
  • CSV output for detailed analysis and comparison

Technical Terms

[*1] OpenROADM
Defines interoperability specifications for optical transmission equipment (ROADM), optical transponders, and pluggable optical components, as well as YANG data model specifications, and specifies interfaces for achieving interconnectivity and interoperability between each functional part of an optical transmission network in a multi-vendor environment.

[*2] IPoDWDM
Abbreviation for IP over DWDM technology carrying IP packets directly using high-speed DWDM (dense wavelength division multiplexing) technology. The IP layer and optical transport layer are integrated by combining a transceiver such as OpenZR+ with optical transport functions with the IP router interface to help cut planned capital investment and operation costs.

[*3] IETF
Abbreviation for the Internet Engineering Task Force technical organization tasked with assuring and improving internet interoperability. Defines YANG Model specifications for communications protocols and routers.

The post Anritsu and the University of Texas at Dallas Collaborate to Showcase Orchestration System for OpenROADM/IPoDWDM at OFC 2024 appeared first on ELE Times.

Today, NXP announced a new platform and automotive processor that promises more integration and utility in SDVs—no matter the architecture.

Author: STMicroelectronics

The STSPIN32G4 integrates a three-phase gate driver, an STM32G431, and a power management system under one package to solve major engineering challenges, thus enabling new applications. While ST continues to offer STSPIN motor drivers, we also realized that engineers still face several conundrums. Designers want to run more powerful applications but must also shrink their PCBs and reduce costs. Similarly, applications demand more efficiency, but improving it by a few decimal percentage points remains a struggle. ST engineers thus launched the STSPIN32G4 because no other integrated motor controller offered such a powerful mainstream MCU and such a flexible power management system.

STSPIN32G4 and the first challenge: How to make things more powerful in a smaller design? More power under one roof The STSPIN32G4

Let’s take the example of an engineer working on a high-end vacuum cleaner with a high-speed motor. The MCU inside the STSPIN32G4 will stand out, in this instance, because of its computational throughput. A lower-performance CPU core means a lower conversion rate when designing a field-oriented control (FOC) sensorless application. The engineer in the vacuum cleaner example would have to use two or three shunt resistors to compensate for the MCU’s lower performance. On the other hand, the greater computational throughput means a single shunt is sufficient. As a result, using the STSPIN32G4 enables the creation of a powerful application with fewer components.

More peripherals in one device

A team working on a collaborative robot or a guided vehicle would also appreciate the MCU in the STSPIN32G4 for reasons other than the bump in DMIPS. In this instance, engineers must drive two sets of wheels, but traditional motor controllers don’t have enough analog-to-digital converters to handle such a task. As a result, engineers end up using two motor drivers. The STSPIN32G4 is unique because it provides two sets of PWM timers and 12-bit ADCs, among other things. It, therefore, becomes possible to drive two motors with just one integrated device.

Saving 65% space

While it’s impossible to enumerate all the features in the STSPIN32G4, the reality is that its integrated nature is one of the best ways to solve the space challenge. Motor control applications are increasingly smaller, whether for convenience, costs, or to stand out better. Thanks to its integrated nature, the STSPIN32G4 helps reduce the overall design size by 65% compared to discrete solutions. Practically, it allows engineers to put the control system at the back of the motor and design a much smaller e-bike, vacuum cleaner, or power tool, among other things.

STSPIN32G4 and the second challenge: how to make things more energy efficient while keeping costs down? A more efficient power management

According to our benchmarks, using the new device lowers the overall power consumption by 3% to 5% compared to a system that uses external components. A saving of just a single percent already has a significant impact. ST provided such power efficiency by bringing the typical standby consumption to only 15 µA thanks to a very low-quiescent regulator. Hence, we expect engineers to create significantly more compact designs without needing an external cooling system, thus lowering the BoM.

The motor controller also supports a supply voltage of up to 75 V, compared to only 48 V previously. Additionally, the STSPIN32G4 comes with an over-current protection mechanism and a drain-source voltage (VDS) monitoring system that acts as a redundancy. It monitors the external MOSFETs and turns all gate driver outputs off if it detects an over-voltage condition. As a result, we expect engineers to use the STSPIN32G4 in appliances. Indeed, a white good connected to a grid often suffers from wide voltage variations from the mains. The greater supply voltage range and protection features of the new device will better handle these abnormal conditions.

A more flexible power management

Engineers sometimes shy away from integrated solutions, fearing they may restrict their optimization capabilities. Hence, ST ensured a high level of customization. For instance, developers can program registers through an I2C interface to use the STSPIN32G4’s VCC buck converter. Moreover, we published an application note showing how to use the buck regulator in a buck-boost configuration by adding a few external components. Finally, engineers can bypass the buck and LDO regulators to rely on only an external Vcc supply.

Teams that designed a highly precise power supply to meet the stringent requirements of their application can, thus, ignore the STSPIN32G4 regulators. In contrast, others can simplify their designs by using its VCC buck converter to power a few external components, like a memory module. Similarly, developers can choose to enable or disable the standby mode. Such a feature is vital for products like power tools. When users pick a drill after months or even years, they must use it immediately. In such a case, engineers will want to completely disconnect their system from the battery to maximize its usage.

Engineers also get a lot more flexibility in how they drive a motor. They could use a 6-step driver circuit or a field-oriented control, both with or without a sensor and with one, two, or even three shunts. It gives developers the ability to control how much measurement data they gather. Consequently, it also becomes possible to qualify an STSPIN32G4 and use it in many different applications, which can help a company shorten its time to market and optimize its operations.

How to get started The EVSPIN32G4

ST launched two development boards to enable teams to test and experiment with the STSPIN32G4. The EVSPIN32G4 uses STL110N10F7 power MOSFETs and a heat sink to allow an output current of up to 20 A RMS. As a result, teams can push the new devices to develop more powerful designs. However, ST is also mindful that not every designer will use the STSPIN32G4 in high-powered systems. Hence, we are also launching the EVSPIN32G4NH, a similar development board without passive cooling; NH at the end of the nomenclature stands for “no heat sink”. We also updated the X-CUBE-MCSDK to support the new boards and devices.

The EVLSPIN32G4-ACT

More recently, our teams released two reference designs. The EVLSPIN32G4-ACT drives a three-phase brushless motor supporting up to 5 ARMS and can manage a supply input of 48 V for a surprising 250 W total power in a board measuring only 62 mm x 50 mm. Additionally, it can connect to the STWIN.box (STEVAL-STWINBX1) to rapidly create a high-speed data logger. Thanks to our FP-IND-DATALOGMC software pack and Quick Start Guide, engineers have a step-by-step process to connect both boards and run applications that can gather data from the sensors on the STWIN.box and the motor itself. We even offer a GUI to help visualize the information.

The EVSPIN32G4-DUAL

The other board is the EVSPIN32G4-DUAL, which combines the STSPIN32G4 and the STDRIVE101, a triple half-bridge gate driver. As a result, the board can drive two three-phase brushless motors for up to 10 ARMS output current and a supply of 74 V thanks to two power stages. Thanks to the operational amplifiers of the STSPIN32G4, it’s possible to have a sensor-less system with a single shunt current sensing or use Hall sensors and encoders with the embedded MCU. Put simply, the reference design shows how to create a powerful dual motor application in a small factor for home appliances, e-mobility, pumps, tools, and more.

The post STSPIN32G4, The 1st motor controller with an integrated MCU solves 2 major challenges appeared first on ELE Times.

submitted by /u/perpetualwalnut [link] [comments]

With Microchip’s newest dual-pad reference design, designers can start developing with the Qi 2.0 standard.

submitted by /u/BlownUpCapacitor [link] [comments]

Quintessent Inc of Santa Barbara, CA, USA, which specializes in heterogeneous integration of quantum dot lasers and silicon photonic integrated circuits (PICs), has closed on just over $11.5m in an oversubscribed seed funding round led by Osage University Partners (OUP), joined by new investors including M Ventures, and existing investors Sierra Ventures, Foothill Ventures, and Entrada Ventures...

In this project, which uses the Arduino IDE, we create and demonstrate a digital drawing pad using an ESP32-based e-paper display dev board, rotary encoders for drawing control, and an accelerometer for shake detection to initiate an erase.

Pushing ahead with the European Union (EU)-funded photonixFAB initiative, the consortium partners have taken the first step on the path to industrialize the European silicon photonics value chain by providing early access to R&D and small-scale manufacturing through technology partners...

Yet another magic smoke cloud frozen in the transparent gel. The rectifier diode(s) of this unit got overloaded, probably by a short circuit on the power board. https://preview.redd.it/s231wzag0wqc1.png?width=1280&format=png&auto=webp&s=abea0250ccd9b134dc01061b08a0de636e269aee https://preview.redd.it/9aa1nlui0wqc1.png?width=1280&format=png&auto=webp&s=1a42b2a6f35aec10feb93bf2a925eaf8d55ade25 submitted by /u/DrNachtschatten [link] [comments]

Editor’s Note: This is a four-part series of DIs proposing improvements in the performance of a “traditional” PWM—one whose output is a duty cycle-variable rectangular pulse which requires filtering by a low-pass analog filter to produce a DAC. The first part suggests mitigations and eliminations of common PWM error types. The second discloses circuits driven from various Vsupply voltages to power rail-rail op amps and enable their output swings to include ground and Vsupply. The third pursues the optimization of post-PWM analog filters. This fourth part pursues the optimization of post-PWM analog filters.

 Part 1 can be found here.

 Part 2 can be found here.

 Part 3 can be found here.

Recently, there has been a spate of design ideas (DIs) published (see Related Content) which deals with microprocessor-generated pulse width modulators driving low-pass filters to produce DACs. Approaches have been introduced which address ripple attenuation, settling time minimization, and limitations in accuracy. This is the fourth in a series of DIs proposing improvements in overall PWM-based DAC performance. Each of the series’ recommendations is implementable independently of the others. This DI addresses PWM sequence modifications which ease low pass analog filtering requirements.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The tyranny of resolution vs response time

The combination of PWM clock frequency Fclk Hz and the number of bits b of PWM resolution dictates the lowest frequency (Fclk·2-b Hz) output component of a standard PWM. Over all the possible duty cycles, this component is also the largest and therefore the most challenging for an analog filter to suppress. For a given Fclk, the more bits of resolution, the longer the settling time will be of a filter which provides adequate suppression. But there is a way around this limitation.

Suppose a standard 8-bit PWM whose output is either 0 or 1 is configured for a duty cycle of (arbitrarily) 121/256. The first 121 states in a 256-state cycle would be 1 and the remaining 135 would be 0’s. But what if the first 128 states started with 60 ones and the last 128 states started with 61 ones? Let’s call this the “split-in-two” PWM. These two sequences have been offset in amplitude slightly so that they can be clearly seen on a graph shown in Figure 1.

Figure 1 Output sequences of standard and split-in-two 8-bit PWMs with the same clock frequency, period, and duty cycle (121/256).

The blue waveform represents the standard PWM and the orange one is the split-in-two PWM. Why might the latter be advantageous? Consider the spectra of the two PWMs seen in Figure 2.

Figure 2 Frequency content of standard and split-in-two 8-bit PWMs with the same clock frequency, period, and duty cycle (121/256).    

The energy in the first harmonic of the split-in-two PWM is negligible in comparison with that of the standard PWM. The necessary attenuation for the first harmonic has been significantly lessened, and that which was required is now applied to the harmonic at double the frequency. A less aggressive attenuation-with-frequency analog filter can now be employed, resulting in a shorter settling time in response to a change in duty cycle.

Another way to look at this is to double the split-in-two PWM period to 512 states to produce a 9-bit PWM. As shown in Figure 3, the spectra of the two PWMs are almost identical because the time domain waveforms are almost identical—they differ only in that every other 256-bit sequence, one additional one-state replaces a zero-state. The higher resolution 9-bit PWM produces a small amount of energy (less than 1%) at half the frequency of the 8-bit’s fundamental. Any analog low pass filter with adequate suppression of the 8-bit fundamental frequency will more than sufficiently attenuate the signal at half that frequency.

Figure 3 Frequency content of a standard 8-bit PWM of duty cycle 121/256 and a split-in-two 9-bit PWM of duty cycle (121.5/256). They share the same clock, but the split-in-two’s period is twice the standard PWM’s.

The super-cycle

We can think of the split-in-two as generating a “super-cycle” consisting of two cycles of 2b states, each having at least S one-states, with 0 ≤ S < 2b. In one cycle, one zero-state could be swapped for a one-state if the total number of ones in the super-cycle is odd. This is a (b+1)-bit PWM with a period of 2b+1 states. But there is no reason to stop at two. There can be a super-cycle of 2n cycles where n is any integer. With each cycle capable of optionally swapping one zero-state for a one-state, this leads to a PWM super-cycle with a resolution of 2b+n bits. But unlike standard, non-super-cycle PWMs whose maximum spectral energy component is at fclk/2b+n Hz, the super-cycle’s is at a much higher fclk/2b Hz. As with the specific case of the split-in-two, this eases analog filtering requirements and results in a shorter settling time.

It’s worth thinking of a super-cycle as consisting of the sum of two different sequences. One is the S-sequence in which every cycle consists of an identical sequence of S contiguous one-states. The other is the X-sequence where each cycle optionally swaps the first zero-state following the last one-state with another one-state. The X-sequence has X one-states where 0 ≤ X < 2n. The duty cycle of the super-cycle is then (2n·S + X)/2b+n.

When n = 1 for a super-cycle, there is only one cycle where an extra one-state can reside. But when n > 1, X is also greater than one and the question becomes how to distribute the X ones among the 2n cycles so as to minimize the super-cycle’s energy at low frequencies. The fine folks at Microchip who manufacture the SAM D21 microcontroller not only have figured this out for us, but they have also implemented it in hardware [1]! For this IC, it is necessary only to write the values of X and S to separate registers to implement a super-cycle PWM; the hardware does the rest unsupervised. Fortunately, it is simple for almost any microprocessor to augment a standard PWM to implement a super-cycle. For each PWM cycle, the duty cycle count must be modified so that immediately after the sequence of S ones, the first zero gets changed to a one if and only if the following C expression is true for that cycle:

MASK & (cycleNbr * X) > MASK – X

Here, MASK = 2n– 1, X is as before, and cycleNbr is the numeric position of the cycle in the super-cycle. Figure 4 is a graph of the magnitudes of the lowest 32 harmonics of an n = 4, b = 8 super-cycle PWM. The graph provides evidence of the benefit of this approach.

Figure 4 First 32 harmonics of an n=4, b=8 super-cycle PWM. Spectra are displayed for X=1 through 8. (Spectra of X=9 through 15 are the same as those shown.)

The X-sequence’s energy is relatively low, having only 0 through 2n-1 one-states, but it also presents the lowest frequency component, fclk/2n+b Hz. The S-sequence generally contains the most energy by far (except for instances of very small duty cycles), but its smallest frequency component is noticeably higher at Fclk/2b Hz. Among the X sequences, X = 1 gives the largest amplitude for its first harmonic: 2-11 at fclk/2n+b Hz. The S sequence’s spectrum starts at the X sequence’s harmonic number 24 = 16 and produces its largest amplitude of 2/π for that harmonic when S = 211. If this were a standard PWM (an n = 0 super-cycle—no super-cycle at all that is, just a normal PWM), then that amplitude of 2/π would appear at frequency which is 16 times lower. The standard PWM presents a much more severe filtering problem. Its filter would take a lot longer to settle in response to a duty cycle change because of the much larger amount of low frequency attenuation required.

Comparing the filters for (n+b)-bit standard and super-cycle PWMs

The filtered AC steady state time-domain contributions of both the standard and the super-cycle (with its X and S sequences) PWMs should be less than some fraction α of the voltage of the PWMs’ one-state. A reasonable value of α is 2-(n+b+1), ½ LSB. This translates to an attenuation factor of 1/4 at the first harmonic of the X sequence. It is fortunate that even a simple two-component R-C filter meeting this requirement will sufficiently attenuate all higher X sequence harmonics, so there are no additional constraints to meet to suppress them. The 16th X harmonic frequency is that of the first S harmonic. Its PWM energy requires an attenuation factor of (π/2)·2-(n+b+1) at a 50% duty cycle. Again, any low pass filter meeting this requirement will adequately attenuate the remaining S-sequence harmonics. For an Fclk = 20 MHz, Figure 5 and Figure 6are graphs of the frequency and time domain step responses of 3rd order filters (two op-amps, 3 resistors, and 3 capacitors) meeting these requirements for standard 12-bit and super-cycle n = 4, b = 8  (12-bit) PWMs.

Figure 5 The frequency responses of filters for standard and super-cycle n = 4 bit PWMs with 12 bits of resolution. The maxima of the peaked waveforms are the maximum responses allowed for the filters at the peaked frequencies. The filters ensure that the steady state time domain energy at their outputs is less than ½ LSB of Full Scale.

Figure 6 The log of the absolute value of time responses of filters for standard and super-cycle n = 4 bit PWMs with 12 bits of resolution. The much shorter settling time of the super-cycle PWM is clearly evident.

 Easing low pass analog filter requirements

When partnered with an appropriate analog filter, an approach to PWM embodiment available in hardware in an existing microprocessor [1] offers significantly shorter settling times than does a standard PWM. This approach can be implemented with the aid of a small amount of software in almost any microcontroller.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

Related Content

• Double up on and ease the filtering requirements for PWMs
• Optimizing a simple analog filter for any PWM
• Fast-settling synchronous-PWM-DAC filter has almost no ripple
• Cancel PWM DAC ripple and power supply noise
• Cancel PWM DAC ripple with analog subtraction
• Cancel PWM DAC ripple with analog subtraction—revisited
• Cancel PWM DAC ripple with analog subtraction but no inverter
• Fast PWM DAC has no ripple

 References

1. https://ww1.microchip.com/downloads/en/DeviceDoc/SAM-D21DA1-Family-Data-Sheet-DS40001882G.pdf(See section 31.6.3.3.)

The post Parsing PWM (DAC) performance: Part 4 – Groups of inhomogeneous duty cycles appeared first on EDN.

Automotive-qualified gallium nitride (GaN) open foundry BelGaN of Oudenaarde, Belgium has qualified its BEL1 first-generation 650V eGaN platform for volume production for several lead customers that placed orders. After achieving this milestone within just two years, BelGaN is now ready to scale up as a high-volume GaN foundry in Europe...