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Infineon Technologies AG has successfully completed its Share Buyback Program 2024, announced on 26 February 2024 in accordance with Article 5(1)(a) of Regulation (EU) No 596/2014 and Article 2(1) of Delegated Regulation (EU) No 2016/1052. As part of the Share Buyback Program 2024, a total of 7,000,000 shares (ISIN DE0006231004) were acquired. The total purchase price of the repurchased shares was € 232,872,668. The average purchase price paid per share was € 33.27.

Alexander Foltin, Head of Finance, Treasury and Investor Relations of Infineon

The buyback was carried out on behalf of Infineon by an independent credit institution via Xetra trading on the Frankfurt Stock Exchange, serving the sole purpose of allocating shares to employees of the company or affiliated companies, members of the Management Board of the company as well as members of the management board and the board of directors of affiliated companies as part of the existing employee participation programs.

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Are you ready to showcase your design talent and celebrate a remarkable milestone with PCBWay? We’re excited to announce the PCBWay 10th Badge Design Contest, inviting designers, makers, and dreamers like you to join us in commemorating our journey of innovation over the past 10 years and looking ahead to the future.

Introduction of PCBWay:

At PCBWay, we’re not just a company; we’re a community of innovators, dreamers, and makers dedicated to pushing the boundaries of technology and bringing ideas to life. Since our inception, we have been a driving force in the electronics industry, providing cutting-edge solutions and unparalleled service to our customers worldwide.

With a decade of experience under our belt, we have earned a reputation for excellence, reliability, and innovation. From PCB manufacturing to assembly, prototyping, and beyond, we offer a comprehensive suite of services tailored to meet the diverse needs of our clients.

Celebrating 10 Years of PCBWay:

Since our inception, PCBWay has been at the forefront of innovation, revolutionizing the electronics industry with our cutting-edge solutions and unwavering commitment to excellence. As we mark our 10th anniversary, we want to celebrate this incredible journey with you, our valued community members, who have been instrumental in our success.

PCBWay Capabilities:

1. Expert PCB Design:

With years of experience, our team excels in PCB design, handling projects of varying complexity with precision.

1. Comprehensive Solutions:

From initial 3D designs to hardware and software development, we offer end-to-end solutions for seamless integration and optimal performance.

1. Swift Turnaround:

Our powerful design capabilities ensure quick completion of PCB layouts, meeting tight deadlines without compromising quality.

1. Advanced Manufacturing:

We provide a range of manufacturing services including 3D printing, CNC machining, PCB fabrication, and assembly. Utilizing cutting-edge equipment and techniques, we deliver high-quality results for prototypes and mass production.

Explore PCBWay’s capabilities and milestones showcased on our Projects page. From innovative designs to remarkable achievements, witness our journey of excellence in the electronics industry. Discover how we’ve transformed ideas into reality and empowered creators worldwide. Join us in celebrating our achievements and exploring the endless possibilities at PCBWay Projects.

The Theme: A Decade of Innovation with PCBWay:

The theme of our contest encapsulates the essence of our journey: “A Decade of Innovation with PCBWay.” We invite you to unleash your creativity and design a badge that pays homage to the milestones we’ve achieved over the past decade while envisioning the limitless possibilities that lie ahead.

Design Requirements:

Your badge design must incorporate two key elements: the “PCBWay” logo and the number “10.” Feel free to explore various techniques, including PCB, PCB+SMT/THT, and PCB+3D printing, to create something that is not only visually captivating but also functional and innovative.

To access the PCBWay logo vector, simply click here.

How to Submit Your Design:

Submitting your design is easy! You can send it to us via email at sponsor@pcbway.com. Don’t forget to use the hashtag #PCBWay10BadgeContest when sharing your designs on social media to ensure maximum visibility.

Exciting Prizes Await:

We believe in rewarding creativity and innovation. That’s why the winner of our contest will receive a generous cash prize of $1,000! Additionally, two runner-ups will each receive a $200 PCBWay coupon.

But that’s not all! Selected designs that meet our requirements will be featured on our official channels and may even become the official badge for PCBWay’s 10th anniversary. Plus, we’ll provide a free prototyping service for these badges along with a $50 PCBWay coupon.

Important Dates to Remember:

Contest Opens: March 12, 2024

Submission Deadline: May 31, 2024

Winner Announcement: June 15, 2024

Join Us in Celebrating a Decade of Innovation:

This contest is more than just an opportunity to win prizes; it’s a chance to reflect on the incredible journey we’ve embarked on together over the past 10 years and to dream about the future possibilities with PCBWay.

So what are you waiting for? Dust off your design tools, unleash your creativity, and join us in celebrating a decade of innovation with PCBWay. We can’t wait to see the innovative and creative badges you design!

At PCBWay, we’re not just celebrating our 10th anniversary; we’re celebrating a decade of innovation, collaboration, and endless possibilities. Join us as we continue to shape the future of electronics and inspire the next generation of creators.

For design inspiration, visit PCBWay community: https://www.pcbway.com/project/

Join us TODAY and be a part of this momentous celebration.

The post Celebrate a Decade of Innovation with PCBWay: Join Our 10th Badge Design Contest! appeared first on Electronics Lovers ~ Technology We Love.

PCBWay stands as a prominent figure in the realm of printed circuit board (PCB) manufacturing and assembly services, offering a comprehensive suite of solutions tailored to meet the diverse needs of clients worldwide. With a reputation built on quality, reliability, and innovation, PCBWay prides itself on delivering cutting-edge PCB solutions that exceed industry standards. From rapid prototyping to full-scale production runs, PCBWay caters to a wide spectrum of requirements, including rigid, flexible, and rigid-flex PCBs, as well as advanced PCB assembly services. With a commitment to excellence and a customer-centric approach, PCBWay remains at the forefront of PCB technology, empowering businesses and individuals alike to bring their ideas to life with precision and efficiency.

PCBWay has recently introduced several upgrades to their flexible PCB offerings. These enhancements encompass new parameters and special processes, enriching the versatility and customization options available to customers. Let’s delve into each of these new features to understand their significance in the realm of flexible PCB fabrication.

New Parameters:

Expanded Layer Support:

PCBWay now supports flexible PCBs with up to 16 layers, providing customers with increased design flexibility and complexity.

High-Frequency Polyimide Option:

The addition of “High Frequency (DKs3.6)” for polyimide base material enables the fabrication of flexible PCBs optimized for high-frequency applications, such as wireless communication systems.

Transparent/Translucent PET Option:

Introducing “Transparent/Translucent” as an option for PET (polyethylene terephthalate) in the polyimide base material column offers aesthetically pleasing and visually appealing flexible PCB solutions.

Variable FPC Thickness:

Customers can now select from a range of thickness options for one-layer (0.025/0.05mm) and two-layer (0.08mm) flexible PCBs, catering to diverse application requirements.

Versatile Stiffener Choices:

The inclusion of “TOP Black FR4/BOT Black FR4” stiffeners, along with various thickness options (0.2mm/0.4mm/0.5mm/0.6mm/0.8mm/1.0mm/1.2mm/1.5mm), facilitates enhanced mechanical support and rigidity for flexible PCB designs.

Conductive Double-Sided Tape Options:

With the introduction of new drop-down options such as “HT-A1134/HDF-600/without,” customers can select the most suitable conductive double-sided tape for their specific application needs, ensuring reliable adhesion and electrical connectivity.

Increased Order Quantity Limit:

The updated order quantity limit of 3000 for flexible PCBs allows for larger production runs, enabling scalability and cost-effectiveness for mass production projects.

New Special Processes:

Stiffener Between Top and Bottom Edge Connector: This special process enhances the structural integrity and durability of flexible PCBs, particularly in applications where edge connectors are subjected to mechanical stress or handling.

• Single-Side Double Access: Offering access from both sides of the flexible PCB on a single layer provides greater flexibility in routing and connecting components, optimizing layout efficiency and minimizing space constraints.
• Peelable Soldermask: Peelable soldermask allows for easy removal or rework of solder mask material, enabling modifications or repairs to be carried out with precision and ease.
• Via Filled with Copper: Filling vias with copper enhances conductivity and thermal dissipation, improving the overall performance and reliability of flexible PCBs, especially in high-current or high-frequency applications.
• Edge Plating: Edge plating reinforces the edges of flexible PCBs with additional copper layers, enhancing structural integrity, EMI shielding, and solder joint reliability.
• Half-Cut: The half-cut process involves partially cutting through the flexible PCB substrate, allowing for precise bending or folding of the board without compromising electrical connectivity or mechanical strength.

The stack-up of FPC (Flexible Printed Circuit)

The stack-up of FPC (Flexible Printed Circuit) with an air gap refers to the arrangement of layers within a flexible PCB where intentional gaps or spaces are introduced between certain layers. These gaps are filled with air, creating a void or airspace within the PCB structure.

The purpose of incorporating air gaps in the FPC stack-up is to achieve specific design objectives such as:

Reduced Dielectric Constant:

By introducing air as a dielectric material between layers, the overall dielectric constant of the PCB can be lowered. This can be advantageous in high-frequency applications where minimizing signal loss and maintaining signal integrity are critical.

Controlled Impedance:

Air gaps can help in controlling the impedance of transmission lines within the flexible PCB. By adjusting the dimensions and placement of air gaps, designers can achieve precise impedance matching for signals traveling through the PCB.

Improved Thermal Management:

Air has lower thermal conductivity compared to solid dielectric materials used in PCBs. Introducing air gaps can help in thermal isolation, reducing heat transfer between adjacent layers and improving thermal management within the flexible PCB.

Flexibility Enhancement:

In some cases, air gaps can enhance the flexibility and bendability of the flexible PCB. By strategically placing air gaps in areas where bending or folding is expected, designers can prevent stress concentrations and potential damage to the PCB during flexing.

Overall, the incorporation of air gaps in the FPC stack-up offers designers a versatile tool to optimize the performance, reliability, and manufacturability of flexible printed circuits for a wide range of applications.

In conclusion, PCBWay’s upgraded flexible PCB features empower customers with a comprehensive suite of options to tailor their designs according to specific performance, aesthetic, and production requirements. PCBWay provides comprehensive support for FPC manufacturing, including custom stack-up options, specialized processes like peelable solder mask, and a variety of material choices to meet the unique requirements of each project. Additionally, PCBWay offers services for rigid-flex PCBs, which combine the benefits of both rigid and flexible PCBs into a single design. These enhancements underscore PCBWay’s commitment to delivering innovative solutions and exceptional quality in the realm of flexible PCB fabrication.

The post Exploring PCBWay’s Enhanced Flexible PCB Features appeared first on Electronics Lovers ~ Technology We Love.

Company introduces Context Grounding to augment GenAI models with business-specific data, an IBM watsonx.ai connector, and updates for Autopilot

UiPath, a leading enterprise automation and AI software company, recently announced several new generative AI (GenAI) features in its platform designed to help enterprises realize the full potential of AI with automation by accessing powerful, specialized AI models tailored to their challenges and most valuable use cases. UiPath showcased its latest capabilities at the virtual AI Summit that took place on March 19th, 2024.

The UiPath Business Automation Platform offers end-to-end automation for business processes. There are four key factors that business leaders seeking to embed AI in their automation program must keep top of mind: business context, AI model flexibility, actionability, and trust. The new AI features of the UiPath Platform address these key areas to ensure customers are equipped with the tools necessary to enhance the performance and accuracy of GenAI models and tools and more easily tackle diverse business challenges with AI and automation.

“Businesses need an assortment of AI models, the best in class for every task, to achieve their full potential. Our new family of UiPath LLMs, along with Context Grounding to optimize GenAI models with business-specific data, provide accuracy, consistency, predictability, time to value, and empower customers to transform their business environments with the latest GenAI capabilities on the market,” said Graham Sheldon, Chief Product Officer at UiPath. “These new features ensure that AI has the integrations, data, context, and ability to take action in the enterprise with automation to meet our customers’ unique needs.”

At the AI Summit, UiPath announced:

Generative Large Language Models (LLMs) 

The new LLMs, DocPATH and CommPATH, give businesses LLMs that are extensively trained for their specific tasks, document processing and communications. General-purpose GenAI models like GPT-4 struggle to match the performance and accuracy of models specially trained for a specific task. Instead of relying on imprecise and time-consuming prompt engineering, DocPATH and CommPATH provide businesses with extensive tools to customize AI models to their exact requirements, allowing them to understand any document and a huge variety of message types.

Context Grounding to augment GenAI models with business-specific data

Businesses need a safe, reliable, low-touch way to use their business data with AI models. To address this need, UiPath is introducing Context Grounding, a new feature within the UiPath AI Trust Layer that will be entering private preview in April. UiPath Context Grounding helps businesses improve the accuracy of GenAI models by providing prompts and a foundation of business context through retrieval augmented generation. This system extracts information from company-specific datasets, like a knowledge base or internal policies and procedures to create more accurate and insightful responses.

Context Grounding makes business data LLM-ready by converting it to an optimized format that can easily be indexed, searched, and injected into prompts to improve GenAI predictions. Context Grounding will enhance all UiPath Gen AI experiences in UiPath Autopilots, GenAI Activities, and intelligent document processing (IDP) products like Document Understanding.

GenAI Connectors & IBM watsonx.ai

IBM used the UiPath Connector Builder to create a unique watsonx.ai connector. The new connector provides UiPath customers with access to multiple foundational models currently available in watsonx.ai. GenAI use cases, such as summarization, Q&A, task classification, and optimization for chat, are quickly integrated and infused into new and existing UiPath workflows and frameworks. IBM Watsonx customers can also access broader UiPath platform capabilities, such as Test Automation, Process Mining and Studio workflows, all within a low/no-code UX environment. IBM’s industry-leading consulting capabilities, coupled with the UiPath Business Automation Platform, will help support successful GenAI adoption, including the right strategy for infusing AI into more powerful, and complex automated workflows.

“IBM and UiPath strongly believe that AI and GenAI are rapidly changing the entire landscape of business globally,” said Tom Ivory, Senior Partner, Vice President, Global Leader of Global Automation at IBM. “We are excited that IBM’s watsonx.ai and UiPath’s Connector Builder together now help create insights, and efficiencies that result in real value for our customers.”

The IBM Watson Connector is now generally available through the Integration Service Connector Catalog.

Autopilot for Developers and Testers

UiPath Autopilot is a suite of GenAI-powered experiences across the platform that make automation builders and users more productive. Autopilot experiences for Developers and Testers are now available in preview with a targeted general availability in June. Over 1,500 organizations are using UiPath Autopilot resulting in over 7,000 generations and over 5500 expressions generated per week.

Autopilot for Developers empowers both professional and citizen automation developers to create automation, code, and expressions with natural language, accelerating every aspect of building automation.

Autopilot for Testers transforms the testing lifecycle, from planning to analysis, reducing the burden of manual testing and allowing enterprise testing teams to test more applications faster. Autopilot for Testers empowers testing teams to rapidly generate step-by-step test cases from requirements and any other source documents, generate automation from test steps, and surface insights from test results, allowing testers to identify the root cause of issues in minutes, not hours or days.

Prebuilt GenAI Activities for faster time-to-value

New prebuilt GenAI Activities utilize the UiPath AI Trust Layer and are easy to access, develop with, and leverage high-quality AI predictions in automation workflows that deliver faster time to value. GenAI Activities provides access to a growing collection of GenAI use cases, such as text completion for emails, categorization, image detection, language translation, and the ability to filter out personally identifiable information (PII) enabling enterprises to do more with GenAI. With GenAI Activities, enterprises can reduce the time to build and achieve a competitive edge using GenAI to help customize the customer experience, optimize supply chains, forecast demands, and make informed decisions.

The post UiPath Unveils New Family of LLMs at AI Summit to Empower Enterprises to Harness Full Capabilities of GenAI appeared first on ELE Times.

New edition of database tracks 33% more facilities and highlights advanced packaging and factory certifications

The new edition of the Worldwide Assembly & Test Facility Database expands coverage to 670 facilities, 33% more than the previous release, including 500 outsourced semiconductor assembly and test (OSAT) service providers and 170 integrated device manufacturer (IDM) facilities, SEMI and TechSearch International announced today. The database is the only commercially available listing of assembly and test suppliers that provides comprehensive updates on packaging and testing services offered by the semiconductor industry.

The updated database includes factory certifications in critical areas such as quality, environmental, security and safety as well as data reflecting automotive quality certifications obtained by each site. The new edition also highlights advanced packaging offerings by each factory, defined as flip chip bumping and assembly, fan-out and fan-in wafer-level packaging (WLP), through silicon via (TSV), 2.5D and 3D capability.

“Understanding the location of legacy packaging as well as advanced packaging and test is essential to effective supply-base management,” said Jan Vardaman, President at TechSearch International. “The updated Worldwide Assembly & Test Facility Database is an invaluable tool in tracking the packaging and assembly ecosystem.”

“The database increases its focus on advanced packaging while highlighting conventional packaging capabilities and new test capabilities to support innovations in key end markets including automotive,” said Clark Tseng, Senior Director of SEMI Market Intelligence.

Combining the semiconductor industry expertise of SEMI and TechSearch International, the Worldwide Assembly & Test Facility Database update also lists revenues of the world’s top 20 OSAT companies and captures changes in technology capabilities and service offerings.

Covering facilities in the Americas, China, Europe, Japan, Southeast Asia, South Korea and Taiwan, the database highlights new and emerging packaging offerings by manufacturing locations and companies. Details tracked include:

• Plant site location, technology, and capability: Packaging, test, and other product specializations, such as sensor, automotive and power devices
• Packaging assembly service offerings Ball grid array (BGA), specific leadframe types such as quad flat package (QFP), quad flat no-leads (QFN), small outline (SO), flip-chip bumping, WLP, Modules/System in Package (SIP), and sensors
• New manufacturing sites announced, planned or under construction

Key Report Highlights

• The world’s top 20 OSAT companies in 2022 with financial comparisons to 2021, as well as preliminary comparisons to 2023
• 150-plus facility additions compared to the 2022 report
• 200-plus companies and more than 670 total back-end facilities
• 325-plus facilities with test capabilities
• 100-plus facilities offering QFN
• 85-plus bumping facilities, including more than 65 with 300mm wafer bumping capacity
• 90-plus facilities offering WLCSP technology
• 130-plus OSAT facilities in Taiwan, more than 150 in China, and more than 60 in Southeast Asia
• 50-plus IDM assembly and test facilities in Southeast Asia, about 45 in China, nearly 20 in Americas and more than 12 in Europe
• More than 30% of global factories offering advanced packaging capabilities in one of the following areas: flip chip bumping and assembly, fan-out and fan-in WLP, TSV, 2.5D and 3D

Worldwide Assembly & Test Facility Database licenses are available for single and multiple users. SEMI members save up to 25% on licenses. Download a sample of the report and see pricing and ordering details.

For more information on the database or to subscribe to SEMI market data, visit SEMI Market Data or contact the SEMI Market Intelligence Team (MIT) at mktstats@semi.org.

The post Expanded Semiconductor Assembly and Test Facility Database Tracks OSAT and Integrated Device Manufacturers in 670 Facilities, SEMI and TechSearch International Report appeared first on ELE Times.

Author: STMicroelectronics

Where are embedded systems heading in 2024, and how can makers stay ahead of the curve? Few people used to ask these questions a decade ago. Today, the answers can make or break entire companies. Indeed, once relegated to a few niche applications, embedded systems are now everywhere. From factories to home appliances or from expensive medical devices in hospitals to ubiquitous wearables, every time we become more connected or more sustainable, an embedded system is usually at the heart of innovations. ST will thus hold the STM32 Summit on March 19 to introduce our community to the latest technologies shaping our industry. In the meantime, let’s step back to see where 2024 is taking us.

Computational efficiency or doing more with less

Avid readers of the ST Blog know that greater efficiency is often a key driver of our innovations. However, we may need to broaden our understanding of “efficiency”. In essence, efficiency is the ratio of work done per amount of energy spent. In the microcontroller world, it refers to electrical efficiency. Hence, improving efficiency means lowering the power consumption while offering the same or more computational throughput. However, as embedded systems applications become vastly more optimized, a new efficiency ratio shapes the industry: application complexity for a given computational throughput.

To illustrate this point, let’s use a simple thought experiment. Imagine bringing today’s high-performance MCU back in time just five years ago. That device could not run the neural network or rich UIs it can run today because frameworks and machine learning algorithms were far cruder. The reason is that embedded systems aren’t just more powerful but that new applicative optimizations have made them more capable. Consequently, the same amount of computational power yields far greater results today.

Trained vs. pruned and quantized with TAO Toolkit

For instance, the quantization of neural networks enabled more powerful edge AI systems. In the case of a recent demo with Schneider Electric, a deeply quantized neural network meant that a people-counting application ran on an STM32H7. And NVIDIA featured the same MCU when running a network optimized with its TAO Toolkit and STM32Cube.AI. Similarly, new motor control algorithms, like ZeST, mean MCUs drive motors more accurately and efficiently, and new UI framework optimizations mean richer graphics while needing less memory. For instance, the latest version of TouchGFX supports vector fonts, and our latest STM32U5 has an IP accelerating vector graphics, which wouldn’t have been as impressive without the graphical framework to help developers take advantage of it.

Consequently, engineers must not only ensure their embedded processing solutions is reducing their power consumption but that it also runs the latest optimizations. In many instances, a real-time application is no longer just basic code running in a while loop. Developers must find new ways to leverage the cloud, machine learning, sensor fusion, or graphical interfaces. Hence, it is critical to find the right MCU supported by an entire ecosystem that can bring these new optimizations to them. Engineers must ask how fast a device runs and how well it can support the complexity and richness of the application.

Multiple wireless protocol support or talking more with the world A wireless utility metering system

The idea that an embedded system connects to a network is far from new. The industry even coined the term “Internet of Things” because so many applications rely on the network of networks. However, until now, applications have primarily chosen one mode of communication, either wired or wireless. And if the latter, it used to settle on one wireless protocol, such as cellular, Wi-Fi, or Bluetooth. Over the years, the industry has seen the multiplication of wireless protocols. From 6LoWPAN to LoRaWAN, Zigbee, Thread, NB-IoT, and more, there’s no shortage of new protocols. Interestingly, there has also been the absence of a clear winner. Instead of a traditional consolidation, many technologies seem to prosper concomitantly.

Let’s take the 2.4 GHz spectrum as an example. While Bluetooth is still dominant, Zigbee and Thread have grown in popularity. Many companies also work on a custom IEEE 802.15.4 protocol for competitive or regulatory reasons. In fact, the proliferation of network protocols is so rampant that Matter, the latest initiative unifying home automation under one standard, runs over multiple wireless technologies like Wi-Fi, Thread, and Bluetooth and supports many 2.4 GHz bridges, including Zigbee and Z-Wave instead of settling on just one wireless technology.

As a result, engineers face a relatively new challenge: create a system that must support multiple wireless protocols to stay competitive. Indeed, by adopting a device that supports multiple technologies, a company can qualify one MCU and adapt to the needs of the market. For instance, a developer could work on a proprietary IEEE 802.15.4 protocol in one region, and then adopt Thread in another while keeping the exact same hardware. It would only require a change to the code base. Engineers would thus reduce their time to market and enjoy far greater flexibility. Put simply, embedded systems developers in 2024 must design with multi-protocol support in mind and choose devices that will meet current and future needs.

Security or protecting future investments Security must be a top priority for smart home products

One positive trend in embedded systems has been recognizing that security is not optional. For the longest time, many joked that IoT stood for “Internet of Threats”. Today, developers know it is imperative to protect servers, code, end-user data, and even physical devices from attacks. In a nutshell, a failure to secure an embedded system could have catastrophic effects on the product and its brand. However, a new security challenge has emerged in the form of regulatory interventions. The European Union, the United States, and many other countries and standardizing bodies have enacted new rules mandating features and protections. The problem is that they aren’t always clear or final, as some are still being worked on.

The industry has been answering this new challenge with more formal security standards. For instance, the Platform Security Architecture (PSA) and the Security Evaluation Standard for IoT Platforms (SESIP) certifications offer an extensive methodology to help engineers secure their embedded systems. These certifications thus provide a path to future-proof designs and ensure they meet any stringent requirements. However, it also means that developers can’t treat security as an afterthought or work toward those certifications after designing their system. It is becoming critical to think of security as soon as the first proof of concept and adopt a microcontroller that can meet the proper certification level.

Let’s take the example of a smart home application that shares private and sensitive data with a cloud. Increasingly, governments require encrypted communications, protections against physical attacks, safeguards against software intrusions, the ability to securely update a system over-the-air, and monitoring capabilities to detect a breach. In many instances, a SESIP Level 3 certification would help guarantee that a system could meet those requirements. Unfortunately, engineers who fail to choose an MCU capable of targeting such a certification could end up compromising the entire project. As there are hardware and platform considerations that ensure a product can meet a certain security certification, developers must adopt a new mindset when choosing an MCU.

See what the future holds at the STM32 Summit See how the STM32 Summit can help you anticipate upcoming trends

As we look at the trends that will shape 2024 and beyond, we see that it is critical to find an ecosystem maker. Computational efficiency depends on the MCU as well as the framework, middleware, and algorithms that run on it. Similarly, supporting multiple wireless protocols demands new development tools, and securing embedded systems requires practical software solutions on top of hardware IPs. That’s why we are excited to host the STM32 Summit on March 19. Join us as we showcase how ST is bringing solutions to help teams stay ahead of upcoming trends.

Viewers will get to learn more about exciting devices that are shaping new trends while also discovering entirely new products. Attendees will also be able to ask questions to ST experts and receive answers live. Registering to this event thus grants a unique access to our teams. Moreover, the STM32 Summit will feature some of our customers who will share real-world experiences. Instead of ST telling the industry how to meet the challenges ahead, we wanted our partners to show viewers how they do it. Put simply, the STM32 Summit isn’t only here to inform but to inspire.

The post STM32 Summit: 3 important embedded systems trends for 2024 appeared first on ELE Times.

Odyssey Semiconductor Technologies Inc of Ithaca, NY, USA — which develops high-voltage vertical power switching components based on proprietary gallium nitride (GaN) processing technology — has entered into a definitive agreement to sell its assets for $9.52m in cash to “a large semiconductor company”...

A few days ago I asked this subreddit and a few other subreddits how to fix white noise issue of IEMs while using with laptop. A lot of you suggested to get an impedance adapter. However those are very expensive despite that the device is actually a very simple circuit that can be made at home with some soldering ability. So that's what I did and it solved the issue. I got the schematic from this guide on diyaudioheaven and made the circuit on a small piece of perfboard/Veroboard. Things required: Small Veroboard 4 resistors, preferably less than 100 ohm An audio socket An audio cable For soldering: a soldering iron and a small amount of solder wire. Here is the picture of what I made. https://preview.redd.it/uomy1le1qbpc1.jpg?width=4160&format=pjpg&auto=webp&s=c7dfcc427298a8b7ab5f28559f223b154dcdb809 I am not putting the image of the backside where all the connections are made because I've taped it and I am too lazy to remove and reapply and also because it won't help anyone who won't understand the original schematic in the first place. I didn't notice any change in the sound quality however people listening to music might notice as the connections are not super precise. I use my IEMs to listen to lectures and podcasts, the white noise was getting very annoying in any long hearing sessions, which my circuit solved. In the end I am glad. submitted by /u/LivingGraveGround [link] [comments]

Mersen of Courbevoie, France (which focuses on electrical power and advanced materials for high-tech industries) is to benefit from subsidies totaling over €12m under the European Commission’s Important Project of Common European Interest program in MicroElectronics and Communication Technologies (IPCEI ME/CT)...

Awhile back I published a simple design idea for a thermal airspeed sensor based on a self-heated Darlington transistor pair. The resulting sensor is simple, sensitive, and solid-state, but suffers from a radically nonlinear airspeed response, as shown in Figure 1.

Figure 1 The Vout versus airspeed response of the thermal sensor is very nonlinear.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Veteran design idea contributor Jordan Dimitrov has provided an elegant computational numerical solution for the problem that makes the final result nearly perfectly linear. He details it in Proper function linearizes a hot transistor anemometer with less than 0.2 % error.

However, a consequence of performing linearization in the digital domain after analog to digital conversion is a significant increase in required ADC resolution, e.g., from 11 bits to 15, here’s why…

Acquisition of a linear 0 to 2000 fpm airspeed signal resolved to 1 fpm would require an ADC resolution of 1 in 2000 = 11 bits. But inspection of Figure 1’s curve reveals that, while the full scale span of the airspeed signal is 5 V, the signal change associated with an airspeed increment of 1999 fpm to 2000 fpm is only 0.2 mV. Thus, to keep the former on scale while resolving the latter, needs a minimum ADC resolution of:

 1 in 5 / 0.0002 = 1 in 25,000 = 14.6 bits

15-bit (and higher resolution) ADCs are neither rare nor especially expensive, but they’re not usually integrated peripherals inside microcontrollers as mentioned in Mr. Dimitrov’s article. So, it seems plausible that a significant cost might be associated with provision of an ADC with resolution adequate for his design. I wondered about what alternatives might exist.

Here’s a design for simple and cheap high-resolution ADC built around an old, inexpensive, and widely available friend: the 555 analog timer chip. 

See Figure 2 for the schematic.

Figure 2 High resolution voltage-to-time ADC suitable for self-heated transistor anemometer linearization. An asterisk denotes precision components (1% tolerance).

 Signal acquisition begins with the R2, R3, U1 summation network combining the 0 to 5 V input signal with U1’s 2.5v precision reference to form:

V1 = (Vin + 2.5v)/2 = 1.25 to 3.75v = (0 to 3) * 1.25v

 V1 accumulates on C1 between conversion cycles with a time constant of:

(R2R3/(R2 + R3) + R1)C1 = 1.1M * 0.039 µF = 42.9 ms

 Thus, for 16 bit accuracy, a minimum settling time is required of:

42.9 ms LOGe(216) = 480 ms

 The actual conversion cycle can then be started by inputting a CONVERT command pulse (>2.5v amplitude and >1 microsecond duration) to the 555 Vth (threshold) pin 6 as illustrated in Figure 3.

 Figure 3 ADC cycle begins with a CONVERT Vth pulse that generates an OUT pulse of duration Tout = LOGe(V1 / 1.25 V)R1C1.

The OUT pulse (low true) begins with the rising edge of CONVERT and is coincident with the 555 Dch (discharge) pin 7 being driven to zero volts, beginning the discharge of C1 from V1 to the 555 trigger voltage (Vtrg = Vc/2 = 1.25v) on pin 7. The duration of C1 discharge and Tout, accumulated digitally (a counter of 16 bits and resolution of 1µs is adequate) by a suitable microcontroller, are given by:

Tout = LOGe(V1 / 1.25 V)R1C1 = LOGe(V1 / 1.25 V) 1M * 0.039 µF

= LOGe((Vin + 2.5 V) / 2.5 V) 39 ms

= LOGe(1) 39 ms = 0 for Vin = 0

= LOGe(3) 39 ms = 42.85 ms for Vin = 5 V

At the end of Tout, Dch is released so the recharge of C1 can commence, and the conversion result:

(N = 1 MHz * Tout)

is available for linearization computation. The math to decode and recover Vin is given by:

Vin = 2.5 V (EXP(N / 39000) – 1)

A final word. You may be wondering about something. Earlier I said a resolution of 1 part in 25000 = 14.6 bits would be needed to quantify the Vin delta between 1999 and 2000 fpm. So, what’s all this 42850 = 15.4 bits stuff?

The 42850 thing arises from the fact that the instantaneous slope (rate of change = dV/dT) of the C1 discharge curve is proportional to the voltage across, and therefore the current through, R1. For a full-scale input of Vin = 5 V, this parameter changes by a factor of 3 from V1 = 3.75 V and 3.75 µA at the beginning of the conversion cycle to only 1.25 V and 1.25 µA at the end. This increase in dV/dT causes a proportional but opposite change in resolution. Consequently, to achieve the desired 25000:1 resolution at Vin = 5 V, a higher average resolution is needed.

The necessary resolution factor bump is square root (3) = 1.732… of which 42850 / 25000 = 1.714 is a rough and ready, but adequate, approximation.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

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The post 15-bit voltage-to-time ADC for “Proper Function” anemometer linearization appeared first on EDN.

Efficient Power Conversion Corp (EPC) of El Segundo, CA, USA — which makes enhancement-mode gallium nitride on silicon (eGaN) power field-effect transistors (FETs) and integrated circuits for power management applications — has announced the availability of the EPC9193, a 3-phase brushless DC (BLDC) motor drive inverter using the EPC2619 eGaN FET. The EPC9193 operates with a wide input DC voltage ranging from 14V and 65V and has two configurations — a standard unit and a high-current version...

The u-blox F10 platform increases positioning accuracy by reducing multipath effects, simplifying the process of promptly locating a vehicle.

u-blox, a global provider of leading positioning and wireless communication technologies and services, has announced F10, the company’s first dual-band GNSS (Global Navigation Satellite Systems) platform combining L1 and L5 bands to offer enhanced multipath resistance and meter-level positioning accuracy. The platform caters to urban mobility applications, such as aftermarket telematics and micromobility.

Applications that use GNSS receivers for accurate positioning are on the rise. Yet, current receivers do not fully perform in urban areas. Accurate and reliable positioning in dense urban environments, where buildings or tree foliage can reflect satellite signals, requires GNSS receivers to mitigate multipath effects. The L5 band’s resilience to these effects significantly improves positioning accuracy. Combined with the well-established L1 band, an L1/L5 dual-band GNSS receiver can deliver < 2 m positioning accuracy (CEP50), against about 4 m with the L1 band only. The u-blox team has conducted driving tests in several urban areas, confirming a significant improvement over GNSS L1 receivers.

The F10’s firmware algorithm prioritizes L5 band signals in weak signal environments, ensuring reliable positioning accuracy even when paired with small antennas. The platform is also equipped with protection-level technology that provides a real-time trustworthy positioning accuracy estimate.

When a cellular modem is extremely close to a GNSS receiver, it can interfere with the receiver’s reception. Some F10 module models (NEO-F10N, MAX-F10S, and MIA-F10Q) are equipped with a robust RF circuit that allows the GNSS and the cellular modem to operate without interference.

The u-blox F10 platform is pin-to-pin compatible with the previous u-blox M10 generation for easy migration. It also supports u-blox AssistNow, which offers real-time online A-GNSS service with global availability to reduce GNSS time-to-first-fix and power consumption.

The u-blox EVK-F101 evaluation kit will be available in April 2024.

The post u-blox launches new GNSS platform for enhanced positioning accuracy in urban environments appeared first on ELE Times.

A CDN or Content Delivery Server, is a geographically distributed network of interconnected servers. CDNs are a crucial part of the modern internet infrastructure which solves the problem of latency (delay before transfer of data begins from a web server) by speeding up the webpage loading time for data-heavy (like multimedia) web applications.

The usage of CDN has significantly increased with the rise of data volumes in web applications in the last few years. As per the Sandvine Global Internet Phenomena Report 2023, different popular CDN providers are included in the list of top 10 video applications for APAC region for their increased volume of application traffic.

Figure 1: Without CDN and with CDN scenario Network Traffic Analysis

The ATI team in Keysight has analyzed the network traffic of different popular CDN like Amazon CloudFront, Cloudflare, Akamai, Fastly and has seen some interesting information from the decrypted traffic which can be useful for other researchers.

Inside HTTP Request Header:

When a website decides to use CDN, then sometimes it typically integrates the CDN service name like CloudFront, Cloudflare, akamai etc. at the DNS level which changes the DNS records like CNAME records to point into the CDN’s domain. The same behavior is also seen inside the “Host” or “: authority” header inside the HTTP request. For example, if the original website is “www. popularOTT.com”, then after the CDN name integration the URL looks like www.popularOTT.cdnprovider.com as shown below –

Figure 2: Sample CDN request header Inside HTTP Response Header:

When a response is sent from the Content Delivery Server (CDN) server, it often includes some specific headers inside the HTTP response packet which provide some information about the CDN server as shown below –

• X-Cache: This header indicates whether a request is a hit, miss or bypass in the CDN cache. If its value is set as “HIT” (“HIT from cloudfront” for CloudFront) inside the HTTP response that means the request is served by the CDN server, not the origin server.

Figure 3: Sample response header from CDN server containing X-Cache header.

• X-Cache-Status: It is similar to “X-Cache” header which provides some detailed information about the caching process. Sometimes we also see the CDN provider information inside the header name. As example when a response is sent from Cloudflare CDN, then sometimes we see this “cf-cache-status” (here cf refers to Cloudflare) header inside the response packet.

Figure 4: Sample response header from CDN server containing X-Cache-Status header.

• Via: This repones header indicates if any intermediate proxy or CDN presents through which the request has passed. As example when a request has passed through Amazon CloudFront CDN, then sometimes we see information about that like “1 2b14bcf8de4af74db0f6562ceac643f8.cloudfront.net (CloudFront)” inside the “via” response header.

Figure 5: Sample response header from CDN server containing Via header.

• Server: In some cases, we can see the CDN server name in the “server” header inside the HTTP response packet as shown below –

Figure 6: Sample response header from CDN server containing Server header.

• Sometimes, we see other custom headers like “x-akamai-request-id”, “x-bdcdn-cache-status” etc. inside the HTTP response which indicates that the response is sent from a CDN server.

Figure 7: Sample response header from CDN server containing other CDN related headers.

CDN in Keysight ATI

At Keysight Technologies, our Application and Threat Intelligence (ATI) team, researchers have examined the traffic pattern of various leading CDN service providers based on their application traffic from the world’s top 50 most popular websites and they have published the network traffic pattern of 2 popular CDNs (Amazon CloudFront and Cloudflare) in ATI-2024-03 Strike Pack released on February 15, 2024. So please stay tuned for the other popular CDN application traffic which will be released in the upcoming ATI releases.

 

The post Looking into CDN Traffic in the Network appeared first on ELE Times.

We are at a global inflection point as we cope with the limitations of energy supply and the consequences of climate change. Regional conflicts are elevating risks in the traditional crude oil supply chain. Changes in rainfall patterns and disputes over water use priorities are limiting hydroelectric power generation. Moreover, extreme weather events have intensified the threat to lives and property. These challenges are compelling us to focus on energy efficiency requirements in almost everything we do. As a result, there is a significant trend towards designing more energy-efficient transportation and generation equipment.

Designing Energy-Efficient Machinery

Each industry has its goals to respond to these trends. The automotive industry is investing in electric vehicles and enhancing the aerodynamic efficiency of all their vehicles. The aerospace industry aims to reduce the cost and time required to design new aircraft models that are efficient and durable. In the same vein, the turbomachine industry benefits significantly from every efficiency and extension improvement of the product lifecycle.

Figure 1: OEM Design Goals Automotive Design

The automotive industry must comply with the new CAFÉ standards for 2028 and 2032. These standards will have an impact on their fleet, meaning they will need to build electric vehicles and improve the average fuel efficiency for their internal combustion engine models. A 10% reduction in the aerodynamic drag coefficient can lead to a 5% improvement in fuel economy. Simulation is a crucial tool to ensure that the design will perform well once manufactured and tested in the wind tunnel.

Figure 2: Automotive Design for Fuel Efficiency

To achieve this kind of leap forward, the industry must be able to do the following:

• Simulate turbulent air in fine detail
• Evaluate 100s of precise aerodynamic design changes
• Simulate entire car design for net impact

Aircraft Design

The commercial aircraft industry is highly regulated with a focus on safety and environmental impact. The process of designing a new aircraft involves several steps that must meet requirements for safe function, performance, and operation, and the aircraft must be certified for the entire flight envelope. Simulation is the only way to ensure the aircraft will perform as intended before building and flight-testing a prototype.

Figure 3: Aerospace Flight Envelope Performance

To simulate all operating conditions, designers must:

• Simulate lift in turbulent air in fine detail
• Simulate the entire aircraft design for net impact
• Evaluate all operating conditions (see chart)

Turbomachinery Design

Turbomachinery includes energy generators, large turbine aircraft engines, marine engines, and other machines with rotating motion. Improving energy efficiency can yield significant returns because of the scaled impact of the machine over its lifetime. Similarly, designing machines to last longer and require less maintenance can have a significant economic impact. Simulation is the best way to analyze various design changes to optimize the final design outcome.

Figure 4: Turbomachinery Design for Efficiency and Durability

To achieve this kind of leap forward, the industry must be able to:

• Evaluate multiple design optimization tradeoffs
• Simulate combustion dynamics in fine detail
• Simulate a full engine design for net impact

Announcing the Millennium Enterprise Multiphysics Platform

To address these needs, we are announcing the world’s first accelerated digital twin, delivering unprecedented performance and energy efficiency—the Cadence Millennium Enterprise Multiphysics Platform. Targeted at one of the biggest opportunities for greater performance and efficiency, the first-generation Cadence Millennium M1 CFD Supercomputer accelerates high-fidelity computational fluid dynamics (CFD) simulations. Available in the cloud or on-premises, this turnkey solution includes graphics processing units (GPUs) from leading providers, extremely fast interconnections, and an enhanced Cadence high-fidelity CFD software stack optimized for GPU acceleration and generative AI. By fusing Millennium M1 instances into a unified cluster, customers can achieve an unprecedented same-day turnaround time and near-linear scalability when simulating complex mechanical systems.

The Millennium Platform addresses the performance and efficiency needs of the automotive, aerospace and defense (A&D), energy, and turbomachinery industries with critical advances in multiphysics simulation technology. Performance, accuracy, capacity, and accelerated computing are all essential to enabling digital twin simulations that explore more design innovations, providing confidence that they will function as intended before undertaking prototype development and testing.

Highlights and benefits include:

• Performance: Combines best-in-class GPU-resident CFD solvers with dedicated GPU hardware to provide supercomputer-equivalent throughput per GPU of up to 1000 CPU cores
• Efficiency: Reduces turnaround time from weeks to hours with 20X better energy efficiency compared to its CPU equivalent
• Accuracy: Leverages Cadence Fidelity CFD solvers to provide unmatched accuracy to address complex simulation challenges
• High-Performance Computing: Built with extensible architecture and massively scalable Fidelity solvers to provide near-linear scalability on multiple GPU nodes
• AI Digital Twin: Rapid generation of high-quality multiphysics data enables generative AI to create fast and reliable digital twin visualizations of the optimal system design solution
• Turnkey Solution: The industry’s first solution that couples GPU compute with modern and scalable CFD solvers, providing an optimized environment for accelerated CFD and multidisciplinary design and optimization

Flexibility: Available with GPUs from leading vendors, in the cloud with a minimum 8-GPU configuration or on-premises with a minimum 32-GPU configuration—providing a flexible and scalable solution to fit each customer’s deployment needs

The post Digital Twins and AI Acceleration Are Transforming System Design appeared first on ELE Times.

Electronics design engineers bear the responsibility of overcoming the world’s concerns with electric vehicle (EV) power sources. Lithium-ion batteries are heavy, put pressure on natural resources, and sometimes are slow to charge. The logical next step in EV development is using ultracapacitors as a complementary power source for when there are not enough batteries to go around, allowing electrification to scale and tone down the detractors of modern charging electronics.

Looking to ultracapacitors may remove some of the market uncertainties surrounding other EV power generators. The electrostatic storage provides higher capacitance than the chemical method of conventional EV batteries. Additionally, the designs remove several rare metals from the composition, making it less challenging to acquire specific materials.

It may not have the density of chemical makeup, but its disruptively long-life cycle and lightning-fast fueling could make EV ownership more attractive. Whereas repeated charges in other batteries produce notable degradation, ultracapacitors can experience over 1 million charge and discharge cycles before noticeable damage.

Car manufacturers can install ultracapacitors alongside batteries for supplementary power. The energy boost is ideal for large-capacity fleet vehicles driving long ranges. Sometimes, they need more instantaneous power bursts climbing steep inclines than waiting for a chemical reaction. The two technologies working in conjunction reduce strain on both, extending their life cycles.

Ultracapacitor commercialization

Ultracapacitor designers started to see interest pique in the last several years. In 2020, an Estonian manufacturer received $161 million in new contracts for individual and public transportation needs. This signals electronics design engineers must create robust, accessible ultracapacitors for increasing demand and combating the climate crisis.

Lithium-ion batteries have an advantage over all other EV power sources because of their density, even if their heft and life span negatively affect their reputation. They are still the go-to device for auto manufacturers. Engineers must consider these design aspects for future ultracapacitor blueprints:

• Materials with higher surface area and greater capacitance
• Electrolytes with higher conductivity using additives
• Thermal management for improved temperature regulation and reduced runaway
• Seamless compatibility when integrated with other batteries
• Porous electrode designs for increased performance

Additionally, these specs inform engineers how to size the ultracapacitor for driving applications. Everything from maximum voltage potential to discharge duration affects this, which must be communicated to OEMs, so they can integrate it into manufacturing.

What’s next for design engineers

Electronics design engineers must collaborate with renewable energy experts to make the transition to market-friendly ultracapacitors a reality. Engineers must validate a design’s electromagnetic compatibility and signal integrity. These efforts only matter if power providers are consistent and reliable to support charging infrastructure.

Grid stability with high frequency and voltage is the foundation for success, so communicating ultracapacitor design needs to the renewable sector is critical. Similarly, while one of the selling points for ultracapacitors is their charging time, there are few options for fueling these vehicles. Stations must be equipped with local battery packs instead of directly connected to the grid to prevent overloads and shutdowns.

The final frontier electronics design engineers could explore is a vehicle capable of running solely on an ultracapacitor. Currently, using them with other batteries is the next step. Research and development should explore its potential as a sole generator, though it does not appear feasible in 2024’s developmental landscape.

Electrification needs lithium-ion to become commercially viable, and it is the most cost-effective option right now for consumers. However, the circuit designs and engineers’ prototypes for ultracapacitors show a bright future for the EV industry. This power source, alongside other battery options, will lead to more comprehensive compliance considerations, intersector collaboration, and cost optimization for the EV market.

Ellie Gabel is a freelance writer as well as an associate editor at Revolutionized.

Related Content

• Zooming on Hybrid Supercapacitors
• Fast-charging a supercapacitor from energy harvesters
• Do Electric Vehicle Batteries on the Grid Make Sense?
• Designing powerful electronic solutions with ultracapacitors
• Ultracapacitors: Best Option for EV Energy Storage Technology

The post Harnessing the promise of ultracapacitors for next-gen EVs appeared first on EDN.

Welcome to the intricate realm of PCB (Printed Circuit Board) design, where what begins as a simple circuit board evolves into a sophisticated masterpiece of electronic engineering. As the backbone of modern electronics, PCBs breathe life into our everyday devices, from smartphones to laptops. Crafting a reliable and functional PCB extends beyond merely connecting components. It demands a meticulous understanding of various aspects to achieve optimal performance and manufacturability. Central to this endeavor is constraint-based PCB design—a strategic methodology that meticulously governs the physical and electrical characteristics of a PCB. Such constraints not only safeguard against manufacturing pitfalls but also ensure electrical prowess, culminating in a product that doesn’t just meet the mark but sets new standards. In this post, we explore PCB constraints and how they play a crucial role in ensuring a successful design.

Grasping Constraint-Based PCB Design

Constraint-based design involves defining parameters that dictate how a PCB should be constructed. These constraints encompass multiple aspects, including electrical, physical, and manufacturing considerations. Considering constraints early in the design process is crucial, as it sets the groundwork for a successful design that aligns with the project requirements and end goals.

Constraint-based PCB design is akin to a maestro orchestrating a symphony. It balances numerous requirements to shape the overall design process, ensuring a harmonious outcome. These constraints can vary:

Electrical Constraints:

• Trace Width and Spacing:Defines the width and spacing of traces to ensure proper current carrying capacity and avoid short-circuits.
• Via Sizes and Types:Specifies dimensions and types of vias, based on design requirements and manufacturing capabilities.
• Impedance Control:Ensures traces are designed to have specific impedance values, crucial for high-speed designs.
• Clearance:Defines the minimum distance between different electrical entities (like traces, pads, vias) to avoid short circuits.
• High-speed Constraints:Rules related to the design of high-speed circuits, including length matching, differential pair routing, and phase control.

Physical Constraints:

• Board Dimensions:Specifies the size and shape of the PCB.
• Layer Stackup:Defines the number and arrangement of copper and insulating layers in the PCB.
• Component Placement:Provides guidelines for placing components on the board, ensuring they don’t interfere with each other and adhere to thermal and mechanical considerations.
• Thermal Constraints:Ensures areas generating high heat have sufficient thermal relief, including the use of heat sinks or thermal vias.

Manufacturability Constraints (Design for Manufacturability – DFM):

• Solder Mask Clearance:Ensures that solder masks are appropriately applied to avoid short circuits during the soldering process.
• Silkscreen Overlap:Ensures that component labels or other silkscreen elements do not overlap with pads or vias.
• Hole Sizes:Specifies the minimum and maximum sizes for drilled holes based on manufacturing capabilities.
• Annular Ring Size:Defines the minimum width of the copper ring around a drilled hole.
• Copper-to-Edge Clearance:Defines the minimum distance required between the edge of the PCB and any copper feature.

Assembly Constraints (Design for Assembly – DFA):

• Component Orientation:Ensures components are correctly oriented for automated assembly.
• Component-to-Component Clearance:Ensures sufficient space between components to allow for assembly and avoid interference.
• Polarity and Pin 1 Indicators:Guidelines for marking components to ensure they are placed correctly during assembly.

Reliability Constraints:

• Flex and Bend: Defines regions that can and cannot be bent in flex PCBs.
• Vibration and Shock: Constraints to ensure components can withstand specific vibration and shock levels, especially in rugged applications.
• Testing Constraints (Design for Test – DFT):
  • Test Point Requirements:Specifies the number and placement of test points for in-circuit testing.
  • Access for Probing:Ensures test equipment can access critical nodes during testing.
• Environmental and Regulatory Constraints:
  • RoHS/Lead-Free Design:Ensures PCBs are designed to adhere to environmental regulations, like the Restriction of Hazardous Substances (RoHS).
  • Electromagnetic Compatibility (EMC):Ensures designs adhere to electromagnetic interference (EMI) and susceptibility requirements.

Advantages of Constraint-Based PCB Design

A. Enhanced Signal Integrity and Reliability

In the world of electronics, signal integrity is paramount. Constraint-based design minimizes electromagnetic interference (EMI) and ensures proper trace routing for impedance control. By optimizing ground and power planes, noise is reduced, leading to improved signal reliability.

B. Improved Thermal Management

Efficient heat dissipation is a challenge in compact electronics. Constraint-based design tackles this by strategically placing components, utilizing thermal relief, and integrating sensors for real-time temperature monitoring. This ensures that devices maintain optimal operating temperatures.

C. Streamlined Manufacturing and Assembly

Designing for manufacturability (DFM) is a key concept. Constraint-based design includes component placement rules that facilitate automated assembly, reducing errors. By considering various soldering and assembly techniques, manufacturing becomes more seamless.

D. Faster Time-to-Market

Time is of the essence in the competitive electronics market. Constraint-based design reduces the need for countless design iterations by identifying flaws early through simulations. Collaborative design involving cross-functional teams also expedites the process.

E. Cost Savings

Design re-spins are expensive and time-consuming. Constraint-based design minimizes these by ensuring the initial design aligns with requirements. Efficient layouts optimize material usage and eliminate the need for costly post-production modifications.

F. Compliance and Standards

Electronic products must adhere to regulatory standards. Constraint-based design aids in designing with EMC, safety, and other industry standards in mind. This simplifies the certification process and ensures products meet legal requirements.

Implementing the Methodology

Design Rule Check (DRC) is a fundamental step in the PCB design process. It involves checking the design against a set of predefined rules to ensure the PCB will be functional, manufacturable, and reliable. Implementing DRC in your PCB design process helps catch errors before manufacturing, reducing costly re-spins, and potential functional issues.

Here’s a step-by-step guide on how to implement DRC in PCB design:

1. Understand Manufacturing Capabilities:
   • Begin by gathering the capabilities and constraints from your PCB manufacturer. This might include rules related to trace width and spacing, via sizes, hole sizes, annular ring sizes, and whatever you need to set your design up for success.
2. Set Up the Design Rules in Your PCB Design Software:
   • Most modern PCB design tools include a design rules setup or configuration section;
   • Enter the manufacturer’s constraints and any additional rules you need for your specific design. This might include electrical rules, high-speed rules, thermal rules, etc.
3. Layer-specific Rules:
   • Some rules are specific to certain layers. For example, the top and bottom layers might have different trace width and spacing rules compared to inner layers. Make sure to define these layer-specific rules.
4. Run the DRC:
   • Once your rules are set up, you can run the DRC. This will usually generate a list of violations or errors based on the rules you’ve set;
   • Some common violations might include trace width violations, clearance violations, unconnected nets, and overlapping components.
5. Review and Address Violations:
   • For each violation, the PCB design software typically provides a description and a visual indication of where the issue is on the board;
   • Go through each violation and correct the issue in the design. This might involve moving components, rerouting traces, or adjusting the design rules if they were set up incorrectly.
6. Iterative Process:
   • After correcting known violations, run the DRC again to ensure that no new issues have been introduced and all previous ones have been resolved;
   • This might need to be repeated several times until no violations are found.
7. Additional Checks:
   • Beyond standard DRC, consider running other checks like Electrical Rule Check (ERC) to catch logical and connectivity errors, or a Differential Pair Routing Check for high-speed designs.
8. Document Any Deliberate Violations:
   • In some cases, you might choose to violate a rule deliberately for a specific design requirement. In such cases, it’s essential to document this decision, explaining the rationale and ensuring the manufacturer is aware of it.
9. Collaborate with the Manufacturer:
   • Before finalizing the design, it can be beneficial to send the design files to the manufacturer for review. They might run their own DRC and provide feedback based on their specific manufacturing processes.
10. Stay Updated:
    • Manufacturing capabilities and standards can change over time. Periodically review and update your design rules to ensure they align with the latest capabilities and industry best practices.

Wrapping Up

The world of electronics is in perpetual flux, with innovations emerging at breakneck speeds. Amidst this, constraint-based PCB design emerges as a beacon, illuminating the path for designers. By meticulously defining, applying, and validating constraints, designers can craft PCBs that aren’t just functional but also efficient, cost-effective, and superior in quality. In an age where precision and speed are paramount, can you afford to design any other way?

David
Sr. Technical Marketing Engineer
Altium

The post The Critical Role of Constraint-Based PCB Design in Modern Electronics (PCB Design) appeared first on ELE Times.

The generative artificial intelligence (AI) revolution is here. With the growing demand for generative AI use cases across verticals with diverse requirements and computational demands, there is a clear need for a refreshed computing architecture custom-designed for AI. It starts with a neural processing unit (NPU) designed from the ground-up for generative AI, while leveraging a heterogeneous mix of processors, such as the central

Figure 1: Choosing the right processor, like choosing the right tool in a toolbox, depends on many factors and enhances generative AI experiences.

processing unit (CPU) and graphics processing unit (GPU). By using an appropriate processor in conjunction with an NPU, heterogeneous computing maximizes application performance, thermal efficiency and battery life to enable new and enhanced generative AI experiences.

Why is heterogenous computing important?

Because of the diverse requirements and computational demands of generative AI, different processors are needed. A heterogeneous computing architecture with processing diversity gives the opportunity to use each processor’s strengths, namely an AI-centric custom-designed NPU, along with the CPU and GPU, each excelling in different task domains. For example, the CPU for sequential control and immediacy, the GPU for streaming parallel data, and the NPU for core AI workloads with scalar, vector and tensor math.

Heterogeneous computing maximizes application performance, device thermal efficiency and battery life to maximize generative AI end-user experiences.

Figure 2: NPUs have evolved with the changing AI use cases and models for high performance at low power. What is an NPU?

The NPU is built from the ground-up for accelerating AI inference at low power, and its architecture has evolved along with the development of new AI algorithms, models and use cases. AI workloads primarily consist of calculating neural network layers comprised of scalar, vector,and tensor math followed by a non-linear activation function. A superior NPU design makes the right design choices to handle these AI workloads and is tightly aligned with the direction of the AI industry.

Figure 3: The Qualcomm AI Engine consists of the Qualcomm Hexagon NPU, Qualcomm Adreno GPU, Qualcomm Kryo or Qualcomm Oryon CPU, Qualcomm Sensing Hub, and memory subsystem. Our leading NPU and heterogeneous computing solution

Qualcomm is enabling intelligent computing everywhere. Our industry-leading Qualcomm Hexagon NPU is designed for sustained, high-performance AI inference at low power. What differentiates our NPU is our system approach, custom design and fast innovation. By custom-designing the NPU and controlling the instruction set architecture (ISA), we can quickly evolve and extend the design to address bottlenecks and optimize performance.

The Hexagon NPU is a key processor in our best-in-class heterogeneous computing architecture, the Qualcomm AI Engine, which also includes the Qualcomm Adreno GPU, Qualcomm Kryo or Qualcomm Oryon CPU, Qualcomm Sensing Hub, and memory subsystem. These processors are engineered to work together and run AI applications quickly and efficiently on device.

Our industry-leading performance in AI benchmarks and real generative AI applications exemplifies this. Read the whitepaper for a deeper dive on our NPU, our other heterogeneous processors, and our industry-leading AI performance on Snapdragon 8 Gen 3 and Snapdragon X Elite.

Figure 4: The Qualcomm AI Stack aims to help developers write once and run everywhere, achieving scale. Enabling developers to accelerate generative AI applications

We enable developers by focusing on ease of development and deployment across the billions of devices worldwide powered by Qualcomm and Snapdragon platforms. Using the Qualcomm AI Stack, developers can create, optimize and deploy their AI applications on our hardware, writing once and deploying across different products and segments using our chipset solutions.

The combination of technology leadership, custom silicon designs, full-stack AI optimization and ecosystem enablement sets Qualcomm Technologies apart to drive the development and adoption of on-device generative AI. Qualcomm Technologies is enabling on-device generative AI at scale.

DURGA MALLADI SVP & GM, Technology Planning & Edge Solutions, Qualcomm Technologies, Inc. PAT LAWLOR
Director, Technical Marketing,
Qualcomm Technologies, Inc.

The post What is an NPU? And why is it key to unlocking on-device generative AI? appeared first on ELE Times.

Courtesy: Intel

Applications powered by artificial intelligence are some of the most popular pieces of software being developed, especially on cloud computing platforms, which can provide easy access to specified hardware and accelerators at a low startup cost with the option to scale effortlessly. A popular cloud service provider, Google Cloud Platform* (GCP), contains a suite of cloud computing services that provide a variety of tools to develop, analyze, and manage data and applications. GCP also includes tools specific to AI and machine learning development, such as the AI Platform, the Video Intelligence API, and the Natural Language API. Using a platform like GCP for your AI projects can simplify your development while gaining access to powerful hardware that meets your specific needs.

Further enhancements to model efficiency can be accomplished with pre-built software optimizations tailored for diverse applications. By implementing these software optimizations, developers can see models deploy and infer faster and with fewer resources. However, the process of discovering and integrating these optimizations into workflows can be time-consuming and demanding. Accessing comprehensive guides and documentation packaged in an open-source environment empowers developers to overcome challenges by incorporating new optimizing architectures, facilitating the effortless enhancement of their models’ performance.

What are Intel Cloud Optimization Modules?

The Intel Cloud Optimization Modules consist of open-source codebases that feature codified Intel AI software optimizations designed specifically for AI developers working in production environments. These modules provide a set of cloud-native reference architectures to enhance the capabilities of AI-integrated cloud solutions. By incorporating these optimization solutions, developers can boost the efficiency of their workloads and ensure optimal performance on Intel CPU and GPU technologies.

These cloud optimization modules are available on several highly popular cloud platforms, including GCP. The modules utilize specifically built tools and end-to-end AI software and optimizations that enhance workloads on GCP and increase performance. These optimizations can increase machine learning models for a variety of use cases, such as Natural Language Processing (NLP), transfer learning, and computer vision.

Within each module’s content package is an open-source GitHub repository that includes all the relevant documentation: a whitepaper with more information on the module and what it relates to, a cheat sheet that highlights the most relevant code for each module, and a video series with hands-on walkthroughs on how to implement the architectures. There is also an option to attend office hours for specific implementation questions.

Intel Cloud Optimization Modules for GCP

Intel Cloud Optimization Modules are available for GCP, including optimizations for generative pre-trained transformer (GPT) models and Kubeflow pipelines. You can learn more about these optimization modules available for GCP below:

nanoGPT Distributed Training

Large Language Models (LLMs) are becoming popular in Generative AI (GenAI) applications, but it is often sufficient to use smaller LLMs in many use cases. Using a GPT model, such as nanoGPT (124M parameter), can result in better model performance, as smaller models are quicker to build and easier to deploy. This module teaches developers how to fine-tune a nanoGPT model on a cluster of Intel Xeon CPUs on GCP and demonstrates how to transform a standard single-node PyTorch training scenario into a high-performance distributed training scenario. This module also integrates software optimizations and frameworks like the Intel Extension for PyTorch* and oneAPI Collective Communications Library (oneCCL) to accelerate the fine-tuning process and boost model performance in an efficient multi-node training environment. This training results in an optimized LLM on a GCP cluster that can efficiently generate words or tokens suitable for your specific task and dataset.

XGBoost on Kubeflow Pipeline

Kubeflow is a popular open-source project that helps make deployments of machine learning workflows on Kubernetes simple and scalable. This module guides you through the setup of Kubeflow on GCP and provides optimized training and models to predict the probability of client loan default. By completing this module, you will learn how to enable Intel Optimization for XGBoost and Intel daal4py in a Kubeflow pipeline. You’ll also learn to set up and deploy a Kubeflow cluster using Intel Xeon CPUs on GCP with built-in AI acceleration through Intel AMX. Developers also have the option to bring and build their own Kubeflow pipelines and learn how these optimizations can help improve the pipeline workflow.

Elevate your AI initiatives on GCP with Intel Cloud Optimization Modules. These modules can help you leverage Intel software optimizations and containers for popular tools to develop accelerated AI models seamlessly with your preferred GCP services and enhance the capabilities of your projects. See how you can take AI to the next level through these modules, and sign up for office hours if you have any questions about your implementation!

We encourage you to check out Intel’s other AI Tools and Framework optimizations and learn about the unified, open, standards-based oneAPI programming model that forms the foundation of Intel’s AI Software Portfolio. Also, check out the Intel Developer Cloud to try out the latest AI hardware and optimized software to help develop and deploy your next innovative AI projects!

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Courtesy: Onsemi

The ongoing search for efficiency is impacting the design of electronic applications across multiple sectors, including both the automotive and renewables industries. Greater efficiency for an Electric Vehicle (EV) translates into increased range between battery charges and, in renewables, more efficient generation converts more natural energy from the sun or wind into usable electricity.

The quest for efficiency is driving designs in EVs and renewables.

Both applications use switching electronic devices extensively, and the drive for increased efficiency is driving demand for higher voltage devices. The link between higher voltage and higher efficiency is governed by Ohm’s Law, which states that power, or loss, generated in a circuit increases with the square of the current. The same law also tells us that doubling the voltage halves the current flowing in the circuit – reducing losses by a factor of four. Electricity companies demonstrate this principle, operating their grids at very high voltages – 275,000 or 400,000 volts in the UK – to reduce transmission losses.

While the electricity utilities rely on components such as heavy-duty transformers to handle high transmission voltages, it’s a bit more complicated in automotive and renewables applications, both of which make extensive use of electronic devices.

High Voltage Challenges for Semiconductors

Converters and inverters, based on switching power electronic devices, are key components in both alternative energy plants and EVs. Although both MOSFETs and IGBTs are used in these systems, the low gate-drive power, fast switching speeds and high efficiency at low voltages of the MOSFET have led to its dominance, and it is deployed in a wide range of power electronic applications.

Power MOSFETs have three main roles – blocking, switching, and conducting, figure 2, and the device must meet the requirements of each phase.

MOSFETs are required to block large voltages between their drain and source during switching.

During the blocking phase the MOSFET must withstand the full rated voltage of the application, while during the conduction and switching phases, losses and switching frequency are important. Conduction and switching losses both impact overall efficiency while higher switching frequencies enable smaller and lighter systems, a key attribute in both EVs and industrial applications.

The trend towards higher voltage is pushing the limits of the traditional silicon MOSFET. However, it is harder and costlier to get the low RDS(on) and high gate charge values required for reduced conduction losses and fast switching times. Power electronics designers are consequently turning to silicon carbide (SiC) to achieve higher efficiencies. SiC, a wide bandgap technology, has several advantages over silicon, including high thermal conductivity, a low thermal expansion coefficient, and high maximum current density, giving it excellent electrical conductivity compared to silicon. Additionally, SiC’s higher critical breakdown field means that a reduced thickness device can support a given voltage rating, leading to significant size reduction.

SiC MOSFETs are now available which can withstand voltage thresholds up to almost 10 kV, compared with 1500 V for the silicon variants. Also, the low switching losses and high operating frequencies of SiC devices enable them to achieve superior efficiencies, particularly in higher-power applications requiring high current, high temperatures, and high thermal conductivity.

onsemi Addresses the Need for Higher Voltages

In response to the growing demand for devices with high breakdown voltages, onsemi has built an end-to-end in-house SiC manufacturing capability including a range of products such as SiC diodes, SiC MOSFETs, and SiC modules.

This product family includes the NTBG028N170M1, a high-breakdown voltage SiC MOSFET, figure 3. This N-channel, planar device is optimized for fast switching applications at high voltages, with a VDSS of 1700 V, and an extended VGS of ‑15/+25 V.

onsemi’s NTBG028N170M1

The NTBG028N170M1 supports drain currents (ID) up to 71 A continuously and 195 A when pulsed and its superior RDS(ON) – typical value 28 mW – mitigates conduction losses. The ultra-low gate charge (QG(tot)), at just 222 nC, ensures low losses during high-frequency operation and the device is housed in a surface mountable D2PAK–7L package, which reduces parasitic effects during operation.

The onsemi EliteSiC range also includes a range of 1700 V-rated SiC Schottky diodes, which complement MOSFETs in power electronics systems such as rectifiers. The high Maximum Repetitive Peak Reverse Voltage (VRRM) of these diodes, along with their low Peak Forward voltage, (VFM) and excellent reverse leakage currents, equip design engineers to achieve stable, high voltage operation at elevated temperatures.

EliteSiC Supports Efficient Power Electronics Designs

The quest for efficiency is relentless in applications which depend on power electronics devices. The trend towards higher system voltages is challenging the traditional Si-MOSFET and SiC devices offer a way forward, enhancing efficiencies while reducing form factors. The 1700 V NTBG028N170M1 from onsemi enables higher voltage designs for key power electronics systems.

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Author: Dr Abhilasha Gaur, Chief Operating Officer, Electronics Sector Skills Council of India (ESSCI)

As the last pages of the Class 12 exam papers are turned, a new chapter eagerly awaits the young minds of India. Amidst the excitement and anticipation of what lies ahead, many students find themselves pondering the age-old question: “What next?” For those with a passion for fashion, creativity, and innovation, the ESDM sector beckons as a realm of boundless opportunities. In this article, we embark on a journey through the colourful landscape of India’s ESDM industry, exploring the diverse career avenues that await aspiring professionals post-Class 12 exams.

Dr Abhilasha Gaur, Chief Operating Officer, ESSCI

Exploring the Landscape:

The Electronics System Design and Manufacturing (ESDM) sector in India is experiencing phenomenal growth. Supported by government initiatives like “Make in India,” it’s rapidly becoming a major hub for electronics manufacturing and innovation. As per Invest India report, it is projected that India will achieve the milestone of becoming a $1 trillion digital economy by the fiscal year 2026. Presently, the electronics market within India holds a value of $155 billion, with domestic production contributing to 65% of this figure.

If you’ve completed your 12th standard and have a passion for technology,  a career in the ESDM sector holds immense potential. ESDM encompasses the entire spectrum of electronics activities, including:

• Design: Designing integrated circuits (ICs), printed circuit boards (PCBs), electronic systems, and embedded software.
• Manufacturing: Production and assembly of electronic components, devices, and end-products. This includes semiconductor fabrication.
• Testing and Validation: Ensuring product quality, reliability, and compliance with industry standards.
• Repair and Maintenance: Servicing, troubleshooting, and repairing electronic products and systems.

Why is ESDM a Lucrative Career Path?

• Government Initiatives: The Government of India is heavily invested in developing the ESDM sector. Several policies and schemes aim to boost domestic manufacturing, attract foreign investment, and create a skilled workforce.
• Rapid Growth: India’s ESDM market is experiencing substantial growth, projected to reach trillions of rupees in value over the next few years. This growth fuels the demand for skilled professionals.
• Skill Development Focus: Programs focusing on skilling and training the ESDM workforce are a priority, ensuring you have ample opportunities to acquire the required skills.
• Diverse Ecosystem: India’s ESDM sector is diverse, offering opportunities in consumer electronics, telecommunications, defence, healthcare, automotive, and many other industries.
• Global Requirements: In the global market, the requirements of the ESDM industry are multifaceted and continually evolving. First and foremost, there is a persistent need for innovation and technological advancement to stay competitive. Companies are investing in research and development to create cutting-edge products that meet the ever-changing demands of consumers worldwide.

Next Level Options in ESDM for 12th Pass Students

Here’s how you can embark on a rewarding ESDM career after completing your 12th standard:

1. Diploma Programs

• The ESDM sector offers exciting career opportunities for 12th graders through diploma programs. Options like Electronics and Communication Engineering (ECE) provide a strong foundation in electronics principles, communication systems, and embedded systems, opening doors to technician, engineer, and quality control roles. Electronics & Communication Engineering (ECE) focuses on telecom infrastructure and equipment, preparing individuals for technician and maintenance positions in this growing field. Consider your interests and career goals when choosing a diploma program to launch your journey in the dynamic ESDM sector.

2. Skill Development and Certification Courses

• The booming ESDM sector demands skilled professionals. Skill development and certification courses offer a fast-track entry point, equipping 12th-pass students with industry-relevant skills. Government initiatives and industry collaborations provide various affordable options, empowering individuals to join the electronics revolution and contribute to India’s technological advancement. You can learn a lot of the basics and advanced skills with ESSCI – Electronics Sector Skills Council of India, a non-profit organisation, which works under the aegis of MSDE – Ministry of Skill Development and Entrepreneurship.

3. Bachelor’s degree Options

If you desire advanced positions and specialization, consider bachelor’s degree courses. Some popular undergraduate courses are – B.Tech /B.E. in Electronics and Communication Engineering, Electrical and Electronics Engineering, Instrumentation and Control Engineering, Computer Science and Engineering, Mechatronics, Automation and Robotics. These engineering programs provide extensive training in electronics hardware design, testing, manufacturing processes, software skills, and embedded systems. Reputed institutes like IITs, NITs, IIITs and private colleges offer ESDM-focused bachelor’s degree courses for students interested in building careers in the electronics industry. The programs aim to develop competent engineering graduates equipped for upcoming technology shifts like IoT, AI and Industry 4.0.

Target Industries Within the ESDM Ecosystem

• Consumer Electronics Manufacturing: Contribute to the production of smartphones, laptops, televisions, home appliances, and other consumer goods.
• Semiconductors: Play a part in the design and fabrication of the integrated circuits that power these electronics.
• Telecom Infrastructure: Work on the networks and equipment that form the backbone of communication.
• Medical Devices and Healthcare: Develop life-saving medical electronics, diagnostic equipment, and healthcare technology.
• Defence and Aerospace: Be involved with electronics for military and space applications.
• Mechatronics: Design control systems, sensors, and smart features for vehicles.

Essential Skills for the ESDM Sector

• Technical Knowledge: Strong foundation in electronics fundamentals.
• Problem Solving: Analytical thinking and troubleshooting ability.
• Attention to Detail: Precision is critical when working with electronics.
• Adaptability: Keeping up with advancements in technology.

 

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