Новини світу мікро- та наноелектроніки

Digital electronics has profoundly changed musical instrument design. From toy keyboards to performance-grade pianos, synthesizers, and drum sets, to name a few, instruments that once would have been finely crafted wood and metal can today find their voices in CPUs, memory, and data converters.

This does not mean craftsmanship is dead. There is as much skill, experience, and love of music in the intellectual property (IP) inside today’s electronic instruments as in the workshop of a traditional piano maker or luthier. It is just expressed differently. A look inside an instrument will illustrate this point.

A generic architecture

A concert grand piano, an early analog synthesizer, a drum set, and a clarinet could hardly look less alike. Yet, functionally, the digital electronic versions of all these instruments can share a single block diagram and signal flow. Figure 1 displays the block diagram of an ASIC inside electronic musical instruments.

Figure 1 The ASIC for electronic musical instruments is shown with its key building blocks. Source: Faraday Technology Corp.

One or more input devices capture the musician’s intent. This could be just a row of membrane switches for a toy keyboard. A professional piano might have a position sensor on each key and pedal. An electronic version of a clarinet might mean a pressure or velocity transducer and position sensors on the keys. A synthesizer might have a microphone for voice input.

The choice of sensors must both meet cost guidelines and capture what is essential about the musician’s actions at that price point. This must include subtilities, such as a pianist’s attack and graduated use of pedal or a saxophonist’s voicing and modulated use of the keys.

The analog sensor signals will pass through signal-conditioning circuitry and into analog-to-digital conversion. The resulting digital signal streams—which, at this point, represent the musician’s actions, not sounds—will go into a digital subsystem. This subsystem will generally comprise a CPU, usually a digital signal processor, memory, I/O interfaces, and a great deal of software and stored data.

This block not only interprets the incoming sensor data and controls the rest of the instrument but also combines sensor input with sampled or algorithmically generated audio waveforms and shapes these waveforms to produce a digital audio output stream. It is here that the craftsmanship happens.

The digital audio signal may be sent to external devices via an interface such as USB or passed on to digital-to-analog conversion and then to an audio amplifier.

A range of solutions

This description fits various instrument types, levels of sophistication and performance, and price points (Figure 2). In principle, the only differences between digital instruments are the input devices and the software. But the reality is more complex than that.

Figure 2 The above chart highlights three keyboard market segments. Source: Faraday Technology Corp.

Both engineering expertise and musical knowledge are used in the design decisions that produce different types of instruments. What kinds of sensors, and where? What type of analog-to-digital converter (ADC) should be employed, how many channels should be used, and what is the sample rate? What will be the tasks for the CPU and DSP, and consequently, how powerful must each be?

What are the necessary resolution, sample rate, noise level, and distortion of the digital-to-analog converter (DAC)? These choices, along with the software design and the vendor’s extensive library of sound samples, will set the instrument’s personality, whether the child’s toy or concert paragon.

Design implementation

The obvious way to implement the electronic portion of these musical instruments is with a discrete data converter, microcontroller, DSP, and memory chips. This approach allows for a fast time to market and will enable designers to select just the right chip for the intended performance level. It also allows the design team to focus most of their effort on the software from which the instrument’s character will emerge.

However, at least three issues exist with using discrete, off-the-shelf ICs for anything less than a premium professional instrument. First, suppose the organization intends to market a range of instruments at different price points. In that case, the discrete approach will lead to a proliferation of bills of materials (BOM) and board designs, complicating supply-chain management. Worse, it will require several software versions, each of which must be maintained and kept coherent.

Second, using discrete chips will make protecting proprietary software IP from theft difficult. All the pins on the chips are exposed to probing, allowing competitors to watch the operation of the digital electronics and even use diagnostic tools to examine memory through code. Further, the choice of ICs in the design will be visible, if not on the package lids, then on inspection of the dies inside.

Third, sophisticated designs may rely on proprietary hardware—especially in the data converters and the DSP core—to achieve the price/performance point intended at the high end of the product family. Duplicating these special hardware features in off-the-shelf chips may not be possible without carrying out massive overdesign.

Taking the ASIC path

These considerations have led some musical instrument design teams to employ a mixed-signal ASIC (Figure 3). An audio ASIC answers each of the three problems of a discrete design while serving as the foundation of digital electronic instrument designs.

Figure 3 The musical instruments ASIC is segmented into 186 MHz (left) and 192 MHz (right) domains. Source: Faraday Technology Corp.

First, the unit cost of an ASIC for these applications will be low enough that the same chip can be used across a broad product line, often without changing the board design. That cost may be lower than the total cost of discrete chips, especially once inventory, assembly, and test costs are included. A modular approach to software design and test design can allow one version of the software and one test bench to serve all the products in the family. This hugely simplifies debug and life-cycle management.

Second, the ASIC’s data paths and circuits are inside the die, safe from all but the most determined examination. The exception would be external code and audio sample memory. However, these can be encrypted, with the ASIC providing hardware-based encryption and decryption, so the software and data crown jewels are never exposed to the outside world in unencrypted form.

Third, suppose the developers have proprietary circuit designs for audio signal paths, a unique DSP architecture, or even a favorite CPU core. In that case, these can be implemented in the ASIC without concern for whether they are available off the shelf for the entire life of the product family.

However, there is an obvious objection to choosing an ASIC: musical instrument designers rarely have entire internal ASIC design teams. They are unlikely to want to assemble such a team for one project. Nor do they have a network of relationships with silicon IP providers, chip foundries, and outsourced assembly and test houses. These relationships turn a chip design into a reliable stream of finished chips. This is where a flexible, full-range ASIC partner comes in.

An ASIC case study

To show the importance of a partner, let’s look at a representative, composite example of an ASIC engagement. Faraday began discussions with a globally known musical instrument manufacturer. In addition to documenting the desired gross architecture, performance, and features, the initial conversation covered many of the points we have just discussed.

This organization was quite sophisticated in digital audio design, with its own DSP algorithms, logic designs for some critical digital functions, and precise specifications for mixed-signal functions. On the other hand, Faraday drew upon its internal IP libraries and extensive network of third-party IP vendors to gather the non-proprietary blocks, including an ARM CPU subsystem, memory and communications interfaces.

Next, Faraday determined that the design could meet the music company’s demanding digital/analog converter requirements with available IP, eliminating the need for an external DAC. Further, Faraday worked with the instrument designers to produce an optimized netlist for a DSP core optimized to the music company’s algorithms.

Faraday then took the chip design through the customary ASIC design flow of IP integration, functional verification, synthesis, and mixed-signal integration. At that point, it stepped in to complete the back-end design, conferring with the instrument design team when necessary, and taped out to the foundry the two partners had jointly selected.

About 18 months after the initial engagement, the musical instrument company received working silicon from the assembly and test vendor Faraday had arranged. A flexible engagement such as this can make an ASIC design the realistic best choice for a musical instrument or another such electronic product.

Kevin Kai-Wen Liu is a project manager at Faraday Technology Corp.’s headquarters in Hsinchu, Taiwan.

 

 

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The post Electronic musical instruments design: what’s inside counts appeared first on EDN.

BluGlass Ltd of Silverwater, Australia — which develops and manufactures gallium nitride (GaN) blue laser diodes based on its proprietary low-temperature, low-hydrogen remote-plasma chemical vapor deposition (RPCVD) technology — has signed an agreement with Macquarie University (project lead) and defence company Aurizn to develop and test a new laser-based method to measure subsurface water temperature and depth. BluGlass will provide visible GaN lasers, partially funded by an Australia's Economic Accelerator (AEA) seed grant to support the commercialization of visible lasers in maritime applications...

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It happened in 2014. A year later, it happened again. And after a nine-year blessed respite, a month back it happened a third time. What am I talking about? Close-proximity lightning (each time unknown whether it just cloud-to-cloud arced overhead or actually hit the ground) that once again clobbered some of my residence’s electronics. Thursday night, August 8, we scored a direct hit from a west-to-east traversing heavy rain, hail and wind squall. When the house shook from a thunderclap seemingly directly overhead, I had a bad feeling. And the subsequent immediate cessation of both LAN and WAN connectivity sadly confirmed my suspicions.

As background for those unfamiliar with my past coverage, I’m the third owner of this house, located in the Rocky Mountain foothills just southwest of Golden, CO. The previous owner had, when retrofitting the residence to route coax and Ethernet to various locations in both the ground floor and upper level, gone the easy-and-inexpensive route of attaching the cabling to the house’s exterior, punching through rooms’ walls wherever interior connectivity was desired. Unfortunately, that cabling has also proved to act as an effective electromagnetic pulse (EMP) reception antenna whenever sufficient-intensity (strength and/or proximity) lightning is present.

This time, a few things—one of our TVs that initially no longer “saw” any of its active HDMI inputs and the exercise treadmill whose motor stalled—were temporarily stunned until after I power-cycled them, after which time they thankfully returned to normal operation. Alas, other gear’s demise was more definitive. Once again, several multi-port Ethernet switches (non-coincidentally on the ends of those exterior-attached network cable spans) got fried, along with a CableCard receiver and a MoCA transceiver (both associated with exterior-routing coax). My three-bay QNAP NAS also expired, presumably the result of its connection to one of the dead multi-port Ethernet switches. All this stuff will be (morbidly) showcased in teardowns to come.

Today, however, I’ll focus on the costliest victim, the control subsystem for the hot tub on the back deck. In the earlier 2014 and 2015 lightning incidents, we’d still been using the home’s original spa, which dated from the 1980s and was initially located inside the residence. The previously mentioned second owner subsequently moved it outside (the original “hot tub room” is now my office). The geriatric hot tub ran great but eventually leaked so badly that in 2019 we went ahead and replaced it. In retrospect, I remember having a conversation with the technician at the time about how its discrete transistor-and-relay dominant electronics would have likely enabled it to run forever, but for physical integrity compromise that led to its eventual demise.

After the storm calmed, on a hunch I went outside and lifted the hot tub cover. The control panel installed on the hot tub rim interestingly was still illuminated. But the panel itself was dead; the display was blank, and the control buttons were all inoperable. Curiously, the hot tub pump (and presumably other subsystems) also seemed to still run fine; I could hear the motor kick on as normal in response to each power activation cycle, for example. But not being able to adjust the temperature and pump speed, not to mention alter the filter cycle settings (and the clock settings they’re based on) was an obvious non-starter.

Unfortunately, the manufacturer’s three-year warranty had expired two years earlier. More generally, production on this particular control panel had ironically ended roughly coincident with when I bought the hot tub back in 2019, and my technician was no longer able to source a replacement. This meant that, although there was a chance that only the comparatively inexpensive control panel had gone bad, I was going to have to replace the entire “pod” kit that included (among other things) a newer model control panel. Here’s what the old “pod” looked like after my technician pulled it out and before he hauled it away for potential spare-parts scavenging purposes; according to him, the blue cylindrical structure on top is the water heater:

And here are some closeups. The large square IC at the center of the last one, for example, is likely the digital control processor. Unfortunately, its markings have either been intentionally obscured or were otherwise too faint for me to be able to discern:

I unfortunately don’t have any comparative pictures of the original hot tub’s electronics, but trust me, they were way more “analog”. Feel free to chime in with your thoughts in the comments as to the comparative reliability of “oldie but goodie” vs “shiny new” circuitry…

Now for the removed old control panel:

And its installed and operational successor:

So, what happened here? As setup for my theorizing, here are a few more old-panel photos:

Originally, there were actually two cables connected to the panel. One, not shown here, was a simple two-wire harness that, I hypothesize, ran power from the “pod” circuit board to the panel’s LEDs for illumination purposes. As I mentioned earlier, it seemingly survived the storm just fine. The one shown here, on the other hand, is a multi-wire cluster that terminates at and connects to the circuit board via the connector shown in the second-photo closeup.

This particular cable was, I believe, the Achilles heel. Its signals are presumably low-voltage, low-current digital in nature. Remember my earlier mention of Ethernet cables (for example) acting as EMP reception antennae, with disastrous equipment consequences? I’m guessing the same thing happened here, via this foot-or-so long multi-wire harness. Did the EMP only fry the control panel’s electronics, versus also damaging the “pod” board circuitry? Perhaps. By analogy, in some cases over these three (to date…another heavy-thunder storm is ironically brewing as I type these words) lightning-damage episodes, the Ethernet switches on both ends of a particular outdoor cable run have died, while in other cases, only one switch has expired. Regardless, given the replacement parts-(non)availability circumstances, it’s a moot point.

I’ve got more to tell, including the already-mentioned teardowns, plus (for example):

• How I resurrected my network storage, in the process bolstering my file backup scheme
• Options (some of which I’ve tried, with varying degrees of success, and documented) for dispensing with the outdoors-routed Ethernet and coax cables, and
• Residence-wide surge protection schemes

For now, however, I’ll wrap up this post’s topic focus with an as-usual invitation for readers’ thoughts in the comments!

—Brian Dipert is the Editor-in-Chief of the Edge AI and Vision Alliance, and a Senior Analyst at BDTI and Editor-in-Chief of InsideDSP, the company’s online newsletter.

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• Teardown: Ethernet and EMP take out TV tuner
• Teardown: MoCA adapter succumbs to lightning strike

The post Lightning strikes…thrice???!!! appeared first on EDN.

It’s Day Two of our weeklong virtual conference, and it begins with a keynote discussion with the fascinating Dr. Alex Lidow from EPC and continues with live sessions from many other industry-leading companies.

With efficiency and energy sustainability being key drivers of LED selection for industrial and outdoor lighting applications, LED product and lighting maker Lumileds LLC of San Jose, CA, USA says that its new LUXEON 5050 HE Plus can deliver luminous efficacy of 199lm/W and luminous flux of 746lm, as well as reducing application power consumption by 18% or more in critical infrastructure applications common to cities and businesses around the world. Further, the lower energy consumption of the LUXEON 5050 HE Plus supports the transition to low-carbon or no-carbon electricity supply. OEMs can achieve greater sustainability in their manufacturing process by reducing the physical material in both the heatsink and the system’s driver...

Factory floors look much different than they did in the past. Today, robots assemble products, think on their feet to navigate complex environments, take on new tasks, and make real-time decisions. And they do plenty of this without human supervision.

Early industrial robots advanced manufacturing by taking over redundant and dangerous tasks but were still confined to straightforward and pre-programmed actions. Things have changed. Autonomous mobile robots (AMRs) are equipped with cutting-edge microelectronics, high-performance batteries, and advanced wireless connectivity.

While these robots are not self-aware, they still visualize and interpret the environment around them. Gathering information from various sensors, they respond to changing conditions and adapt their actions to accomplish assigned tasks. Navigating their way through a busy factory environment, these AMRs act autonomously by employing a form of artificial intelligence called machine learning.

Autonomous robots are playing a vital role in the lights-out factory. Also known as the dark factory, these facilities require very little human activity., Lights-out manufacturing is becoming more possible since AMRs are equipped with advanced sensors that enable them to operate in the dark. AMRs also play a crucial role in production, delivering raw materials around the factory. Their ability to act independently allows them to calculate the safest route through the dynamic environment. Any change in the production schedule is communicated to the fleet of AMRs, ensuring that the correct parts are in the right place at the right time.

To effectively navigate industrial settings, AMRs rely on sensors, vision systems, and machine learning to understand their environment. Like many industrial machines, these robots need to process vast volumes of data while working in harsh conditions. To help with this, radio frequency (RF) connectors provide communication from the sensor to the processor, delivering high data rates while withstanding the vibration and shock of the industrial environment.

Radio Frequencies for Robots

An essential component of the AMR communication process involves RF signals. Every device that transmits or receives data wirelessly uses RF signals to carry information. RF signals are carried around the equipment using coaxial cables and connectors constructed with a single central conductor surrounded by an outer conductive shield. The inner and outer conductors are separated by an insulator called a dielectric, whose dimensions are critical to allow for efficient transmission of an RF signal.

While 5G wireless communication uses relatively low frequencies, up to 6GHz, many applications require higher performance. Modern precision RF connectors can transmit signals with frequencies greater than 80GHz. These higher frequencies allow AMRs to wirelessly send enormous amounts of information, forming part of a dynamic network in which information is shared with other nearby equipment. This data network forms the backbone of the smart factory.

RF connectors that allow such high frequencies are manufactured to exact requirements. The bodies and contacts of the connector are machined to ensure consistent dimensions, and the plastic materials used for the dielectric are chosen for their stability. The result is a connector that delivers a consistent impedance profile and low losses, even at the highest frequencies.

Still, the physics of higher frequencies means that connectors have become smaller. For instance, the ever-popular SMA connector, which has provided many years of service in industrial applications, is limited at higher frequencies. Newer designs, such as the 2.92mm coaxial connector, can deliver up to 40GHz, while the SMPM is capable of even higher frequencies up to 65GHz.

From Automotive to Automation

Designers of the latest AMRs can benefit from technology developed for the automotive industry. The introduction of electrification, advanced driver assistance systems (ADAS), and self-driving vehicles has seen a growing demand for robust RF connector systems that can withstand the harsh conditions vehicles face. This reliability is critical for AMRs that travel beyond the factory walls. Optimizing AMRs will require high-performance RF connectors to provide communications with the latest 5G network when they are away from the factory network. These autonomous robots will also need small and robust antenna connectors for use with global positioning and global navigation satellite systems (GPS and GNSS).

The key to all these communication systems will be RF connectors designed for the industrial world’s tough conditions. However, the smaller connectors that are capable of the higher frequencies required for effective communication can be vulnerable in these demanding conditions. Precision manufacturing and robust design will be vital, as will design features that reduce the stress on cables, such as edge-launching and angled PCB mounting connectors.

Conclusion

A wide range of industries have employed the latest AMRs. Their ability to work without supervision makes them ideal for use in hazardous situations where they perform tasks that are too dangerous for a human worker. While their primary use is currently in industrial settings, the use cases for AMRs could be as diverse as scientific research or disaster relief, and even in the vacuum of space or on the battlefield.

Industrial AMRs will free human workers from the need to supervise repetitive tasks. These devices must share information, navigate, and communicate through various environments, from the home to the factory and beyond. RF technology provides AMRs with the wireless links they need to accomplish these tasks. To deliver communication signals, designers will require the latest RF connectors that offer high performance in some of the most demanding conditions in the world.

David Pike

The post RF Connectors for Autonomous Mobile Robots appeared first on ELE Times.

The new MCU features a unique multicore architecture to optimize performance and power efficiency.

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A trans-inductor voltage regulator (TLVR) modifies the conventional multiphase buck converter, accelerating the converter’s output current slew-rate speed capabilities to approach the fast load slew rate of the high-speed processor or application-specific integrated circuit’s core voltage rail. The output inductors each get a secondary winding, which are connected in series to create a secondary loop to accelerate the response to load changes. This improvement in load transient performance is at the cost of increased steady-state ripple and its resulting power loss, however. The problem is that it is very hard to estimate the actual overall inductance in the secondary loop, which is a primary driver of performance, as layout and printed circuit board (PCB) construction can significantly affect it. In this power tip, I will show a simple measurement that you can use to estimate actual leakage inductance in the TLVR secondary loop and optimize performance.

Figure 1 is a simplified schematic of the multiphase buck converter without and with the TLVR circuit.

Figure 1 Simplified multiphase buck converter and TLVR schematics. Source: Texas Instruments

Note the added secondary loop in the TLVR connecting all of the secondaries of the output inductors with the compensating inductor value, Lc, and parasitic elements shown. The sum of all of these inductances is the total secondary-loop inductance, or Ltsl. Ltsl determines TLVR performance, as both the added output current slew rate and high-frequency ripple current from the TLVR loop are inversely proportional to it. Because of the unpredictability of the parasitic inductances, when the TLVR was first introduced, it included a fixed Lc in the secondary loop.

The existing approach sets Lc to “swamp out” the parasitic inductances, assuming that they are much less than Lc. But there is a scope measurement across Lc that either will verify this assumption, or if not, provide the information you need to estimate the Ltsl. You can then adjust Lc to better match the target overall leakage for best slew-rate capability and ripple current performance, and in some cases omit it.

The TLVR performance equation is the output current slew-down capability ΔI/Δt in amperes per microseconds (A/µs), with some recent applications asking for as much as 5,000 A/µs. Slew-up capability is just as important, but with VIN (12 V typically) generally much greater than VOUT (0.7 V to 1.8 V typically), the slew-up rate capability will generally be much greater, and potentially excessive. Limiting how many phases you can turn on at the same time will usually reduce excessive slew-up capability.

The equations in Table 1 show that the load slew-rate acceleration is inversely proportional to Ltsl. Table 2 shows that the high-frequency TLVR currents are also inversely proportional to Ltsl.

Buck slew down ΔI/Δt		L is the value of the discrete output inductor at each stage
TLVR slew down ΔI/Δt		Lm is the value of the magnetizing inductance at each stage
Ltsl	(Assuming that Ltsl = Lc [1])	LLeakage is defined as the leakage inductance of each output inductor

Table 1 Buck and TLVR slew-down ΔI/Δt equations. Source: Texas Instruments

Time period where all phases are off (TOFF)		Fsw is the switching frequency of each phase
High frequency p-p current ripple (ΔILtsl)		In the secondary loop and in each power stage
Root-mean-square (RMS) value of this current

Table 2 TLVR high-frequency currents in the secondary winding and all phases when VOUT ´ Nphases < VIN. Source: Texas Instruments

Below in Table 3 are the expected voltages across Lc when VOUT x Nphases < VIN assuming Ltsl ≈ Lc, and recalculation of Ltsl when smaller voltages are seen.

Voltage across Ltsl (and Lc if Ltsl ≈ Lc) when one phase is on		Assuming the polarity of Lc as shown in Figure 1
Voltage across Ltsl (and Lc if Ltsl ≈ Lc) when all phases are off		Assuming polarity of Lc as shown in Figure 1
RMS of the waveform
Estimating Ltsl when the actual waveform is smaller than the expected waveform		Use calculated VLtslrms and measured VLcrms

Table 3 Expected voltage waveform across Lc when VOUT x Nphases < VIN assuming Ltsl ≈ Lc, and recalculation of Ltsl when smaller voltages are seen. Source: Texas Instruments  

Now it’s time to introduce a design example, starting with the requirements and overall approach, as shown in Table 4. 

VIN	12 V	TLVR loops	2 loops interleaved
VOUT	1.0 V	Each loop	>2,500 A/µs
Maximum IOUT	1,000 A	Stages Ntotal	16
Power stages	32	Phases Nphases	8
Phases	16	Lm	120 nH
Stages/phase	2	Target Ltsl	100 nH
Fsw each phase	570 kHz	Ripple frequency	4.56 MHz
Maximum load step	500 A	Ripple p-p/RMS	11.7 A/3.4 A
Load slew rate	5,000 A/µs	VLtsl on/off	–8 V/+16 V
		VLtslrms	11.3 VRMS

Table 4 Design requirements and overall approach. Source: Texas Instruments

 This 32-stage design uses two TLVR loops each at the near-5-MHz sawtooth frequency, but 180 degrees out of phase in order to achieve good but imperfect cancellation of the sawtooth waveforms in the output capacitors. Without TLVR, even with 32 phases and inductors at only 70 nH, the fastest slew-down rate would be 460 A/µs. Based on the equations in Table 2, the slew-down capability would be -5,387 A/µs. Getting this >5,000 A/µs slew-rate capability requires accepting a high-frequency ripple current in each phase of 3.4 ARMS.

I tested a board built up with the assumption that Ltsl ≈ Lc and used 100 nH the target Ltsl for Lc. Figure 2 shows the layout of one of the two TLVR loops.

Figure 2 The layout of a 16-power-stage TLVR loop. Source: Texas Instruments

But is the 100-nH Lc really the true Ltsl of this 16-stage loop? See the large secondary loop between “start” and “end” in Figure 2. Measuring the actual voltage waveform across Lc (L36 here) when all 16 stages and eight phases are active sheds light on this assumption. If Ltsl ≈ Lc and using the formulas from Table 3, you should expect a square wave going between +8 V and -16 V at eight times the per-phase switching frequency. The RMS value of this waveform should be 11.3 V.

Figure 3 shows what I actually measured.

Figure 3 Measured voltage waveform across an eight-phase/16-stage compensating inductor with expected TLVR waveform if Ltsl ≈ Lc, shown in black. Source: Texas Instruments

Both the actual L36 waveform (pink) versus the expected total leakage waveform (black) and the RMS value (5.02 V versus 11.3 V) point to Lc being one-half the Ltsl and point to that fact that there is another 100 nanohenries from inductor leakages and PCB traces in the secondary loop. Comparing the actual versus expected RMS values instead of peak values will reduce the confusion introduced by the parasitic ringing evident on the measured waveform.

With the total inductance in the secondary loop at 200 nH, the output current slew-down capability is reduced to -2,827 A/µs for the 32-stage design. For the 5,000 A/µs load slew-rate application, shorting out the actual Lc reduced the total secondary inductance back to 100 nH. For applications with a maximum load slew rate less than 3,000 A/µs, leaving the compensating inductors in place will reduce circulating high-frequency currents by half and reduce losses from these currents by 75%.

Obtaining leakage inductance

Knowing the actual leakage inductance in your TLVR loop will put you in the best position to get your output current slew rate while minimizing added losses caused by the TLVR loop. Discovering that one simple measurement will give you the necessary information is one example of what my colleagues and I pursue at Texas Instruments in the interests of power-management optimization.

Josh Mandelcorn has been at Texas Instrument’s Power Design Services team for almost two decades focused on designing power solutions for automotive and communications / enterprise applications. He has designed high-current multiphase converters to power core and memory rails of processors handling large rapid load changes with stringent voltage under / overshoot requirements. He previously designed off-line AC to DC converters in the 250 W to 2 kW range with a focus on emissions compliance. He is listed as either an author or co-author on 17 US patents related to power conversion. He received a BSEE degree from the Carnegie-Mellon University, Pittsburgh, Pennsylvania.

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References

1. Schurmann, Matthew, and Mohamed Ahmed. “Introduction to the Trans-inductor Voltage Regulator (TLVR).” Texas Instruments Power Supply Design Seminar SEM2600, literature No. SLUP413. 2024-2025.

The post Power Tips #133: Measuring the total leakage inductance in a TLVR to optimize performance appeared first on EDN.

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LED product and lighting maker Lumileds LLC of San Jose, CA, USA has released its latest LED engineered for deep dimming applications. The new LUXEON 2835 Commercial Deep Dimming LED offers what is claimed to be the industry’s most consistent dimming performance down to 1% dimming. With a Vf range of just 0.05 split into two Vf bins of 0.025, users no longer need to engage in complex binning processes, costly driver compatibility design, or burdensome testing...

• Smaller, more efficient products to ramp-up in volumes through 2025 across 750V and 1200V classes, will bring the advantages of silicon carbide beyond premium models to mid-size and compact electric vehicles.
• ST plans to introduce multiple silicon carbide technology innovations through 2027, including a radical innovation.

STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, is introducing its fourth-generation STPOWER silicon carbide (SiC) MOSFET technology. The Generation 4 technology brings new benchmarks in power efficiency, power density and robustness. While serving the needs of both the automotive and industrial markets, the new technology is particularly optimized for traction inverters, the key component of electric vehicle (EV) powertrains. The company plans to introduce further advanced SiC technology innovations through 2027 as a commitment to innovation.

“STMicroelectronics is committed to driving the future of electric mobility and industrial efficiency through our cutting-edge silicon carbide technology. We continue to advance SiC MOSFET technology with innovations in the device, advanced packages, and power modules,” said Marco Cassis, President, Analog, Power & Discrete, MEMS and Sensors Group. “Together with our vertically integrated manufacturing strategy, we are delivering industry leading SiC technology performance and a resilient supply chain to meet the growing needs of our customers and contribute to a more sustainable future.”

As the market leader in SiC power MOSFETs, ST is driving further innovation to exploit SiC’s higher efficiency and greater power density compared to silicon devices. This latest generation of SiC devices is conceived to benefit future EV traction inverter platforms, with further advances in size and energy-saving potential. While the EV market continues to grow, challenges remain to achieve widespread adoption and car makers are looking to deliver more affordable electric cars. 800V EV bus drive systems based on SiC have enabled faster charging and reduced EV weight, allowing car makers to produce vehicles with longer driving ranges for premium models. ST’s new SiC MOSFET devices, which will be made available in 750V and 1200V classes, will improve energy efficiency and performance of both 400V and 800V EV bus traction inverters, bringing the advantages of SiC to mid-size and compact EVs — key segments to help achieve mass market adoption. The new generation SiC technology is also suitable for a variety of high-power industrial applications, including solar inverters, energy storage solutions and datacenters, significantly improving energy efficiency for these growing applications.

Availability
ST has completed qualification of the 750V class of the fourth generation SiC technology platform and expects to complete qualification of the 1200V class in the first quarter of 2025. Commercial availability of devices with nominal voltage ratings of 750V and 1200V will follow, allowing designers to address applications operating from standard AC-line voltages up to high-voltage EV batteries and chargers.

Use cases
ST’s Generation 4 SiC MOSFETs provide higher efficiency, smaller components, reduced weight, and extended driving range compared to silicon-based solutions. These benefits are critical for achieving widespread adoption of EVs and leading EV manufacturers are engaged with ST to introduce the Generation 4 SiC technology into their vehicles, enhancing performance and energy efficiency. While the primary application is EV traction inverters, ST’s Generation 4 SiC MOSFETs are also suitable for use in high-power industrial motor drives, benefiting from the devices’ improved switching performance and robustness. This results in more efficient and reliable motor control, reducing energy consumption and operational costs in industrial settings. In renewable energy applications, the Generation 4 SiC MOSFETs enhance the efficiency of solar inverters and energy storage systems, contributing to more sustainable and cost-effective energy solutions. Additionally, these SiC MOSFETs can be utilized in power supply units for server datacenters for AI, where their high efficiency and compact size are crucial for the significant power demands and thermal management challenges.

Roadmap
To accelerate the development of SiC power devices through its vertically integrated manufacturing strategy, ST is developing multiple SiC technology innovations in parallel to advance power device technologies over the next three years. The fifth generation of ST SiC power devices will feature an innovative high-power density technology based on planar structure.  ST is at the same time developing a radical innovation that promises outstanding on-resistance RDS(on)  value at high temperatures and further RDS(on) reduction, compared to existing SiC technologies.

ST will attend ICSCRM 2024, the annual scientific and industry conference exploring the newest achievements in SiC and other wide bandgap semiconductors. The event, from September 29 to October 04, 2024, in Raleigh, North Carolina will include ST technical presentations and an industrial keynote on ‘High volume industrial environment for leading edge technologies in SiC’. Find out more here: ICSCRM 2024 – STMicroelectronics.

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The first day of Industry Tech Days 2024 begins with a keynote discussion with an expert from MIT about the challenges facing societal institutions to keep up with the rapid growth in AI. Join us throughout the day for great live sessions with Q&A.

The premise of artificial intelligence (AI) transforming the semiconductor industry is steadily taking shape, and two critical venues to gauge the actual progress are leading EDA houses and silicon foundries. The three major EDA toolmakers—Cadence, Synopsys, and Siemens EDA—have recently telegraphed their close collaboration on AI-driven design flows for TSMC’s advanced chip manufacturing nodes.

For a start, semiconductor fabs must have accurate lithography models for optical proximity correction in advanced manufacturing nodes. Huiming Bu, VP of Global Semiconductor R&D and Albany Operations at IBM Research, acknowledges that utilizing artificial intelligence and machine learning accelerates the development of highly accurate models that yield the best results during silicon fabrication.

On the design side, AI-powered EDA software is helping optimize complex IC designs while facilitating migration toward 2D/3D multi-die architectures. “Increased complexity, engineering resource constraints and tighter delivery windows were challenges crying out for a full AI-driven EDA software stack from architectural exploration to design and manufacturing,” said Shankar Krishnamoorthy, GM of Synopsys EDA Group.

Below is a brief recap of EDA toolmakers’ current liaison with TSMC centered on AI-driven design flows for advanced process nodes.

Start with Cadence Design Systems, working closely with TSMC on Cadence.AI, a chips-to-systems AI platform that spans all aspects of design and verification while facilitating digital and analog design automation using AI tools. The two companies are also collaborating on the Cadence Joint Enterprise Data and AI (JedAI) Platform, which employs generative AI for design debug and analytics.

Figure 1 The JedAI platform for generative AI applications provides workflow automation, model training, data analytics, and large language model (LLM) services. Source: Cadence

Synopsys has also its own AI-driven EDA suite Synopsys.ai for design, verification, testing and manufacturing of advanced digital and analog chips. Synopsys.ai includes DSO.ai, an AI application for optimizing layout implementation workflows, and VSO.ai, an AI-driven verification solution.

The company’s CEO Sassine Ghazi told the Synopsys User Group (SNUG) conference audience that Synopsys.ai has achieved hundreds of tape-outs to date and is delivering more than a 10% boost in performance, power, area (PPA), double-digit improvements in verification coverage, and 4x faster analog circuit optimization when compared to optimization without the use of AI.

Figure 2 Synopsys.ai offers AI-driven workflow optimization and data analytics solutions meshed with generative AI capabilities. Source: Synopsys

Like Cadence and Synopsys, Siemens EDA is extending its AI-centric collaboration with leading fabs like Intel Foundry and TSMC. Its new Solido Simulation Suite features AI-accelerated simulators for IC design and verification. The company has also unveiled Catapult AI NN software for High-Level Synthesis (HLS) of neural network accelerators integrated into application-specific integrated circuits (ASICs) and system-on-chips (SoCs).

Figure 3 Solido Simulation Suite integrates AI-accelerated SPICE, Fast SPICE, and mixed-signal simulators to help engineers accelerate critical design and verification tasks. Siemens EDA

AI in the semiconductor industry is still in its infancy, and these efforts to create AI-optimized design flows mark baby steps for infusing AI into the electronics design realm. However, the timing seems right, given how advanced nodes are desperately seeking intelligent solutions to bolster yields and silicon defect coverage.

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