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When a design needs auxiliary voltage rails and the associated current loads are modest, capacitor pump voltage multipliers are often the simplest, cheapest, and most efficient way to make them.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The simplest of these is the diode pump voltage doubler. It consists of just two diodes and two capacitors but has the inherent disadvantages of needing a separately sourced square wave for drive and of producing an output voltage that’s at least two diode drops less than twice the supply rail. Active switching (typically with CMOS FETs) is required to avoid this inefficiency and accurately double the supply.

CMOS voltage doubler chips are available off the shelf. An example is the Maxim MAX1682. It serves well in applications where the current load isn’t too heavy, but it (and similar devices) isn’t particularly cheap. The 1682 costs nearly $4 in singles, creating the temptation to see if we can do better, considering that generic CMOS switch chips (like the 74AC14) can be had in singles for 50 cents.

A plan to do so begins with Figure 1, showing a simplified sketch of a CMOS logic inverter.

Figure 1 Simplified schema of typical basic CMOS gate I/O circuitry showing clamping diodes and complementary FET switch pair.

Notice the input and output clamping diodes. These are put there by the fabricator to protect the chip from ESD damage, but a diode is a diode and can therefore perform other useful functions, too. Similarly, the P-channel FET pair was intended to connect the V+ rail to the output pin when outputting a logic ONE, and the N-channel for connection to V- to pin for a ZERO. But CMOS FETs will willingly conduct current in either direction. Thus, current running from pin to rail works equally well as from rail to pin. 

Figure 2 shows how these basic facts relate to charge pumping and voltage multiplication.

Figure 2 Simplified voltage doubler, showing driver device (U1), commutation device (U2), and coupling (Cc), pump (Cp), and filter (Cf) capacitors.

Imagine two inverters interconnected as shown in Figure 2 with a square-wave control signal coupled directly to U1’s input and through DC blocking cap Cc to U2 with U2’s input clamps providing DC restoration.

Consider the ONE half cycle of the square-wave. Both U1 and U2 N-channel FETs will turn on, connecting the U2 end of Cp to V+ and the U1 end to ground, charging Cp to V+. Note the reversed polarity of current flow from U2’s output pin due to Cp driving the pin negative.

Now consider what happens when the control signal reverses to ZERO.

The P FETs will turn ON while the N FETs turn OFF. This forces the charge previously accepted by Cc to be dumped to Cf through U2’s output and V+ pin, thus completing a charge-pumping cycle that delivers a quantum of positive charge to be deposited on Cf. Note reversed current flow through U2 occurs again. The cycle repeats with the next alternation of the control signal, and so on, etc., etc.

During startup, until sufficient voltage accumulates on Cf for normal operation of U2’s internal circuitry and FET gate drive, U2 clamp diodes serve to rectify the Cp drive signal and begin the charging of Cf until the FETs can take over.

So much for theory. Translation of Figure 2 into a complete voltage doubler is shown in Figure 3.

Figure 3 Complete voltage doubler: 100 kHz pump clock set by R1C1, Schmidt trigger , driver (U1), and commutator (U2)

A 100 kHz pump clock is output on pin 2 of 74AC14 Schmidt trigger U1. This signal is routed to the five remaining gates of U1 and (via coupling cap C2) the six gates of U2. Positive charge transfer occurs through C3 into U2 and from there accumulates on filter cap C5.

Even though Schmidt hysteresis isn’t really needed for U2, another AC14 was chosen for it in pursuit of matched switching delay times, thus improving efficiency-promoting synchronicity of charge transfer. Some performance spec’s (V+ = 5V) are:

• Impedance of 10 V output: 8.5 Ω
• Maximum continuous load: 50 mA
• Efficiency at 50 mA load: 92%
• Efficiency at 25 mA load: 95%
• Unloaded power consumption: 440 µW
• Startup time < 1 millisecond

So, what happens if merely doubling V+ isn’t enough? As Figure 4 illustrates, this design can be easily cascaded to make an efficient voltage tripler. Extension to even higher multiples is also possible.

Figure 4 Adding four inexpensive parts suffices to triple the supply voltage.

Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.

 Related Content

• Voltage inverter uses gate’s output pins as inputs and its ground pin as output
• Voltage Multipliers
• Easy four-quadrant multiplier using a quad op amp
• A simple, accurate, and efficient charge pump voltage inverter for $1 (in singles)

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I just picked up this vintage metronome at the thrift store and found this really cool looking PCB design when I went to change the battery. I've never seen anything like this, so I thought I would share! The soldering is pretty damn sloppy, but the connections are so psychedelic! Super cool submitted by /u/Snoo_29332 [link] [comments]

Market research firm TrendForce’s latest reports indicate a significant turning point for the LED lighting market in 2024, as an estimated quantity of 5.8 billion LED lamps and luminaires reach the end of their lifespan. This is set to trigger a substantial wave of secondary replacements, breathing new life into the market and boosting total LED lighting demand to 13.4 billion units, the firm adds...

Union Minister for Steel and Aviation, Jyotiraditya M. Scindia, today virtually flagged off India’s first Green Hydrogen Plant in the Stainless Steel sector located at Jindal Stainless Ltd., Hisar, Haryana.

This mega project- a collaboration between Jindal Stainless Ltd. and Hygenco, is set to be the world’s first off-grid Green Hydrogen plant for the stainless-steel industry and the world’s first Green Hydrogen plant with rooftop and floating solar. Furthermore, the plant is expected to reduce approx. 2700 metric tonnes of carbon emissions annually, and a total of 54,000 tonnes of CO2 emissions over the next 20 years.

In his address, Jindal said “We cannot think of decarbonisation without reducing the emissions accompanying such critical manufacturing processes. And this is where this path-breaking and pioneering green hydrogen plant comes in.”

This project is poised to revolutionise green growth and green jobs that will further drive the country’s journey towards the target of net zero carbon emission by 2070. “India’s rich history of environmentalism, deeply embedded in its traditions and practices, is now being revitalized through modern strategies”, Scindia expressed.

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Helps simplify operation and save energy in industrial power supplies, portable device chargers, and AC/DC adapters

STMicroelectronics’ SRK1004 synchronous-rectifier controller eases the design and enhances the efficiency of converters built with silicon or GaN transistors, including industrial power supplies, portable device chargers, and AC/DC adapters.

Capable of withstanding up to 190V at its sense input, the SRK1004 can be connected in a high-side or low-side configuration. Four variants let users avoid complex calculations by optimizing their design through device selection alone, selecting gate-drive voltage between 5.5V or 9V, with logic-level MOSFETs, standard MOSFETs, or GaN transistors. Suitable for noncomplementary active clamp, resonant, and quasi-resonant (QR) flyback topologies, the SRK1004 introduces a next-generation turn-off algorithm that simplifies operation and saves energy.

The features of this controller enable converters to provide a high output power rating within compact dimensions. The operating frequency can be up to 500kHz, allowing the use of small magnetic components as well as maximizing the benefits of wide-bandgap technology when using GaN transistors. The controller is fabricated in ST’s silicon-on-insulator (SOI) process, which ensures robust performance while permitting a tiny 2mm x 2mm DFN-6L package.

By operating with a supply voltage from 4V to 36V, the SRK1004 can be powered from a variety of standard industrial bus voltages. The wide input-voltage range also provides flexibility to adjust the step-down ratio for optimum efficiency. Also, with fast-acting short-circuit detection built-in, the controller helps build rugged and reliable equipment.

Of the four variants introduced, the SRK1004A and SRK1004B are configured for 5.5V gate-drive voltage and can be used with logic-level MOSFETs or GaN transistors. The SRK1004C and SRK1004D for 9V gate-drive voltage are suited to MOSFETs designed for standard gate-drive signals.

All variants of the SRK1004x synchronous rectification controllers are in production now and available from $0.45 for orders of 1000 units. The evaluation boards, EVLSRK1004A, EVLSRK1004B, EVLSRK1004C, and EVLSRK1004D, are also available to accelerate evaluation and design start with each type, at the budgetary price of $50.00.

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After having been informed of the unexpected cancellation of a cornerstone project for its micro-LED program, ams OSRAM GmbH of Premstätten, Austria and Munich, Germany says that it is re-assessing its micro-LED strategy. Discussions with the related customer — reported to be Apple — are ongoing...

Semiconductor production test and reliability qualification equipment supplier Aehr Test Systems of Fremont, CA, USA has shipped the first order from a major silicon photonics customer for a new high-power configuration of its FOX-XP system for volume production wafer-level burn-in and stabilization of next-generation silicon photonics integrated circuits (ICs)...

Ultra-fast supercapacitors now available from Farnell feature cutting-edge, dual-layer technology

element14 is now stocking the range of high-power electric double layer capacitor (EDLC) radial supercapacitors from Abracon, a supplier of leading-edge, innovative electronic components including frequency control, timing, power, magnetics, RF and antenna solutions.

element14 Product Segment Leader for Abracon, Euan Gilligan, said, “We are delighted to stock this remarkable line of EDLC radial supercapacitors, which are specifically engineered to meet the accelerating demand for fast-charging, high-capacity energy storage solutions. They are key components for a wide range of industries, including automotive, renewable energy, industrial automation, consumer electronics and many more.”

The EDLC supercapacitors are efficient and compact, providing exceptional energy density. Available in 2.7-volt and 3.0-volt supercapacitors are top performers for applications that require rapid power bursts due to their ultra-fast charge and dissipation capabilities.

Moreover, these supercapacitors are designed for longevity, with an impressive lifecycle that minimises maintenance costs and enhances system durability. This ability eliminates the operational safety concerns often seen in lithium batteries.

They are also able to operate across a wide temperature range, making them suitable for deployment in challenging environmental conditions. For example, they can operate down to -40°C, which traditional batteries cannot.

Gilligan added, “These supercapacitors are ideal for uninterrupted and backup power supplies, micro energy storage, data transmission and various energy start-up designs. They are also especially useful for wireless networks, energy harvesting, cold-crack engines, microgrids and more.”

Abracon provides an online selection tool that enables developers to select the desired supercapacitor performance by allowing them to filter by type, current, tolerance and more.

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Servotech Power Systems Ltd., a leading manufacturer of EV chargers in India, has bagged an order of 1400 DC fast EV chargers from Indian Oil Corporation Limited (IOCL) and other EV charger OEMs. The total order is valued at 111 crores and involves two charger variants of 60 kW and 120 kW. The order secured by IOCL involves Servotech manufacturing, supplying and installing DC EV chargers nationwide, prioritizing deployment at Indian Oil petrol pumps and other said locations. Additionally, Servotech will also manufacture and supply the rest of the chargers to EV charger OEMs. This move is seen as an important step as it will promote decarbonized mobility and cater to the evolving needs of the EV charging infrastructure.

• Recently, Servotech received 1500 DC Fast EV charger orders from HPCL and OEMs.
• The company also received an 1800 DC EV chargers order from BPCL.
• The total number of EV charger orders from oil marketing companies and EV charger OEMs stands at 4700 units.
• The total value of the combined orders stands at 333 crores.

Servotech is committed to installing all these chargers by the end of the FY 2024-25. Servotech will deploy 5% of the 4700 units of DC EV chargers by March 31st, 2024. Additionally, Servotech will also complete the deployment of 2649 AC EV chargers orders received by BPCL by the same deadline i.e. 31st March 2024.

Sarika Bhatia, Director of Servotech Power Systems Ltd., said on this commendable order wins: “We are honored to contribute to India’s E-Mobility revolution alongside major oil marketing companies like IOCL, HPCL, and BPCL. Together, we are committed to accelerating the transition to a sustainable future. It’s a source of pride that these industry leaders have chosen us based on our manufacturing capabilities and quality conscious EV chargers. As a premier EV charger manufacturer, we aim to transform India into a nation where EVs are not just a vision but a reality. With shared vision and unwavering dedication, we believe in making this dream come true. Leveraging the network of oil marketing companies and installing EV chargers at their petrol pumps, we’re building a robust infrastructure for EVs, making them accessible to all, everywhere”.

“Our top-notch DC fast EV chargers are poised to create e-mobility hubs, streamlining transactions, enhancing accessibility, simplifying user experience, and aiding navigation for EV drivers. With our proactive assistance, we’re driving a seamless shift toward a greener, more sustainable transportation landscape” said Sarika Bhatia.

The post Servotech Secures another Order for 1400 DC Fast EV Chargers worth Rs. 111 Crore from IOCL and Other OEMs appeared first on ELE Times.

Author: Amit Sethi, Technical Marketing Manager, STMicroelectronics Pvt Ltd

NFC, a short-range wireless communication technology, enables data exchange between devices when they are brought into proximity. In medical applications, NFC can play a pivotal role in facilitating communication between medical devices, improving patient identification, and ensuring secure data transfer.

Patient Identification and Authentication: One of the critical aspects of healthcare is accurate and secure patient identification. NFC technology provides a robust solution by enabling healthcare providers to create electronic patient records linked to NFC tags or cards. These tags can store essential patient information such as medical history, allergies, and current medications. When a patient arrives, medical staff can quickly access this information by scanning the NFC tag with a compatible device, ensuring that the right patient receives the right care. This not only enhances patient safety but also streamlines the registration process, reducing administrative overhead.

Medication Management: NFC technology offers innovative solutions to improve medication management within healthcare facilities. Smart medication packaging equipped with NFC tags can be used to track medication usage, monitor adherence, and provide real-time data on a patient’s medication history. Patients can use NFC-enabled devices to access information about their prescribed medications, including dosage instructions and potential side effects. This technology helps in preventing medication errors and enhances overall patient education regarding their treatment plans.

Medical Device Connectivity: In a hospital setting, various medical devices are used to monitor patients and gather vital health data. NFC facilitates seamless connectivity between these devices, allowing for efficient data sharing and integration. For example, an NFC-enabled wearable device worn by a patient can transmit real-time health data to a monitoring station, enabling healthcare professionals to make timely decisions. This connectivity also extends to medical equipment calibration and updates. NFC can be employed to wirelessly update the software or firmware of medical devices, ensuring that they are always operating with the latest features and security patches.

Access Control and Security: Security is paramount in healthcare and NFC technology
contributes significantly to access control and data security. NFC cards or badges can serve as secure identification credentials for healthcare staff, limiting access to sensitive areas and patient records. This helps in preventing unauthorized access, safeguarding patient privacy, and maintaining the integrity of healthcare data. Moreover, NFC technology can be integrated into mobile devices, allowing healthcare professionals to securely access patient information through encrypted connections. This ensures that patient data remains confidential and protected against unauthorized access.

Contactless Payments in Healthcare: The use of contactless payments has become
commonplace in various industries, and healthcare is no exception. NFC technology facilitates secure and convenient contactless payment solutions within healthcare facilities. Patients can make payments for services or copayments by simply tapping their NFC-enabled payment cards or mobile devices. This not only streamlines the payment process but also reduces the risk of handling physical currency or cards, contributing to a more hygienic and efficient financial transaction experience in healthcare settings.

Patient Engagement and Monitoring: NFC technology plays a vital role in patient engagement and monitoring. Wearable devices equipped with NFC can be used to track patients’ activity levels, monitor vital signs, and transmit data to healthcare providers in real time. This proactive approach to patient monitoring allows for early detection of potential health issues and timely interventions. Patients can also use NFC-enabled devices to check in for appointments, access educational materials, and receive personalized health recommendations. This empowers the patients to engage actively in their healthcare journey.

NFC technology has the potential to revolutionize medical applications, offering solutions that enhance patient care, improve efficiency, and contribute to the overall advancement of
healthcare systems. From secure patient identification to streamlined medication management and innovative patient engagement strategies, NFC provides a versatile platform for innovation in the healthcare sector. As technology continues to evolve, the integration of NFC in medical applications will likely become more widespread, driving further improvements in patient outcomes and healthcare delivery. With careful consideration of security measures and industry standards, NFC stands poised to play a transformative role in shaping the future of healthcare.

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Hi !! Im happy to share my latest project. It's an ESP32-based board crafted for flexible projects, featuring an IMU, ADCs, XBee socket, RTC, Buzzer, Li-ion battery charger (1.5A) and monitor, general-purpose IOs, pushbuttons, RGB LEDs, SD card slot, Qwiic connectors, ambient temperature, humidity, pressure sensors, and USB programming capability! Almost completely SMT. The PCB is a 4-layer design that I personally assembled <3 https://preview.redd.it/svxw5hlczxlc1.png?width=4000&format=png&auto=webp&s=e54bd89516de9d19a2950ca8faae45d8c4ab28cc submitted by /u/Slimethon [link] [comments]

submitted by /u/wuyongzheng [link] [comments]

Editor’s Note: This is a four-part series of DIs proposing improvements in the performance of a “traditional” PWM—one whose output is a duty cycle-variable rectangular pulse which requires filtering by a low-pass analog filter to produce a DAC. The first part suggests mitigations and eliminations of common PWM error types. The second discloses circuits driven from various Vsupply voltages to power rail-rail op amps and enable their output swings to include ground and Vsupply. This third part pursues the optimization of post-PWM analog filters.

 Part 1 can be found here.

 Part 2 can be found here.

Recently, there has been a spate of design ideas (DIs) published (see Related Content) which deals with microprocessor-generated pulse width modulators driving low-pass filters to produce DACs. Approaches have been introduced which address ripple attenuation, settling time minimization, limitations in accuracy, and enable outputs to reach and include ground and supply rails. This is the third in a series of DIs proposing improvements in overall PWM-based DAC performance. Each of the series’ recommendations are implementable independently of the others. This DI addresses low pass analog filters.

Wow the engineering world with your unique design: Design Ideas Submission Guide

The PWM output

Spectrally, the PWM output consists of a desirable DC (average) portion and the remainder—undesirable AC signals. With a period of T, these signals consist of energy at frequencies n/T, where n = 1, 2, 3, etc., that is, harmonics of 1/T. If the PWM switches between 0 and 1, for every harmonic n there exists a duty cycle corresponding to a peak signal level of (2/π)/n. This shows the futility of an attenuation scheme which focuses on a notch or band reject type of filter—there will always be a significant amount of energy that is not attenuated by such. The highest amplitude harmonic is the first, n = 1. At the very least, this harmonic must be attenuated to an acceptable level, α. Any low pass filter that accomplishes this will apply even more attenuation to the remaining harmonics which are already lower in level than the first. In summary, the search for the best filter will focus on what are called all-pole low pass filters, which is another way of saying low pass filters which lack notch and band-reject features.

The skinny on low pass all-pole filters

Analog filters can be defined as a ratio of two polynomials in the complex (real plus imaginary) variable s:

Where I ≤ K. The terms zi and pi are referred to respectively as the zeroes and the poles of the filter. K is the order (first, second, etc.) of the filter as well as the number of its poles. All-pole filters of unity gain at DC can be specified simply as:

Filter types include Butterworth, Bessel, Chebyshev, and others. These make different trade-offs between the aggressiveness of attenuation with increasing stop-band frequency and the rapidity of settling in response to a time domain impulse, step, or other disturbance. Improving one of these generally denigrates the other. Tables of poles for various orders and types of these filters can be found in the reference [1]. Values given are for filters which at approximately 1 radian per second (2π Hz) exhibit 3 dB of attenuation with respect to the level at DC. This point is considered to be the transition between the low frequency pass and high frequency stop bands. Multiplying all poles by a frequency scaling factor (FSF) will cause the filter to attenuate 3 dB at 2π·FSF Hz. The frequency response of a filter can be calculated by substituting j·2π·f for s in H(s) and taking the magnitude of the sum of the real and imaginary parts. Here, j = √-1 and f is the frequency in Hz.

The time domain response of a filter to a change in PWM duty cycle reveals how quickly it will settle to the new duty cycle average. For a filter of unity gain at DC, this involves subtracting from 1 the inverse Laplace transform of H(s)/s. A discussion of Laplace transforms, their inverses, and practical uses is beyond the scope of this DI. These inverse transforms can, however, be readily determined by using a web-based tool [2].

Requirements of an optimal filter

A filter must attenuate the maximum value over all duty cycles (2/π) of the PWM first harmonic by a factor of α. A b-bit PWM has a resolution of Full-Scale·2-b. So, for the first harmonic peak to be no greater than ½ LSB, α should be set to (π/2)·2-(b+1). Asking for more attenuation would slow the filter response to a step change in duty cycle. From the time domain perspective, the time ts should be minimized for the filter to settle to +/- α · Full Scale in response to a duty cycle change from Full Scale to zero.

Towards an optimal filter

Consider a 12-bit PWM clocked from a 20 MHz source. The frequency of its first harmonic is F0 = 4883 Hz, and its α is 1.917·10-4. 3rd, 5th, and 7th order filters of types Bessel, Linear Phase .05° and .5° Equiripple error, Gaussian 6 dB and 12 dB, Butterworth, and .01 dB Chebyshev are considered. These are roughly in order of increasingly aggressive attenuation with frequency coupled with increasing settling times. Appropriate FSFs are needed to multiply the poles (listed in reference [1]) of each filter to achieve attenuation α at F0 Hz. Excel’s Solver [3] was used to find these factors. The scaled values were divided by 2π to convert them to Hertz and applied to LTspice’s [4] 2ndOrderLowpass filter objects in its Special Functions folder to assemble complete filters. The graph in Figure 1 shows the frequency responses of 24 scaled filters. These include 3rd, 5th, and 7th order versions of the filter types listed above. These filters were named after the mathematicians who developed the math describing them (I have for some reason failed to find any information about Mr. or Ms. Equiripple). Additionally, there are the same three orders of one more filter type that was developed by the author and will be described later. Although the author makes no claims of being a mathematician, for want of an alternative, these have been named Paul filters. (An appalling choice, I’m sure you’ll agree.)

Figure 1 The frequency response of 24 scaled filters including include 3rd, 5th, and 7th order versions of the 7 filter types listed above (Bessel, Linear Phase, Equiripple, Gaussian, Butterworth, Chebyshev and the Paul filter developed by the author) where the value of α is depicted by the horizontal red line.

In Figure 1, the value of α is depicted by the horizontal line. It and all the filter responses intersect at a frequency of F0 (the PWM’s first harmonic) satisfying the frequency response attenuation requirement. Figure 2 is the Bessel filter portion of the LTspice file which generates the above graph. The irregular pentagons are LTspice’s 2ndOrderLowPass objects. The resistors and capacitors implement first order sections. H = 1 is the filter’s gain at DC.

Figure 2 The Bessel filter portion of the LTspice file which generates the response in Figure 1, U1-U6 are LTspice’s 2ndOrderLowPass objects, resistors and capacitors implement first order sections, and H = 1 is the filter’s gain at DC.

By changing the “.ac dec 100 100 10000” command in the file to “.tran 0 .01 0”, replacing the “SINE (0 1) AC 1” voltage source with a pulsed source “PULSE(1 0 0 1u 1u .0099 .01)” and running the simulation, the response of these filters to a duty cycle step from 1 V to 0 V is obtained as shown in Figure 3.

Figure 3 Replacing the AC voltage source with a pulsed source to change the duty cycle step of the filter response from 1 V to 0 V.

Oh, what a lovely mess! The vertical scale is the common log of the absolute value of the response—absolute value because the response oscillates around zero, and log because of the large dynamic range between 1 and α, the latter of which is again shown as a horizontal line.

Which filter’s absolute response settles (reaches and remains less than α) in the shortest period of time? To find the answer to that question, use is made of LTspice’s “Export data as text” feature under the “File” option made available by right-clicking inside the plot. This data is then imported into Excel. Each filter’s data is parsed backwards in time starting from 10 ms. The first instants when the responses exceed α are recorded. These are the times that the filters require to settle to α. (As can be seen, there were some that require more than 10 ms to do so.) For each filter order, it was determined which type had the shortest settling time. Table 1 shows the settling times to ½ LSB for 8-bit through 16-bit PWMs of 3rd, 5th, and 7th orders of filters of various types.

Table 1 Settling times to ½ LSB for 8-bit through 16-bit PWMs of 3rd, 5th, and 7th orders for various types of filters. The fastest settling times are shown in bold red while those that failed to settle within 10 ms are grey and listed as “> 10 ms”.

The entries in each table row with the fastest settling time is shown in bold red. Those which failed to settle within 10 ms are listed as > 10 ms and are greyed-out. In general, the 7th orders settled faster than the 5th orders, which were noticeably faster than the 3rd’s. Also, those with the lower Q sections settled faster than the higher Q alternatives (again, see the tables in reference [1]). The Chebyshev filters with ripples greater than .01 dB (not depicted) for instance, had higher Q’s than all the ones listed above and had hopelessly long settling times.

As a group, the Paul filters settled the fastest, but that does not preclude the selection of another filter in an instance when it settles faster. Still, it’s worth discussing how the Pauls were developed. Starting with the 3rd, 5th, and 7th order frequency-scaled Bessel poles, the Excel Solver evaluated the inverse Laplace transforms of the filters’ functions H(s). It was instructed to vary the pole values while minimizing the maximum value of the filter response after a given time ts. This was made subject to the constraint that the amplitude response of |H(2πj·F0)| be α, where F0 = 20MHz / 212 and α = (π/2)·2-(12+1). If the maximum response exceeded α for a given ts, ts was increased. Otherwise ts was reduced. Several runs of Solver led to the final set of filter poles. It is interesting that even though the optimization was run for a 12-bit PWM only, settling times at other bit lengths between 8 and 16 is still rather good and in most cases superior to those of the other well-known filters. The Paul filter poles and Qs are listed in Table 2.

Table 2 The poles and Qs for 3rd, 5th, and 7th order Paul filter.

Table 3 includes FSFs for the poles of the well-known filters. The unscaled poles are given in the tables of reference [1]. The scaled poles are characteristic of filters which also attenuate a frequency of F0 by a factor of α.

Table 3 The FSFs for the poles of the well-known filters in the tables of reference [1] for the values of α and F0.

 Implementing a filter

A starting point for the implementation of a filter whose poles are taken from a reference table is to apply to those poles an appropriate FSF.  These factors are given for well-known filters in Table 3 for an attenuation, α, at a frequency of F0 Hz. In Table 2, the Paul filter poles have already been scaled as such. For any of these filters, to change the α from a frequency F0 to F1 Hz, the poles should be multiplied by an FSF of F1/F0.

In settling quickly to the small value of α, some of the biggest errors in filter performance are due to component tolerances. To limit these errors, resistors should be metal film, 1% at worst with 0.1% preferred.  Capacitors should be NPO or C0G for temperature and DC voltage stability, 2% at worst and 1% preferred. Smaller value resistors result in a quieter design and lead to smaller offset voltages due to op amp input bias and offset currents. However, these also require larger-valued, bigger, and more expensive capacitors. Keep these restrictions in mind when proceeding with the following steps.

For a first order section with pole ω:

1. Start by guessing values of R and C such that RC = 1/ω.
2. Choose a standard value NPO or COG capacitor close to that value of C.
3. Calculate R’ = 1/(ω·C) where C is that standard value capacitor.
4. Choose for R the next smaller standard value of R’ and make up the difference with another smaller resistor in series. Although this will not compensate for the components’ 1% and 2% tolerances, it will yield a result which is optimal on average.
5. Connect one terminal of R to the PWM output and the other to the capacitor C (ground its other side) and to the input of a unity gain op amp. If gain is required in the aggregate filter, it is this op amp which should supply it rather than one which implements a second order section; unlike second order sections, gain in this op amp has no effect on the R-C section’s AC characteristics because there is no feedback to the passive components. The output of this op amp should drive the cascade of remaining second order sections (Figure 4).

Figure 4 Recommended configuration where one terminal of R is connected to the PWM output, and the other is connected to the capacitor C (ground its other side) and to the input of a unity gain op amp.

For second order sections with pole ω and quality factor Q, error sources are again component values. Errors can be exacerbated by the choice of a filter topology. A second order Sallen Key [5] section with the least sensitivity employs an op amp configured for unity gain as shown in Figure 5.

Figure 5 A second order Sallen Key section with the least sensitivity employs an op amp configured for unity gain.

To select component values:

1. Start by choosing values of R and C such that RC = 1/ω.
2. Choose standard values of C1 and C2 similar to C such that C1 / C2 is as large as possible, but no larger than 4Q2. Creating a table of all possible capacitor ratios is helpful in selecting the optimal ratio.
3. Calculate D = (1 – 4Q2·C2/C1)0.5 and W = 2·Q·C2·ω
4. For R1a, select a standard resistor value slightly less than (1 + D)/W and add R1b in series to make up the difference.
5. For R2a, select a standard resistor value slightly less than (1 – D)/W and add R2b in series to make up the difference.
6. If there are more than one second order section, the sections should be connected in order of decreasing values of Q to minimize noise.

A PWM filter example

Consider a 5th order Paul filter with an attenuation of α at a frequency F1 = F0/2. Each of the ω values in the Paul filter table would be multiplied by an FSF of F1/F0 = ½, but the Q’s would be unchanged. The following schematic shown in Figure 6 satisfies these constraints.

Figure 6 A 5th order Paul filter scaled to operate at F0/2 Hertz.

 Designing PWM analog filters

A set of tables listing settling times to within ½ LSB of 8 through 16-bit PWMs of period 204.8 µs (1/4883 = 1/F0 Hz) has been generated for 3rd, 5th, and 7th order versions of eight different filter types. These filters attenuate the peak value of steady state PWM-induced ripple to ½ LSB. From these listings, the filter with the fastest settling time is readily selected. These filters can be adapted to a new PWM period by multiplying their poles by a scaling factor equal the ratio of the old to new periods. New settling times are obtained by dividing the ones in the tables by that same ratio.

Pole scaling factors for the operation of well-known filters at F0 are supplied in a separate table. The poles of these filters are available in reference [1] and should be multiplied by the relevant factor to accomplish this. A new “Paul” filter (already scaled for F0 operation) has been developed which in most cases has faster settling times than the well-known ones while providing the necessary PWM ripple attenuation. As with the others, it too can be scaled for operation at different frequencies.

It should be noted that component tolerances will lead to filters with attenuations and settling times which differ somewhat from the calculations presented. Still, it makes sense to employ filters with the smallest calculated settling time values.

Christopher Paul has worked in various engineering positions in the communications industry for over 40 years.

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• Cancel PWM DAC ripple with analog subtraction
• Cancel PWM DAC ripple with analog subtraction—revisited
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• Fast PWM DAC has no ripple

 References

1. http://www.analog.com/media/en/training-seminars/design-handbooks/basic-linear-design/chapter8.pdf%20 (specifically Figures 8.26 through 8.36. This reference does a great job of describing the differences between the filter response types and filter realization in general.)
2. https://www.wolframalpha.com/input?i=inverse+Laplace+transform+p*b%5E2%2F%28%28s%5E2%2Bb%5E2%29*%28s%2Bp%29%29
3. https://support.microsoft.com/en-us/office/define-and-solve-a-problem-by-using-solver-5d1a388f-079d-43ac-a7eb-f63e45925040
4. https://www.analog.com/en/design-center/design-tools-and-calculators/ltspice-simulator.html
5. https://www.ti.com/lit/an/sloa024b/sloa024b.pdf

The post Parsing PWM (DAC) performance: Part 3—PWM Analog Filters appeared first on EDN.

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Infineon Technologies has launched the new Automotive PSoC 4100S Max family. This microcontroller device family expands Infineon’s portfolio of CAPSENSE-enabled Human Machine Interface (HMI) solutions for automotive body/HVAC and steering wheel applications by delivering higher flash densities, GPIOs, CAN-FD, and HW-Security.

The Automotive PSoC 4100S Max with fifth-generation CAPSENSE technology offering 10x higher sensitivity is available in 100-TQFP (14×14 mm²), 64-TQFP (10×10 mm²) and 48-QFN (7×7 mm²) packages. It is an optimal solution for automotive HMI applications requiring low-power consumption, multiple sensing pins (50+), configurable scan times to optimize the system’s refresh rate, high-speed communication (CAN-FD, I2C), and dedicated HW-cryptography for enhanced security while offloading the main CPU. This device offers up to 84 GPIOs and 384 KB of flash memory (the largest PSoC4 flash memory in its class).

The Automotive PSoC 4100S Max is AECQ-100 qualified up to 125 °C ambient temperature and also provides support towards ASIL-B (ISO 26262-ready), which helps the integrator to achieve system level compliance for automotive application supported by Infineon’s latest ModusToolbox development platform, the devices allow developers an easy implementation for a variety of use cases.

The post PSoC Automotive 4100S Max supports fifth generation CAPSENSE technology with higher performance appeared first on ELE Times.

Samsung Semiconductor India Research (SSIR) has announced the opening of its new R&D facility in Bengaluru. The expansion marks a significant milestone in SSIR’s commitment to driving cutting-edge semiconductor research and development in India, while addressing the company’s growing needs for advanced infrastructure. This is SSIR’s second office in Bengaluru, with a capacity to accommodate close to sixteen hundred professionals. Located at Bagmane Capital Tech Park in Angkor-West, the facility spans 1,60,000 square feet across four floors.

The new campus of Samsung Semiconductor India Research (SSIR) features a modern, open-plan layout across four floors, encouraging collaboration and agility. The design includes designated hot-desking areas for workforce flexibility. There are over sixty (60) state-of-the-art meeting rooms for seamless communication, and amenities such as a fully equipped cafeteria, medical facilities, dedicated nap rooms, and recreational areas for rejuvenation for all employees. Additionally, transport shuttle services are also available which will further enhance convenience, ensuring a holistic work experience for SSIR employees.

“It is an exciting moment for us as the new facility in Bengaluru embodies our commitment to expanding our footprint in India and enabling a vibrant environment for our exceptional team members. This new hub reinforces SSIR’s standing as a crucial player in Samsung Semiconductor’s global innovation ecosystem as we open the doors to new opportunities”, said Balajee Sowrirajan, EVP & MD at Samsung Semiconductor India Research.

SSIR currently has a strength of over four thousand and five hundred (4500) employees and will add over seven hundred (700) people including fresh graduates as well as lateral hires across teams in India.

The post Samsung Semiconductor India expands R&D footprint with a new state-of-the-art R&D facility in Namma Bengaluru appeared first on ELE Times.