Новини світу мікро- та наноелектроніки

The Government of India has taken a landmark step towards rendering the tax structure simpler and thereby easing the financial burden upon the common man while while Prime Minister Shri Narendra Modi unveiled the next generation of GST reforms during the festive season, marking a pivotal moment in India’s economic transformation. The changes in GST rates have come into force on Monday, September 22; the news has come as a relief for the electronics industry.

As per the reports, the government has announced major concessions on taxes on many household electronics and technology products:

Electric Accumulators: The GST rate has been reduced from 28% to 18%, substantially lowering the cost of backup power solutions for digital devices and small appliances. This change is expected to boost the adoption of energy storage systems in homes and offices, especially in areas with unreliable power supply.

Composting Machines: With a reduction from 12% to 5%, the rates now encourage a wider acceptance of organic waste management and waste-to-energy solutions.

Two-Way Radios: Taxes have been shrunk from the erstwhile 12% to a meagre 5%. On one hand, such tariff change led to lowered procurement costs for the security forces, including the police department, paramilitary units, and defense establishments.

Industry experts wish these reforms have far-reaching benefits. According to the Industry experts, reduction will foster domestic demand, increase the sale of electronic goods and further enlarge the market for local producers.

Rationalised GST under the new reforms will, therefore, be better placed to make the electronics sector accessible, affordable, and competitive while also striving to sustain digitisation and empowerment on the government level.

The post New GST Rates Bring Relief to Electronics Industry from September 22 appeared first on ELE Times.

What’s a hybrid relay? How does it work? What are its key building blocks? Whether you are designing a power control system or tinkering with a do-it-yourself automation project, it’s important to demystify the basics and know why this hybrid approach is taking off. Here is a brief tutorial on hybrid relays, which also explains why they are becoming the go-to choice for engineers and makers alike.

Read the full article at EDN’s sister publication, Planet Analog.

Related Content

• Common Types of Relay
• IC drives up to four single-coil latching relays
• Designing a simple electronic impulse relay module
• Mastering latching relays: A hands-on design guide
• Electromechanical relays: an old-fashioned component solves modern problems

The post A short tutorial on hybrid relay design appeared first on EDN.

Company to Highlight Broad Portfolio of Semiconductor and Passive Technologies in a Series of Reference Designs and Product Demos Focused on AI Servers, Smart Cockpits, Vehicle Computing Platforms, and More

Vishay Intertechnology, Inc. announced that the company will be showcasing its latest semiconductor and passive technologies at PCIM Asia 2025. In Booth N5, C48, visitors are invited to explore Vishay’s differentiated products and reference designs tailored to the rapidly evolving demands of AI infrastructure and electric vehicles (EV).

At PCIM Asia, Vishay’s exhibits will highlight the company’s solutions for server power supplies, DC/DC converters, power delivery units, BBUs, mainboards, and optical modules in AI infrastructure and applications, as well as smart cockpit and vehicle computing and ADAS platforms for next-generation EVs. To meet the needs of these high growth sectors, the company is focused on expanding its capacity and optimizing its global manufacturing footprint to broaden its portfolio.

Vishay AI solution components on display at PCIM Asia will include power MOSFETs with extremely low on-resistance in PowerPAK 8×8, 10×12, SO-8DC double-sided cooling—for high efficiency thermal management—1212-F, and SO-8S packages; microBUCK buck regulators with 4.5 V to 60 V input; 50 A VRPower integrated power stages in the thermally enhanced PowerPAK MLP55-31L package; SiC diodes in TO-220, TO-247, D2PAK, SMA, and SlimSMA packages; TVS in DFN and SlimSMA packages; surface-mount TMBS rectifiers with ultra-low forward voltage drop of 0.38 V; IHLE series inductors with integrated e-field shields for maximum EMI reduction that handle high transient current spikes without saturation, and low DCR and high voltage power inductors; the T55 vPolyTan polymer tantalum chip capacitor with ultra-low ESR; thin film chip resistors with operating frequencies up to 70 GHz; Power Metal Strip resistors with high power density and low ohmic values, TCR, inductance, and thermal EMF; and PTC thermistors with high energy absorption levels up to 340 J.

Highlighted Vishay automotive solutions will consist of reference designs, demos and components solutions. Reference designs for automotive applications will include active discharge circuits for 400 V and 800 V; a 22 kW bidirectional 800 V to 800 V power converter for OBCs; an intelligent battery shunt built on WSBE Power Metal Strip resistors, with low TCR, inductance, and thermal EMF, and a CAN FD interface for 400 V / 800 V systems; a 4 kW bidirectional 800 V to 48 V power converter for auxiliary power; a compact 800 V power distribution solution; and a 48 V eFuse.

Highlighted Vishay Automotive Grade components for smart cockpit, vehicle computing and ADAS, and other automotive applications include fully integrated proximity, ambient light, force, gesture, and transmissive optical sensors; Ethernet ESD protection diodes; surface-mount diodes in the eSMP package; MOSFETs with extremely low on-resistance in PowerPAK 8x8LR, SO-10LR, 1212, and SO-8L packages; IHLP series low profile high current power inductors that handle high transient current spikes without saturation; the T51 vPolyTan polymer tantalum chip capacitor with ultra-low ESR; metallized polypropylene DC-Link film capacitors with high temperature operation up to +125 °C; and Automotive Grade EMI suppression safety capacitors with the ability to withstand temperature humidity bias (THB) testing of 85 °C / 85 % for 1000 h.

The post Vishay Intertechnology to Showcase Solutions for AI and EV Applications at PCIM Asia 2025 appeared first on ELE Times.

The need for sustainable mobile networks is stronger today than ever before. Increasing operational costs, tightening environmental rules, and international commitments toward sustainable development are all compelling telecom operators, as well as infrastructure vendors, to repaint their perspective on how networks are created and powered. Since wireless infrastructure uses more than any other type of infrastructure in terms of energy use, the transition from 5G to 6G is an opportunity to make sustainability one of the prime considerations alongside speed and capacity.

According to ITU-R Recommendation M.2160 on the IMT-2030/6G Framework, sustainability remains one of the key aspirations, where mobile systems are expected to be designed so that they use minimum power, emit least greenhouse gases, and utilize their resources efficiently. Contrary to what happened in previous generations where energy efficiency was considered after the fact, 6G has the potential to incorporate green-by-design concepts from the start so as to deliver both excellent performance and little environmental impact.

Energy-Saving Features in 5G: Achievements and Limitations

Innovations such as RRC_INACTIVE mode, Idle Mode Signaling Reduction, Discontinuous Reception (DRX), Discontinuous Transmission (DTX), and Carrier Aggregation control helped reduce unnecessary signaling and lower energy use.

The later 5G releases enhanced on such features as:

• Dynamic SSB transmission control based on cell load.
• On-Demand SIB1 broadcasting.
• Cell switch-off and micro-sleep for base stations.
• Improved RRC_INACTIVE mobility.
• Partial activation of antenna ports.
• BWP operation for UEs.
• Dynamic PDCCH monitoring control.
• SCell dormancy in carrier aggregation.
• Low-power receivers for UEs.

However, some structural shortcomings exist: for instance, frequent SSB bursts (every 20 ms) allow only shallow sleep, and persistent antenna activation wastes energy even when traffic is low. Many legacy UEs are incapable of supporting these new modes of efficiency, and high-traffic scenarios still do not have robust network-level mechanisms for saving energy. These gaps necessitate a fundamental rethink of energy efficiency in 6G.

Less ON, More OFF is the Principle on Which 6G Is Built:

In 6G, energy efficiency will become a paramount design concern instead of a mere secondary feature. The phrase “Less ON, More OFF” becomes the banner under which unnecessary transmissions are done away with and base stations and UEs are put to sleep when at all possible.

Samsung Research finds three main enablers:

Carrier-Dependent Capabilities

6G introduces Energy-Saving Network Access (ENA), which dynamically controls SSB transmission.

Multi-toned SSBs: Normal (NM-SSB), Energy-Saving (ES-SSB), and On-Demand (OD-SSB) provide extremely flexible signaling in contrast to 5G-Fixed SSBs-on.

ES-SSB usually delays the transmission periodicity (e.g., 160 ms); the OD-SSBs are transmitted only on demand, reducing base station standby energy.

2. Dynamic Time/Frequency/Spatial/Power Adaptation

Here, DSA is the active adaptation of the number of active antennas and beam directions based on real-time demand.

It avoids over-provisioning and wasting idle power and is particularly applicable for high-frequency bands in which power scales with antenna density.

3. Energy-Aware Network Management and Exposure (EANF)

Interfacing with the central orchestration layer for real-time monitoring of energy consumption, in order to initiate power-aware policies for scheduling, load balancing, and carrier activation.

Further, in the realm of AI-RAN, better traffic predictions will enable the optimization of beam configurations and event-driven measurements, thereby also reducing signaling, and hence power consumption.

Energy Conservation for UEs in 6G

User devices remain at the core of the 6G energy-saving scheme. Network-UE joint power saving opens the way for more proactive strategies whereby the network predicts UE activity, traffic patterns, and battery status to join in coordinating wake-up intervals.

Some of these key innovations include:

• Ultra-low-power wake-up receivers that keep energy use at a minimum.
• Context-aware wake-up signals powered by ML techniques evaluating and adapting timing and frequency.
• Collaborative scheduling between the network and the UE to reduce idle consumption without degradation of user experience.

Performance and Energy Gains

Internal studies with 24-hour traffic profiles demonstrated:

• ENA cuts energy consumption by 43.37% at low traffic and reaches 20.3% average savings.
• DSA further reduces power consumption by another 14.4%, scaling the antenna ports with demand.
• Together, ENA + DSA can reach an energy saving of ~21.2% while also enhancing the user-perceived throughput (UPT) by up to 8.4%.

In this way, such results show that 6G energy savings are not just about switching off and saving power-they also include efficiency improvements and network responsiveness enhancements.

Conclusion:

Rather from being a small improvement, the 6G energy-saving vision represents a paradigm shift. Networks can enter low-power modes more frequently when ENA, DSA, and EANF cooperate, which minimises waste and maintains service quality. 6G offers faster and more dependable connectivity as well as a sustainable foundation for the upcoming ten years of wireless evolution by fusing AI-native intelligence, signalling innovation, and hardware flexibility.

(This article has been adapted and modified from content on Samsung.)

The post Towards Greener Connectivity: Energy-Efficient Design for 6G Networks appeared first on ELE Times.

Fan-out wafer-level packaging (FOWLP) is becoming a critical technology in advanced semiconductor packaging, marking a significant shift in system integration strategies. Industry analyses show 3D IC and advanced packaging make up more than 45% of the IC packaging market value, underscoring the move to more sophisticated solutions.

The challenges are significant—from thermal management and testing to the need for greater automation and cross-domain expertise—but the potential benefits in terms of performance, power efficiency, and integration density make these challenges worth addressing.

Figure 1 3D IC and advanced packaging make up more than 45% of the IC packaging market value. Source: Siemens EDA

This article explores the automation frameworks needed for successful FOWLP design and focuses on core design processes and effective cross-functional collaboration.

Understanding FOWLP technology

FOWLP is an advanced packaging method that integrates multiple dies from different process nodes into a compact system. By eliminating substrates and using wafer-level batch processing, FOWLP can reduce cost and improve yield. Because it shortens interconnect lengths, FOWLP packages offer lower signal delays and power consumption compared to conventional methods. They are also thinner, making them ideal for space-constrained devices such as smartphones.

Another key benefit is support for advanced stacking, such as placing DRAM above a processor. As designs become more complex, this enables higher performance while maintaining manageable form factors. FOWLP also supports heterogeneous integration, accommodating a wide array of die combinations to suit application needs.

The need for automation in FOWLP design

Designing with FOWLP exceeds the capabilities of traditional PCB design methods. Two main challenges drive the need for automation: the inherent complexity of FOWLP and the scale of modern layouts, racking up millions of pins and tens of thousands of nets. Manual techniques cannot reliably manage this complexity and scale, increasing the risk of errors and inefficiency.

Adopting automation is not simply about speeding up manual tasks. It requires a complete change in how design teams approach complex packaging design and collaborate across disciplines. Let’s look at a few of the salient ways to make this transformation successful.

1. Technology setup

All FOWLP designs start with a thorough technology setup. Process design kits (PDKs) from foundries specify layer constraints, via spans, and spacing rules. Integrating these foundry-specific rules into the design environment ensures every downstream step follows industry requirements.

Automation frameworks must interpret and apply these rules consistently throughout the design. Success here depends on close attention to detail and a deep understanding of both the foundry’s expectations and the capabilities of the design tools.

2. Assembly and floor planning

During assembly and floor planning, designers establish the physical relationships between dies and other components. This phase must account for thermal and mechanical stress from the start. Automation makes it practical to incorporate early thermal analysis and flag potential issues before fabrication.

Effective design partitioning is also critical when working with automated layouts. Automated classification and grouping of nets allow custom routing strategies. This is especially important for high-speed die-to-die interfaces, compared to less critical utility signals. The framework should distinguish between these and apply suitable methodologies.

3. Fan-out and routing

Fan-out and routing are among the most technically challenging parts of FOWLP design. The automation system must support advanced power distribution networks such as regional power islands, floodplains, or striping. For signal routing, the system needs to manage many constraints at once, including routing lengths, routing targets, and handling differential pairs.

Automated sequence management is essential, enabling designers to iterate and refine routing as requirements evolve. Being able to adjust routing priorities dynamically helps meet electrical and physical design constraints.

4. Final verification and finishing

The last design phase is verification and finishing. Here, automation systems handle degassing hole patterns, verifying stress and density requirements, and integrating dummy metal fills. Preparing data for GDS or OASIS output is streamlined, ensuring the final package meets manufacturing and reliability standards.

Building successful automated workflows

For FOWLP automation flows to succeed, frameworks must balance technical power with ease of use. Specialists should be able to focus on their discipline without needing deep programming skills. Automated commands should have clear, self-explanatory names, and straightforward options.

Effective frameworks promote collaboration among package designers, layout specialists, signal and power integrity analysts, and thermal and mechanical engineers. Sharing a common design environment helps teams work together and apply their skills where they are most valuable.

A crucial role in FOWLP design automation is the replay coordinator. This person orchestrates the entire workflow, managing contributions from all team members as well as the sequence and dependencies of automated tasks, ensuring that all the various design steps are properly sequenced and executed.

To be effective, replay coordinators need a high-level understanding of the overall process and strong communication with the team. They are responsible for interpreting analysis results, coordinating adjustments, and driving the group toward optimal design outcomes.

The tools of the new trade

This successful shift in how we approach microarchitectural design requires new tools and technologies that support the transition from 2D to 3D ICs. Siemens EDA’s Innovator3D IC is a unified cockpit for design planning, prototyping, and predictive analysis of 2.5/3D heterogeneous integrated devices.

Innovator3D IC constructs a digital twin, unified data model of the complete semiconductor package assembly. By using system technology co-optimization, Innovator3D IC enables designers to meet their power, performance, area, and cost objectives.

Figure 2 Innovator3D IC features a unified cockpit. Source: Siemens EDA

FOWLP marks a fundamental evolution in semiconductor packaging. The future of semiconductor packaging lies in the ability to balance technological sophistication with practical implementation. Success with this technology relies on automation frameworks that make complex designs practical while enabling effective teamwork.

As industry continues to progress, organizations with robust FOWLP automation strategies will have a competitive advantage in delivering advanced products and driving the next wave of semiconductor innovation.

Todd Burkholder is a Senior Editor at Siemens DISW. For over 25 years, he has worked as editor, author, and ghost writer with internal and external customers to create print and digital content across a broad range of EDA technologies. Todd began his career in marketing for high-technology and other industries in 1992 after earning a Bachelor of Science at Portland State University and a Master of Science degree from the University of Arizona.

Chris Cone is an IC packaging product marketing manager at Siemens EDA with a diverse technical background spanning both design engineering and EDA tools. His unique combination of hands-on design experience and deep knowledge of EDA tools provides him with valuable insights into the challenges and opportunities of modern semiconductor packaging, particularly in automated workflows for FOWLP.

Editor’s Notes

This is third and final part of the article series on 3D IC. The first part provided essential context and practical depth for design engineers working on 3D IC systems. The second part highlighted 3D IC design toolkits and workflows to demonstrate how the integration technology works.

Related Content

• 3D IC Design
• Thermal analysis tool aims to reinvigorate 3D-IC design
• Heterogeneous Integration and the Evolution of IC Packaging
• Tighter Integration Between Process Technologies and Packaging
• Advanced IC Packaging: The Roadmap to 3D IC Semiconductor Scaling

The post Automating FOWLP design: A comprehensive framework for next-generation integration appeared first on EDN.

Whether it be designing products and creative content or software engineering, artificial intelligence is steadily changing how we engineer and interact with technology. But although AI can speed up the development process, the real price of the measure lies in trusting its output, particularly when dealing with safety-critical applications. How can AI-generated software be ensured to be correct, secure, and efficient within real-world parameters?

Bosch Research recognizes the immense promise of the generation-and-execution approach in driving innovation and practical impact. This synthesis combines generative AI to suggest solutions and systematic checks to enforce correctness, safety, and performance. Balancing AI creativity occurs with a touch of strictness-a balance that lands well upon software engineering.

How Generate-and-Check Works

Think of solving a crossword puzzle: you may try out different words, but each suggestion is validated against the length of the clue and the letters already in place. Similarly, in software engineering, AI can generate new code or refactor existing code, while automated checks verify compliance with rules and desired outcomes.

Those rules can be either very simple like the coding style enforcement or highly advanced, like formal verification of software properties. From this perspective, rather than verifying every possible system state, safety, correctness, and adherence to requirements are ensured by verifying AI proposals.

Less error-prone AI assistance, and much less reliance on human supervision all the time.

Use Case 1: Smarter Code Refactoring

Refactoring is a perfect application for generate-and-check. The AI proposes improvements, e.g., migrating to more efficient frameworks, while automated checks verify the equivalence of the new version with the old code.

This approach is somewhat different from the traditional ones based mostly on unit tests as it guarantees behavioral invariance, i.e., that the refactored code behaves exactly the same but better in terms of maintainability or efficiency. Tools developed at Bosch Research allow you to profile this too, to make sure that performance has stayed the same or improved after the changes have been made.

Use Case 2: Reliable Software Translation

On the other hand, software translation remains an area where AI excels but demands human monitoring. The idea of translating legacy code into a safer or new-age language seems nice, but oftentimes traditional transpilers would fail in preserving the idiomatic essence of the target environment.

Yet with generate-and-check, AIs can translate idiomatically while automated tools check for functional correctness, safety, security, and performance. This finally offers a chance to modernize codebases in great bulk without stealthily inserting vulnerabilities.

Embedding into the Developer Workflow

AI becomes valuable for developers if their tools support integration with existing toolchains. Generate-and-check would appear in various forms:

IDE plugins for quick, low-latency assistance during coding.

Background workflows for longer tasks, such as legacy migration, where AI proposals can be rolled out as pull requests. Each PR can provide evidence, such as performance metrics or validation checks, preserving developers’ agency albeit under automated rigor.

This guarantees that AI will continue to be an aid rather than a substitute, offering reliable recommendations while developers make the ultimate choices.

Looking Forward:

The generate-and-check paradigm is a mentality shift for trustworthy AI in software engineering, not merely a technical approach. AI offers safer, better, and more efficient software development by combining its generating capacity with reliable verification.

(This article has been adapted and modified from content on Bosch.)

The post Building Trustworthy Software with AI: The Generate-and-Check Paradigm appeared first on ELE Times.

Here’s a pair of 99.9985 kHz crystals from an HP3571A spectrum analyzer. They were used in a 5-stage filter that set the IF bandwidth, and are simply gold-plated flat quartz plates with centered contacts on both sides, packaged like vacuum tubes. Manufactured by Northern Engineering Laboratories, Burlington WI submitted by /u/10ppb [link] [comments]

This article explores the concept of indirect FM generation and the basic operation of the Armstrong modulator.

Hi everyone!, after 10 months of working and improving on my accelerator, its finally complete! This device accelerates a magnet in circles using 4 electromagnets and hall effect sensors (I've tried IR sensors but failed😔). Those sensors detect the magnet and then a N-MOSFET switches the coil on and off at the right moment, which leads to acceleration of the magnet. I've also used a 12v--> 5v voltage regulator and for one reason or another I've put a quick ignition and fire hazard or whatever you call it on the voltage regulator. If you wanna know more, or just wanna see the accelerator in action you find the youtube video at the KIWIvolt youtube channel. I'm thinking to make a part 2 in which the magnet is a sphere and thinking of replacing the breadboard with a PCB. If you have any other ideas or wishes please let me know so i can adjust it, to perfect my accelerator even further. submitted by /u/Affectionate-Play484 [link] [comments]

submitted by /u/avionic_Railcar [link] [comments]

So i used HEF4094BP, i did the same circuit in this video 4094 shift register long time ago, then in 2022 i bought raspberry pi pico, and in this year i write a long code with MicroPython to count from 1 to 9 and repeat the loop, but i need to optimise it next time. submitted by /u/HichmPoints [link] [comments]

Over the last few weeks I’ve worked on an Arduino board connected through an ADC converter into 3 magnetometers. They are set orthogonally to one another (around the clear box) so that the magnetic field strength and direction at a given point can be found. The whole lot gets power through a USB cable that allows you to model the direction and strength in python. It’s been an absolute blast building it :) submitted by /u/ArticleWonderful2374 [link] [comments]

submitted by /u/AutoModerator
[link] [comments]

Left: 1974 (Matsushita Electric) Right: 2021 (Rubycon) Both 16V 1,000μF. Same voltage rating and capacitance, but shrunk this much in about 50 years. submitted by /u/NEET_FACT0RY [link] [comments]

For a biochemical project of mine I needed a very precise scale. The ones I bought were underwhelming, so I decided to just solder one myself. The sensitivity is kind of ridiculous. Sitting near the scale, I can see my heartbeat in the signal when streamed to a PC. Someone walking on a different floor makes the reading jump — and I live in a concrete building. The coil can lift about 20 g. With different coils, you could trade off dynamic range vs. precision. For my purposes, the precision is already overkill. Components were about $100 total. The most expensive part was the neodymium magnet. The principle is electromagnetic force restoration. A 110 Ω coil suspended on a lever lever sits above a neodymium ring magnet. The lever height is held constant by a feedback loop that uses an IR photointerrupter. The current required to hold the weight is directly proportional to the mass. For current sensing I used a 10 Ω shunt resistor (RJ711, 5 ppm/°C TCR) and a 24-bit ADC (ADS1232). The signal is read by an Arduino Nano and displayed on a small LCD (SLC0801B). The photointerrupter is built from a generic IR LED and IR photodiode. The LED is driven with a constant current source (using a 2N7000 MOSFET), while the photodiode is reverse-biased for fast response. The circuit runs from a low-drift 2.0 V reference (REF5020), which provides a stable reference for the ADC. After dividing it to 0.5 V, it also biases the photodiode stage and provides the ADC’s negative input. The coil current is controlled with an N-channel power MOSFET (IRF540N) acting as a low-side driver, operated in its ohmic region. Its gate is driven by the photointerrupter circuit. Zero-drift op-amps (OPA187) buffer the reference voltages, drive the photointerrupter, and control the coil current. I also added a capacitive touch button for tare, so you don’t have to touch the scale directly — that’s surprisingly important at this sensitivity. The schematic looks a bit op-amp heavy, but it’s actually pretty straightforward. Challenges and possible improvements - The lever tends to oscillate, so the feedback loop has to be very fast. A lighter lever with a higher resonant frequency would help, and might require a lower-gate-capacitance MOSFET. - All components in the feedback path need low temperature coefficients to minimize drift. - To fully eliminate drift, one would need to monitor and compensate for coil temperature, photointerrupter temperature, as well as ambient air temperature, humidity, and pressure (for buoyancy effects). - A parallel guide system will eventually be needed so measurements are independent of where the weight is placed on the lever. This build definitely requires some electronics background, so it’s not a first-project type of thing. But if you’re comfortable with soldering and op-amps, it’s very doable. Hope you like it 🙂 submitted by /u/sir_alahp [link] [comments]

This was a brain fart moment upon finding out they were .25 watt, we needed 9 watt capable. This is a lovely bundle of 36 that has next to no resistance now 🤦 .... 20ohm submitted by /u/No-Release3675 [link] [comments]

Miss the old micro SD upgrade days submitted by /u/Nerfarean [link] [comments]

I've had an obsession with rockets/flight controllers and decided to make an open source flight controller from scratch (nicknamed Athena). I've added the Github repo/design files if anyone wants to take a closer look. 👉Github repo / Design files Features Triple MCU: STM32H753VIT6 (MPU), STM32H743VIT6 (TPU), STM32G474RET6 (SPU) 6 Pyro Channels: Direct 12V battery connection with fuse protection 6 PWM Channels: 2 for TVC (Thrust Vector Control), 4 for fin control Sensors: Triple ICM-45686 IMUs, LIS2MDLTR magnetometer, ICP-20100 & BMP388 barometers GNSS & Communication: NEO-M8U-06B GPS, LoRa RA-02 telemetry, Bluetooth DA14531MOD Storage: SD Card + Winbond W25Q256JV flash memory Power Management: 7.4-12V LiPo battery with BQ25703ARSNR charger, USB-C PD support 6-Layer PCB: Signal/GND/Power/Signal/GND/Signal submitted by /u/MinecraftPhd [link] [comments]

Built for battery-operated devices, the new CMOS op amp enables ultra-efficient signal conditioning in wearables, IoT, and compact sensing applications.