Новини світу мікро- та наноелектроніки

Weekly discussion, complaint, and rant thread

Reddit:Electronics - Сбт, 02/24/2024 - 18:00

Open to anything, including discussions, complaints, and rants.

Sub rules do not apply, so don't bother reporting incivility, off-topic, or spam.

Reddit-wide rules do apply.

To see the newest posts, sort the comments by "new" (instead of "best" or "top").

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Vishay Intertechnology Launches Innovative Half-Bridge IGBT Power Modules

ELE Times - Сбт, 02/24/2024 - 11:28

Vishay Intertechnology, Inc. has unveiled a groundbreaking line of five new half-bridge IGBT power modules, housed in the newly redesigned INT-A-PAK package. These modules, namely the VS-GT100TS065S, VS-GT150TS065S, VS-GT200TS065S, VS-GT100TS065N, and VS-GT200TS065N, are built on Vishay’s cutting-edge Trench IGBT technology. They offer designers a choice between two technologies — low VCE(ON) or low Eoff — to mitigate conduction or switching losses in high-current inverter stages for transportation, energy, and industry applications.

These half-bridge devices are a fusion of Trench IGBTs and Gen IV FRED Pt anti-parallel diodes, featuring soft reverse recovery characteristics. The modules’ INT-A-PAK package now boasts a new gate pin orientation, ensuring compatibility with the 34 mm industry-standard package and facilitating mechanical drop-in replacements.

The modules find applications in various fields, including power supply inverters for railway equipment, energy generation, distribution, storage systems, welding equipment, motor drives, and robotics. Specifically designed for reducing conduction losses in output stages for TIG welding machines, these devices offer a collector-to-emitter voltage of ≤ 1.07 V at +125 °C and rated current. For high-frequency power applications, the other variants boast low switching losses, with Eoff down to 1.0 mJ at +125 °C and rated current.

Key features of the VS-GT100TS065S include:

  • VCES: 650 V
  • Continuous Collector Current (IC DC), TC = 80 °C: 185A
  • VCE(on) at 100 A, 25 °C: 1.05 V
  • Chip Level VCE(on) at 100 A, 25 °C: 0.98 V
  • Speed: DC to 1 kHz
  • Package: INT-A-PAK
  • Circuit Configuration: Half-bridge

These modules offer a 650 V collector-to-emitter voltage, continuous collector current ranging from 100 A to 200 A, and low junction-to-case thermal resistance. UL-approved file E78996 can be directly mounted to heatsinks and provide low EMI to diminish snubbing requirements.

Introducing these advanced half-bridge IGBT power modules marks a significant advancement in the field, promising enhanced efficiency and performance across various industrial sectors.

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ISSCC 2024: Inside AMD’s Zen 4c—The Area-Optimized Cloud Computing Core

AAC - Сбт, 02/24/2024 - 02:00
AMD engineers presented their latest innovation this week at ISSCC, showing the world how they realized the Zen 4c CPU core.

I had “fun” routing it

Reddit:Electronics - Птн, 02/23/2024 - 20:57
I had “fun” routing it

It’s not the finish product. I used copper pours instead of wide traces for my power supplies. For the screen shot I deleted the GND. Done in KiCad 7.

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ISSCC 2024: MediaTek Presents Neural Visual-Enhancement Engine for IoT

AAC - Птн, 02/23/2024 - 20:00
We kick off our ISSCC coverage with MediaTek's neural visual-enhancement engine, a device that bests competitors with its energy and area efficiency—making it an appealing up-and-comer for smart devices.

Joule Thief

Reddit:Electronics - Птн, 02/23/2024 - 19:58
Joule Thief

The first joule thief i made.

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No luck😔

Reddit:Electronics - Птн, 02/23/2024 - 19:08
No luck😔

No luck on turning this hfsstc without ociloscope. Have been working on it for 6 months

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An MCU test chip embeds 10.8 Mbit STT-MRAM memory

EDN Network - Птн, 02/23/2024 - 14:51

A prototype MCU test chip with a 10.8 Mbit magnetoresistive random-access memory (MRAM) memory cell array—fabricated on a 22-nm embedded MRAM process—claims to accomplish a random read access frequency of over 200 MHz and a write throughput of 10.4 MB/s at a maximum junction temperature of 125°C.

Renesas, which developed circuit technologies for this embedded spin-transfer torque MRAM (STT-MRAM) test chip, presented details about it on February 20 at the International Solid-State Circuits Conference 2024 (ISSCC 2024) held on 18-22 February in San Francisco. The Japanese chipmaker has designed this embedded MRAM macro to bolster read access and write throughput for high-performance MCUs.

Figure 1 The MCU test chip incorporates a 10.8-Mbit embedded MRAM memory cell array. Source: Renesas

Microcontrollers in endpoint devices are expected to deliver higher performance than ever, especially in Internet of Things (IoT) and artificial intelligence (AI) applications. Here, the CPU clock frequencies of high-performance MCUs are in the hundreds of MHz, and to achieve greater performance, read speeds of embedded non-volatile memory need to be increased to minimize the gap between them and CPU clock frequencies.

However, MRAM has a smaller read margin than the flash memory used in conventional MCUs, which makes high-speed read operation more difficult. At the same time, MRAM is faster than flash memory for write performance because it requires no erase operation before performing write operations. That’s why shortening write times is desirable not only for everyday use but also for cost reduction of writing test patterns in test processes and writing control codes by end-product manufacturers.

Renesas has developed circuit technologies for an embedded STT-MRAM test chip with fast read and write operations to address this design conundrum.

Faster read and write

First, take MRAM reading, which is generally performed by a differential amplifier or sense amplifier to determine which of the memory cell current or reference current is larger. But because the difference in memory cell currents between the 0 and 1 states—read window—is smaller for MRAM than for flash memory, the reference current must be precisely positioned in the center of the read window for faster reading.

So, Renesas introduces two mechanisms to achieve faster read speed. First, it aligns the reference current in the center of the window according to the actual current distribution of the memory cells for each chip measured during the test process. Second, it reduces the offset of the sense amplifier.

Another challenge that Renesas engineers have overcome relates to conventional configurations, where large parasitic capacitance in the circuits is used to control the voltage of the bitline, so it doesn’t rise too high during read operations. While it slows the reading process, Renesas has introduced a Cascode connection scheme to reduce parasitic capacitance and speed up reading. That allows design engineers to realize the random read operation at more than 200 MHz frequencies.

Next, for write operation, it’s worth mentioning that Renesas announced in December 2021 that it has improved write throughput by applying write voltage simultaneously to all bits in a write unit using a relatively low write voltage generated from the external voltage (I/O power) of the MCU through a step-down circuit. Then, it used a higher write voltage only for the remaining few bits that could not be written.

Figure 2 In late 2021, Renesas announced an increase in the write speed of an STT-MRAM test chip manufactured on a 16-nm node.

Now, while power supply conditions used in test processes and by end-product manufacturers are stable, Renesas has relaxed the lower voltage limit of the external voltage. As a result, by setting the higher step-down voltage from the external voltage to be applied to all bits in the first phase, write throughput can be improved 1.8-fold. A faster write speed will contribute to more efficient code writing in endpoint devices.

Test chip evaluation

The prototype MCU test chip combines the above two enhancements to offer a 10.8 Mbit MRAM memory cell array fabricated using a 22-nm embedded process. The evaluation of the prototype chip validated that it achieved a random read access frequency of over 200 MHz and a write throughput of 10.4 MB/s.

The MCU test chip also contains 0.3 Mbit of one-time programmable (OTP) memory that uses MRAM cell breakdown to prevent falsification of data. That makes it capable of storing security information. However, writing to OTP requires a higher voltage than writing to MRAM, which makes it more difficult to perform writing in the field, where power supply voltages are often less stable. Here, Renesas suppressed parasitic resistance within the memory cell array, which in turn, makes writing in the field possible.

Renesas has vowed to further increase the capacity, speed, and power efficiency of MRAM.

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u-blox Launches NORA-W4 Module: Next-Generation IoT Connectivity Solution

ELE Times - Птн, 02/23/2024 - 12:55

In a move set to revolutionize the Internet of Things (IoT) landscape, u-blox has introduced the NORA-W4 module, a cutting-edge solution tailored to meet the evolving demands of IoT applications. This state-of-the-art module, hailed as the most cost-effective and reliable single-band Wi-Fi 6 module on the market, promises to redefine connectivity standards for battery-operated devices.

Designed to address the burgeoning needs of various sectors including smart homes, asset tracking, healthcare, and industrial automation, the NORA-W4 module integrates advanced wireless technologies including Wi-Fi 6, Bluetooth Low Energy 5.3, Thread, and Zigbee. Boasting compact dimensions of just 10.4 x 14.3 x 1.9 mm, the module is built on the Espressif ESP32-C6 System-on-Chip, offering a single-band tri-radio Wi-Fi 6 solution.

One of the standout features of the NORA-W4 module is its ability to enable battery-powered IoT nodes to operate directly over Wi-Fi, eliminating the necessity for a Bluetooth gateway and subsequently reducing system-level costs. This attribute is particularly advantageous for wireless battery-operated sensors and similar applications, promising enhanced efficiency and cost-effectiveness.

Key features of the NORA-W4 module include:

  • Integration of Wi-Fi 6, Bluetooth Low Energy 5.3, Zigbee, and Thread connectivity.
  • Support for Wi-Fi 6 Target Wake Time and low-power peripherals.
  • Comprehensive security features ensure enhanced protection.
  • Compact design with various antenna options and compatibility with other NORA modules.
  • Support for the Matter protocol over Wi-Fi or Thread.
  • Global certification ensures usability worldwide.

Emphasizing the significance of Wi-Fi 6 technology, the module is optimized for IoT environments, offering reduced network congestion and improved throughput in crowded settings such as factories and warehouses. Moreover, its compatibility with Wi-Fi 4 ensures seamless integration with existing infrastructure.

Security remains a top priority, with the module incorporating features such as secure boot, a trusted execution environment, and flash encryption. Offering six variants catering to diverse requirements, the module provides options for open CPU or u-connectXpress, antenna pin or PCB antenna, and 4MB or 8MB flash memory.

Early samples of the NORA-W4 module are currently available, with volume production slated to commence in the second half of 2024. This milestone launch underscores u-blox’s commitment to delivering innovative solutions that push the boundaries of IoT connectivity.

 

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Rohde & Schwarz presents 3GPP 5G conformance test solutions with smallest footprint on the market

ELE Times - Птн, 02/23/2024 - 11:44

Rohde & Schwarz is introducing two new setups for 5G RF and RRM conformance testing. The R&S TS8980S-4A is a cost-efficient single-box solution tailored to 3GPP inband test cases, and the R&S TS8980FTA-3A is a single-rack solution covering all inband and out-of-band test cases. No other solution on the market offers the same capabilities in such a compact format.

The R&S TS8980 is an official 5G conformance test platform approved by the Global Certification Forum (GCF) and the PCS Type Certification Review Board (PTCRB). Chipset, modem and end device manufacturers as well as test houses can use the test system to perform RF (TP298) and RRM (TP296) tests in line with 3GPP specifications. The platform also meets the test requirements of network operators and regulatory bodies.

Rohde & Schwarz has developed two new setups for its successful R&S TS8980 family: the R&S TS8980S-4A and the R&S TS8980FTA-3A. These solutions meet the market requirements for reduced hardware and a smaller footprint.

The single-box solution R&S TS8980S-4A is a fully automated conformance test system for performing validated conformance test cases up to 8 GHz and 4 carrier aggregation (4 CA). Based on an enhanced R&S CMX500 one-box 5G signalling tester (OBT), it is a cost-efficient solution that supports 3GPP RX/TX inband conformance test cases, demodulation and radio resource management (RRM) test cases. Customers can also upgrade their R&S CMX500 to an R&S TS8980S-4A. This solution is particularly attractive for 5G device manufacturers who want to perform inband testing in-house and outsource out-of-band testing to a test house. The automation is based on the R&S Contest software platform with an intuitive GUI, advanced tools for fast debugging and a sophisticated report manager for big data analysis and cloud services.

The single-rack solution R&S TS8980FTA-3A is the most compact conformance test solution on the market. It supports the full range of both inband and out-of-band test cases and the entire device certification process for RF and RRM, covering 5G NR as defined by 3GPP and carrier acceptance specifications. Typically, these capabilities require a two-rack solution. Now, Rohde & Schwarz has succeeded in reducing the footprint of this test system to a single rack setup, allowing it to be installed in laboratories with limited floor space.

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Renesas Develops New AI Accelerator for Lightweight AI Models and Embedded Processor Technology to Enable Real-Time Processing

ELE Times - Птн, 02/23/2024 - 11:08
Renesas Electronics Corporation (TSE: 6723), a premier supplier of advanced semiconductor solutions, today announced the development of embedded processor technology that enables higher speeds and lower power consumption in microprocessor units (MPUs) that realize advanced vision AI. The newly developed technologies are as follows: (1) A dynamically reconfigurable processor (DRP)-based AI accelerator that efficiently processes lightweight AI models and (2) Heterogeneous architecture technology that enables real-time processing by cooperatively operating processor IPs, such as the CPU. Renesas produced a prototype of an embedded AI-MPU with these technologies and confirmed its high-speed and low-power-consumption operation. It achieved up to 16 times faster processing (130 TOPS) than before the introduction of these new technologies, and world-class power efficiency (up to 23.9 TOPS/W at 0.8 V supply).
Amid the recent spread of robots into factories, logistics, medical services, and stores, there is a growing need for systems that can autonomously run in real-time by detecting surroundings using advanced vision AI. Since there are severe restrictions on heat generation, particularly for embedded devices, higher performance and lower power consumption are required in AI chips. Renesas developed new technologies to meet these requirements and presented these achievements on February 21, at the International Solid-State Circuits Conference 2024 (ISSCC 2024), held between February 18 and 22, 2024 in San Francisco.
The technologies developed by Renesas are as follows:
(1)  An AI accelerator that efficiently processes lightweight AI models
As a typical technology for improving AI processing efficiency, pruning is available to omit calculations that do not significantly affect recognition accuracy. However, it is common that calculations that do not affect recognition accuracy randomly exist in AI models. This causes a difference between the parallelism of hardware processing and the randomness of pruning, which makes processing inefficient.
To solve this issue, Renesas optimized its unique DRP-based AI accelerator (DRP-AI) for pruning. By analyzing how pruning pattern characteristics and a pruning method are related to recognition accuracy in typical image recognition AI models (CNN models), we identified the hardware structure of an AI accelerator that can achieve both high recognition accuracy and an efficient pruning rate and applied it to the DRP-AI design. In addition, software was developed to reduce the weight of AI models optimized for this DRP-AI. This software converts the random pruning model configuration into highly efficient parallel computing, resulting in higher-speed AI processing. In particular, Renesas’ highly flexible pruning support technology (flexible N: M pruning technology), which can dynamically change the number of cycles in response to changes in the local pruning rate in AI models, allows for fine control of the pruning rate according to the power consumption, operating speed, and recognition accuracy required by users.
This technology reduces the number of AI model processing cycles to as little as one-sixteenth of pruning incompatible models and consumes less than one-eighth of the power.
(2)  Heterogeneous architecture technology that enables real-time processing for robot control
Robot applications require advanced vision AI processing for recognition of the surrounding environment. Meanwhile, robot motion judgment and control require detailed condition programming in response to changes in the surrounding environment, so CPU-based software processing is more suitable than AI-based processing. The challenge has been that CPUs with current embedded processors are not fully capable of controlling robots in real-time. That is why Renesas introduced a dynamically reconfigurable processor (DRP), which handles complex processing, in addition to the CPU and AI accelerator (DRP-AI). This led to the development of heterogeneous architecture technology that enables higher speeds and lower power consumption in AI-MPUs by distributing and parallelizing processes appropriately.
A DRP runs an application while dynamically changing the circuit connection configuration between the arithmetic units inside the chip for each operation clock according to the processing details. Since only the necessary arithmetic circuits operate even for complex processing, lower power consumption and higher speeds are possible. For example, SLAM (Simultaneously Localization and Mapping), one of the typical robot applications, is a complex configuration that requires multiple programming processes for robot position recognition in parallel with environment recognition by vision AI processing. Renesas demonstrated operating this SLAM through instantaneous program switching with the DRP and parallel operation of the AI accelerator and CPU. This resulted in about 17 times faster operation speeds and about 12 times higher operating power efficiency than the embedded CPU alone.
Operation Verification
Renesas created a prototype of a test chip with these technologies and confirmed that it achieved the world-class, highest power efficiency of 23.9 TOPS per watt at a normal power voltage of 0.8 V for the AI accelerator and operating power efficiency of 10 TOPS per watt for major AI models. It also proved that AI processing is possible without a fan or heat sink.
Utilizing these results helps solve heat generation due to increased power consumption, which has been one of the challenges associated with the implementation of AI chips in a variety of embedded devices such as service robots and automated guided vehicles. Significantly reducing heat generation will contribute to the spread of automation into various industries, such as the robotics and smart technology markets. These technologies will be applied to Renesas’ RZ/V series—MPUs for vision AI applications.

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SK Siltron CSS secures conditional commitment from US DOE for $544m loan

Semiconductor today - Птн, 02/23/2024 - 09:06
Compound semiconductor wafer maker SK Siltron CSS of Auburn, MI, USA (a subsidiary of South Korea-based wafer manufacturer SK Siltron, a part of South Korea's second-largest conglomerate SK Group) has secured a conditional commitment from the US Department of Energy (DOE) for a loan of up to $544m...

Arm Unveils ‘Best Generation of Neoverse Technology Yet’

AAC - Птн, 02/23/2024 - 02:00
Arm's third generation of its Neoverse IP is designed to maximize TCO for intensive workloads and support new technologies like chiplets.

BLDC motor driver prolongs battery life

EDN Network - Чтв, 02/22/2024 - 20:58

A three-phase BLDC motor driver, the AOZ32063MQV from AOS, offers an input voltage range of 5 V to 60 V and 100% duty cycle operation. The IC enables efficient motor operation, while its low standby power helps extend the battery life of cordless power tools and e-bikes.

The AOZ32063MQV drives three half-bridges consisting of six N-channel power MOSFETs for three-phase applications. It has a high-side sink current of 1A and a maximum source current of 0.8 A. A power-saving sleep mode lowers current consumption to just 1 µA.

Along with an integrated bootstrap diode, the driver provides adjustable dead-time control and a fault indication output. Onboard protection functions include input undervoltage, short-circuit, overcurrent, and thermal shutdown. The device operates over a temperature range of -40°C to +125°C.

Housed in a 4×4-mm QFN-28L package, the AOZ32063MQV costs $1.55 in lots of 1000 units. It is available in production quantities, with a lead time of 24 weeks.

AOZ32063MQV product page

Alpha & Omega Semiconductor 

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100-V MLCC is among the industry’s smallest

EDN Network - Чтв, 02/22/2024 - 20:58

Murata expands its GJM022 series of high-Q multilayer ceramic capacitors (MLCCs) with a 100-V device that is just 0.4×0.2 mm (L×W). The MLCC is intended for high-frequency module applications, such as those used in cellular communication infrastructure.

Exhibiting high-Q, low-loss performance, the miniature capacitor enables electronic engineers to overcome packaging limitations, while maintaining optimal performance. A high-temperature guarantee also gives designers greater positioning freedom. The MLCC helps ensure reliable long-term operation, even in close proximity to power semiconductors that radiate heat.

The GJM022 can be used for a wide variety of applications, including impedance matching and DC cutting within RF modules for base stations. In such implementations, the capacitor’s high-Q value and low equivalent series resistance (ESR) contribute to improving power amplifier efficiency and lowering power consumption.

Engineering samples of the GJM022 100-V chip capacitor are available in limited production. The product will move to full stocked production in the next several weeks. A datasheet for the device was not available at the time of this announcement. For information on the GJM series of high-Q MLCCs, click the product page link below.

GJM series product page  

Murata

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Development kit pairs RISC-V and FPGA

EDN Network - Чтв, 02/22/2024 - 20:58

The PolarFire SoC Discovery Kit from Microchip makes RISC-V and FPGA design accessible to a wider range of embedded engineers. This low-cost development platform allows students, beginners, and seasoned engineers alike to leverage RISC-V and FPGA technologies for creating their designs.

The Discovery Kit is built around the PolarFire MPFS095T SoC FPGA, which embeds a quad-core RISC-V processor that supports Linux and real-time applications. It also packs 95,000 FPGA logic elements. A large L2 memory subsystem can be configured for performance or deterministic operation and supports an asymmetric multiprocessing mode.

An embedded FP5 programmer is included for FPGA fabric programming, debugging, and firmware development. The development board also provides a MikroBUS expansion header for Click boards and a 40-pin Raspberry Pi connector, as well as a MIPI video connector. Expansion boards are controlled using protocols like I2C and SPI. 

The PolarFire SoC Discovery Kit costs $132 for the general public and $99 when purchased through Microchip’s Academic Program. Production kit shipments are expected to commence mid-April 2024.

PolarFire Soc Discovery Kit product page

Microchip Technology

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SP4T switches offer high isolation up to 8.5 GHz

EDN Network - Чтв, 02/22/2024 - 20:57

pSemi announced production readiness of two UltraCMOS SP4T RF switches that operate from 10 MHz to 8.5 GHz with high channel isolation. According to the manufacturer, the PE42445 and PE42446 switches integrate seamlessly into 4G and 5G base stations and massive MIMO architectures. They can provide digital pre-distortion feedback loops and transmitter monitoring signal paths to prevent interference and maintain signal integrity.

 

Both the PE42445 and PE42446 offer >60 dB isolation at 4 GHz and operate over an extended temperature range of -40°C to +125°C. Additionally, the devices provide low insertion loss across the band, high linearity of 65 dBm IIP3, and a fast switching time of 200 ns.  The SP4T switches are manufactured on the company’s UltraCMOS process, a variation of silicon-on insulator technology.

The PE42445 comes in a 3×3-mm, 20-lead LGA package, while the PE42446 is housed in a 4×4-mm, 24-lead LGA package. Sales inquiries can be submitted using the product page links below.

PE42445 product page

PE42446 product page 

pSemi

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